CN101764066A - Manufacturing process for a quad flat non-leaded chip package structure - Google Patents
Manufacturing process for a quad flat non-leaded chip package structure Download PDFInfo
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- CN101764066A CN101764066A CN 200910004407 CN200910004407A CN101764066A CN 101764066 A CN101764066 A CN 101764066A CN 200910004407 CN200910004407 CN 200910004407 CN 200910004407 A CN200910004407 A CN 200910004407A CN 101764066 A CN101764066 A CN 101764066A
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- square flat
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- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 238000003466 welding Methods 0.000 claims description 64
- 238000000059 patterning Methods 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 54
- 238000005538 encapsulation Methods 0.000 claims description 45
- 239000011248 coating agent Substances 0.000 claims description 31
- 238000000576 coating method Methods 0.000 claims description 31
- 239000000084 colloidal system Substances 0.000 claims description 13
- 238000012856 packing Methods 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000000969 carrier Substances 0.000 claims description 2
- 238000000465 moulding Methods 0.000 abstract description 4
- 150000001875 compounds Chemical class 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 113
- 238000012545 processing Methods 0.000 description 19
- 238000005530 etching Methods 0.000 description 4
- 238000007711 solidification Methods 0.000 description 4
- 230000008023 solidification Effects 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 208000003351 Melanosis Diseases 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000006087 Brown hydroboration reaction Methods 0.000 description 1
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical group [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000011417 postcuring Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Chips are bonded onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed and the molding compound and the patterned conductive layer are separated.
Description
Technical field
The invention relates to a kind of chip encapsulating manufacturing procedure, and particularly relevant for a kind of square flat non-pin (Quad Flat Non-leaded, QFN) encapsulation procedure.
Background technology
Along with the high development of semi-conductor industry, electronics and semiconductor device are applied in the daily life widely, as aspects such as amusement, education, communications and transportation and electrical home appliances.Electronic product is towards design is complicated, size is little, in light weight and the development of hommization aspect, to bring the user more convenience.In encapsulating structure, lead frame is one of element of using always and is applied to multiple encapsulating products.Type with lead frame, quad flat package (Quad Flat Package, QFP) can be divided into I type pin quad flat package (quad flatpackage with " I " lead, QFI), the quad flat Chip Packaging of J type pin (quad flat packagewith " J " lead, QFJ) and square flat non-pin (Quad Flat Non-leaded, QFN) encapsulation.The pin of the lead frame of square flat non-pin encapsulation does not exceed the edge of encapsulating structure, so it has smaller volume.In addition, the square flat non-pin encapsulation has short signaling path and reaches signal transmission speed faster, therefore is one of main flow of low pin position (low pin count) structure dress kenel always.
Generally speaking, in the manufacture process of square flat non-pin encapsulation, can be on lead frame with a plurality of chip configuration, wherein lead frame comprises a plurality of interconnective pin set, and each chip by pin set institute around.Each chip sees through the routing processing procedure and is electrically connected at a pin set.Then, formation is in order at least one packing colloid of coated wire frame, chip and bonding wire.At last, see through the singulation processing procedure and form a plurality of square flat non-pin encapsulation, wherein the singulation processing procedure comprises punching press processing procedure (punch process) or sawing processing procedure (sawing process).
Summary of the invention
The invention provides a kind of square flat non-pin encapsulation procedure, it can produce the square flat non-pin encapsulation with less thickness.
The present invention proposes a kind of square flat non-pin encapsulation procedure.At first, the conductive layer with a plurality of grooves is provided and is positioned at a patterning welding cover layer on the conductive layer, wherein the patterning welding cover layer covers the groove of conductive layer.Remove the partially conductive layer to form a patterned conductive layer.The a plurality of chips of configuration on patterned conductive layer are so that patterning welding cover layer and chip are positioned at the same side of patterned conductive layer.See through many bonding wires chip is electrically connected at patterned conductive layer, its chips and bonding wire are positioned at the same side of patterned conductive layer.Form at least one packing colloid to coat patterned conductive layer, patterning welding cover layer, chip and bonding wire.Then, cut apart packing colloid and patterned conductive layer.
In one embodiment of this invention, the above-mentioned method that conductive layer with groove and patterning welding cover layer be provided comprises provides the conductive layer with groove.On conductive layer, form a welding cover layer.The patterning welding cover layer is to form a patterning welding cover layer, and wherein the patterning welding cover layer exposes the partially conductive layer.
In one embodiment of this invention, above-mentioned square flat non-pin encapsulation procedure, wherein a plurality of chip carriers and a plurality of pin are formed on patterned conductive layer.
In one embodiment of this invention, above-mentioned square flat non-pin encapsulation procedure, wherein a plurality of first openings and a plurality of second opening are formed on the patterning welding cover layer, and wherein first opening and second opening expose partially patterned conductive layer.
In one embodiment of this invention, the patterned conductive layer that exposes in second opening of above-mentioned chip configuration.
In one embodiment of this invention, above-mentioned square flat non-pin encapsulation procedure more comprises the adhesion coating of formation between chip and patterned conductive layer.
In one embodiment of this invention, above-mentioned adhesion coating is a B rank adhesion coating.
In one embodiment of this invention, above-mentioned B rank adhesion coating is formed on a back side of chip in advance.
In one embodiment of this invention, above-mentioned square flat non-pin encapsulation procedure, wherein before chip was attached at the patterning welding cover layer, B rank adhesion coating was formed on the patterning welding cover layer.
In one embodiment of this invention, above-mentioned groove is patterned welding cover layer and fills up.
In one embodiment of this invention, above-mentioned patterning welding cover layer is a B stratum.
In one embodiment of this invention, above-mentioned square flat non-pin encapsulation procedure, wherein a plurality of first openings are formed on the patterning welding cover layer, and wherein first opening exposes partially patterned conductive layer.
In one embodiment of this invention, above-mentioned chip configuration is on the patterning welding cover layer.
In one embodiment of this invention, above-mentioned patterning welding cover layer is a B stratum.
In one embodiment of this invention, above-mentioned square flat non-pin encapsulation procedure more comprises the adhesion coating of formation between chip and patterning welding cover layer.
In one embodiment of this invention, above-mentioned adhesion coating is a B rank adhesion coating.
In one embodiment of this invention, above-mentioned square flat non-pin encapsulation procedure more is included in and carries out on the conductive layer that a brown is handled or a melanism is handled.
Based on above-mentioned, square flat non-pin encapsulation procedure of the present invention, its square flat non-pin that produces encapsulation has the welding cover layer in order to reinforced structure intensity, so that patterned conductive layer can have less thickness.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Figure 1A to Fig. 1 H is that the processing procedure of the square flat non-pin encapsulation of one embodiment of the invention is analysed and observe flow chart.
The main element symbol description:
100,100 ': the square flat non-pin encapsulation
110: conductive layer
110 ': patterned conductive layer
110a: chip carrier
110b: pin
112: first surface
114: second surface
118: the first weld pads
120: the patterning welding cover layer
122: the first openings
124: the second openings
130: chip
132: active surface
134: the back side
136: the second weld pads
140: adhesion coating
150: bonding wire
160,160 ': packing colloid
R: groove
Embodiment
Figure 1A to Fig. 1 H is that the processing procedure of the square flat non-pin encapsulation of one embodiment of the invention is analysed and observe flow chart.Please refer to Figure 1A, the conductive layer 110 with a first surface 112 and a second surface 114 is provided.Then, partly remove the conductive layer 110 that is positioned at presumptive area, on the first surface 112 of conductive layer 110, to form a plurality of recess R.In the present embodiment, be to form the recess R that is positioned at first surface 112 through etching partially (half-etching) processing procedure or punching press (stamping) processing procedure.
Please refer to Figure 1B, on the first surface 112 of conductive layer 110, form and have a patterning welding cover layer 120 of a plurality of first openings 122 and a plurality of second openings 124, be patterned welding cover layer 120 and fill up so that be formed at the recess R of the first surface 112 of conductive layer 110.The patterning welding cover layer 120 that is formed on the part first surface 112 defines a plurality of first weld pads 118.In a preferred embodiment, more can carry out brown (brown oxidation) processing or melanism (black oxidation) on conductive layer 110 handles, with the surface roughness of increase conductive layer 110, and then the adhesion between lifting conductive layer 110 and the patterning welding cover layer 120.
In an alternate embodiments, compared to Figure 1B on the first surface 112 of conductive layer 110, form a patterning welding cover layer 120 with a plurality of first openings 122 and a plurality of second openings 124, also can on the first surface 112 of conductive layer 110, form a patterning welding cover layer (not illustrating) that has a plurality of first openings 122 and do not have a plurality of second openings 124.
In the present embodiment, patterning welding cover layer 120 can be a B rank film (B-staged film) (also being weldering cover film), and first opening 122 was formed before or after patterning welding cover layer 120 is attached at conductive layer 110.In an alternate embodiments, a liquid weldering overcoat layer can be coated on the first surface 112 of conductive layer 110, and with its curing and patterning forming patterning welding cover layer 120, and liquid weldering overcoat layer can be the liquid weldering in B rank overcoat layer.In an alternate embodiments, more can see through first surface 112 preforming (pre-molding) molding for epoxy resin compound (epoxy moldingcompound), and it is carried out solidifying (post mold curing) processing procedure to form patterning welding cover layer 120 after the demoulding at conductive layer 110.
In addition, in a preferred embodiment, can see through plating (plating) processing procedure and on first weld pad 118, form an electroplated conductive layer (not illustrating).Electroplated conductive layer can be nickel gold lamination or other metal level that is suitable for.It should be noted that and before or after patterning welding cover layer 120 is formed at conductive layer 110, to form electroplated conductive layer.
Please refer to Fig. 1 C, remove to form a patterned conductive layer 110 ' through the second surface 114 of etching to conductive layer 110, wherein patterned conductive layer 110 ' has a plurality of chip carrier 110a and a plurality of pin 110b.The method that partially conductive layer 110 is removed from second surface 114 for example is back of the body etching (back-sideetching) processing procedure.
Please refer to Fig. 1 D, a plurality of chips 130 are adhered to patterned conductive layer 110 ', then and form many bonding wires 150 to electrically connect chip 130 and patterned conductive layer 110 ', wherein each chip 130 has an active surperficial back side 134 of 132, active relatively surperficial 132 and is disposed at a plurality of second weld pads 136 of active surperficial 132.Each chip 130 is adhered to patterned conductive layer 110 ' through being positioned at the adhesion coating 140 between chip 130 and the patterned conductive layer 110 '.In an alternate embodiments, chip 130 can not see through adhesion coating 140 and is adhered on the patterning welding cover layer 120, wherein patterning welding cover layer 120 is for being formed at the B rank welding cover layer (do not have second and open 124 this moment) on pin 110b and the chip carrier 110a, and patterning welding cover layer 120 before configuring chip 130 not by full solidification.
In the present embodiment, can see through routing (wire bonding) processing procedure and form bonding wire 150, so that each bonding wire 150 is electrically connected between one first weld pad 118 and one second weld pad 136.Bonding wire 150 for example is a gold thread.
In this enforcement, adhesion coating 140 for example is a B rank adhesion coating (B-staged adhesive layer).B rank adhesion coating 140 can be ABLESTIK 8008,8008HT, 6200,6201,6202C or HITACHI Chemical CO., the SA-200-6 that Ltd. provides, SA-200-10.In one embodiment of this invention, B rank adhesion coating 140 is the back side that is formed on a wafer.After cut crystal, can obtain having a plurality of chips 130 of the adhesion coating 140 that is positioned at the back side 134.Therefore, B rank adhesion coating 140 is suitable for a large amount of productions.In addition, can see through spin coating, printing or other processing procedure that is suitable for to form B rank adhesion coating 140.Adhesion coating 140 is the back side 134 that is formed on chip 130 in advance.Specifically, can provide a wafer earlier with a plurality of chips 130 of arranging in array.Then, form a second order adhesion coating at the back side 134 of chip 130, and it is partly solidified with it to see through heating (heating) or ultraviolet irradiation (UV irradiation), to form B rank adhesion coating 140.In addition, also can be attached at patterned conductive layer 110 ' before, go up at patterned conductive layer 110 ' and form B rank adhesion coating 140 at chip 130.
In the present embodiment, B rank adhesion coating 140 is to be attached at patterned conductive layer 110 ' full solidification afterwards at chip 130, or after see through the back and solidify (post curing) and handle and full solidification, or coat the back full solidification at packed colloid 160.
Please refer to Fig. 1 E, form at least one packing colloid 160 that coats patterned conductive layer 110 ', patterning welding cover layer 120, chip 130 and bonding wire 150.The material of packing colloid 160 for example is epoxy resin (epoxyresin).
Please refer to Fig. 1 F, coat a packing colloid 160 of patterned conductive layer 110 ', patterning welding cover layer 120, chip 130 and bonding wire 150 compared to the formation of Fig. 1 E, also can form a plurality of packing colloids 160 ' that coat patterned conductive layer 110 ', patterning welding cover layer 120, chip 130 and bonding wire 150.
Please refer to Fig. 1 G and Fig. 1 H, see through the singulation processing procedure and form a plurality of square flat non-pin encapsulation 100 (being illustrated in Fig. 1 G) or a plurality of square flat non-pin encapsulation 100 ' (being illustrated in Fig. 1 H), wherein the singulation processing procedure comprises punching press (punch) processing procedure or sawing processing procedure.Illustrate as Fig. 1 G, square flat non-pin of the present invention encapsulation 100 mainly comprises a patterned conductive layer 110 ', a patterning welding cover layer 120, a chip 130, many bonding wires 150 and a packing colloid 160.Patterned conductive layer 110 ' has a first surface 112, wherein patterned conductive layer 110 ' has a chip carrier 110a and around a plurality of pin 110b of chip carrier 110a, and patterning welding cover layer 120 extends to zone between chip carrier 110a and the pin 110b from the first surface 112 of patterned conductive layer 110 '.Patterning welding cover layer 120 is disposed at first surface 112, and wherein patterning welding cover layer 120 exposes part first surface 112.Chip 130 is disposed at patterned conductive layer 110 ', and wherein patterning welding cover layer 120 and chip 130 are positioned at the same side of patterned conductive layer 110 '.Bonding wire 150 is electrically connected at the patterned conductive layer 110 ' that chip 130 and patterning welding cover layer 120 expose.Packing colloid 160 coats patterned conductive layer 110 ', patterning welding cover layer 120, chip 130 and bonding wire 150.
In sum, compared to traditional square flat non-pin encapsulation procedure, the square flat non-pin encapsulation that square flat non-pin encapsulation procedure of the present invention produces, it has the welding cover layer in order to reinforced structure intensity, so that patterned conductive layer can have less thickness.In addition, the square flat non-pin encapsulation has less integral thickness and lower manufacturing cost, so that production capacity (throughput) obtains to promote.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (16)
1. square flat non-pin encapsulation procedure comprises:
Conductive layer with a plurality of grooves is provided and is positioned at a patterning welding cover layer on this conductive layer, wherein this patterning welding cover layer covers those grooves of this conductive layer;
Remove the partially conductive layer to form a patterned conductive layer;
The a plurality of chips of configuration on this patterned conductive layer are so that this patterning welding cover layer and those chips are positioned at the same side of this patterned conductive layer;
See through many bonding wires those chips are electrically connected at this patterned conductive layer, wherein those chips and those bonding wires are positioned at the same side of this patterned conductive layer;
Form at least one packing colloid to coat this patterned conductive layer, this patterning welding cover layer, those chips and those bonding wires; And
Cut apart this packing colloid and this patterned conductive layer.
2. square flat non-pin encapsulation procedure as claimed in claim 1 is characterized in that, provides this conductive layer with those grooves and the method for this patterning welding cover layer to comprise:
Conductive layer with those grooves is provided;
On this conductive layer, form a welding cover layer; And
This welding cover layer of patterning is to form a patterning welding cover layer, and wherein this patterning welding cover layer exposes this conductive layer of part.
3. square flat non-pin encapsulation procedure as claimed in claim 1 is characterized in that, a plurality of chip carriers and a plurality of pin are formed on this patterned conductive layer.
4. square flat non-pin encapsulation procedure as claimed in claim 1 is characterized in that, a plurality of first openings and a plurality of second opening are formed on this patterning welding cover layer, and wherein those first openings and those second openings expose this patterned conductive layer of part.
5. square flat non-pin encapsulation procedure as claimed in claim 4 is characterized in that, this patterned conductive layer that those chip configuration expose in those second openings.
6. square flat non-pin encapsulation procedure as claimed in claim 1 is characterized in that, more comprises the adhesion coating of formation between those chips and this patterned conductive layer.
7. square flat non-pin encapsulation procedure as claimed in claim 6 is characterized in that, this adhesion coating is a B rank adhesion coating.
8. square flat non-pin encapsulation procedure as claimed in claim 7 is characterized in that, this B rank adhesion coating is formed on a back side of this chip in advance.
9. square flat non-pin encapsulation procedure as claimed in claim 7 is characterized in that, before those chips were attached at this patterning welding cover layer, this B rank adhesion coating was formed on this patterning welding cover layer.
10. square flat non-pin encapsulation procedure as claimed in claim 1 is characterized in that, those grooves are filled up by this patterning welding cover layer.
11. square flat non-pin encapsulation procedure as claimed in claim 1 is characterized in that, this patterning welding cover layer is a B stratum.
12. square flat non-pin encapsulation procedure as claimed in claim 1 is characterized in that, a plurality of first openings are formed on this patterning welding cover layer, and wherein those first openings expose this patterned conductive layer of part.
13. square flat non-pin encapsulation procedure as claimed in claim 12 is characterized in that, those chip configuration are on this patterning welding cover layer.
14. square flat non-pin encapsulation procedure as claimed in claim 13 is characterized in that, this patterning welding cover layer is a B stratum.
15. square flat non-pin encapsulation procedure as claimed in claim 1 is characterized in that, more comprises the adhesion coating of formation between those chips and this patterning welding cover layer.
16. square flat non-pin encapsulation procedure as claimed in claim 15 is characterized in that, this adhesion coating is a B rank adhesion coating.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/270,679 | 2008-11-13 | ||
| US12/270,679 US7803667B2 (en) | 2005-07-21 | 2008-11-13 | Manufacturing process for a quad flat non-leaded chip package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101764066A true CN101764066A (en) | 2010-06-30 |
Family
ID=42495150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910004407 Pending CN101764066A (en) | 2008-11-13 | 2009-02-12 | Manufacturing process for a quad flat non-leaded chip package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101764066A (en) |
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2009
- 2009-02-12 CN CN 200910004407 patent/CN101764066A/en active Pending
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Open date: 20100630 |