CN101764065A - Preparing method of p-type stannous oxide ditch film transistors - Google Patents
Preparing method of p-type stannous oxide ditch film transistors Download PDFInfo
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- CN101764065A CN101764065A CN201010040097A CN201010040097A CN101764065A CN 101764065 A CN101764065 A CN 101764065A CN 201010040097 A CN201010040097 A CN 201010040097A CN 201010040097 A CN201010040097 A CN 201010040097A CN 101764065 A CN101764065 A CN 101764065A
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Abstract
The present invention discloses a preparing method of p-type stannous oxide ditch film transistors, and p-type conducting stannous oxide ditch layers are prepared by using electron beam evaporation technology and rapid thermal annealing technology. The preparing method is simple and controllable, and can realize low-temperature preparation. The p-type stannous oxide ditch film transistors have high field effect mobility, can be used for organic light-emitting diodes and development of oxide based compensating and logic circuits with low loss and the like, and have wide application prospects in the technical field of displays.
Description
Technical field
The present invention relates to the preparation method of thin-film transistor, relate in particular to a kind of preparation method of p type stannous oxide ditch film transistors.
Background technology
Thin-film transistor (TFT) generally is made of substrate, gate dielectric layer, channel layer, gate electrode, source electrode and drain electrode, comprise the TFT (as shown in Figure 1) of bottom grating structure and the TFT (as shown in Figure 2) of top gate structure, in LCD, be used as switch element and drive pixel, wherein Si base (amorphous Si or polycrystalline Si are raceway groove) TFT occupies an leading position, but amorphous Si TFT and polycrystalline Si TFT have unsurmountable shortcoming, such as photic performance degradation, lower field-effect mobility, aperture opening ratio is limited and power consumption is more high.Thereby the development of Display Technique objectively requires to substitute Si material and development of new TFT.
The broad stopband oxide is transparent and have high electron mobility at visible light wave range, and they are made into TFT, will improve the aperture opening ratio of active display matrix greatly, thereby improves brightness, reduces power consumption, makes TFT have higher field-effect mobility.The realization of broad stopband oxide TFT has milestone inthe to transparent electronics.Adopt the Thin Film Transistor (TFT) of broad stopband oxide, can realize that field-effect mobility is greater than 10cm as channel layer
2V
-1s
-1, on-off ratio is near 10
8Etc. stable performance.Yet most oxide semiconductors are n type conductions.So the application of transparent film transistor (TTFT) just is limited in the n channel type.
Therefore, the p type oxide-base TFT of development high field-effect mobility becomes one of problem that also enjoys challenge of greatest concern at present.The good news is that the development of p type oxide TFT has obtained breakthrough in 2008: with tin oxide (SnO
2APPLIED PHYSICS LETTERS 92,122113,2008), nickel oxide (NiO, APPLIED PHYSICS LETTERS 92,242107,2008) and stannous oxide (SnO, APPLIED PHYSICS LETTERS 93,032113,2008) etc. the broad stopband oxide is seen in report in succession as the p type TFT of channel layer.Yet tin oxide, nickel oxide are very low as the field-effect mobility of the p type TFT of channel layer, less than 0.011cm
2V
-1s
-1Though stannous oxide is as the field-effect mobility of the p type TFT of channel layer two magnitudes that exceed than the above two, but its channel layer is the stabilized with yttrium oxide zirconium dioxide (yttria-stabilizedzirconia in costliness, YSZ) the SnO epitaxial film that utilizes single-phase SnO ceramic target and pulsed laser deposition high temperature (575 ℃) to prepare on (001) substrate, transistor then is a top gate structure, this method is to the preparation requirement of source material (single-phase SnO target), the requirement of used substrate kind and temperature and the operation of equipment and subsequent technique (preparation of electrode) required all than higher, thereby preparation difficulty height, and also cause preparation cost to improve.
Summary of the invention
The technical problem that will solve required for the present invention is: how to reduce with stannous oxide as the preparation difficulty of the p type channel thin-film transistor of channel layer and improve device performance.
For solving the problems of the technologies described above, the invention provides a kind of preparation technology's simple controllable, can realize the preparation method of the p type stannous oxide thin-film transistor of low temperature preparation.
A kind of preparation method of p type stannous oxide ditch film transistors comprises step:
(1) selects substrate, and carry out the preparation of gate dielectric layer and gate electrode;
(2) adopt electron beam evaporation equipment and tin oxide evaporation material, under the underlayer temperature condition, on gate dielectric layer, deposit the stannous oxide noncrystal membrane, carry out thermal anneal process then, finish the preparation of channel layer;
(3) prepare source electrode and drain electrode, make the p type stannous oxide ditch film transistors of bottom grating structure.
A kind of preparation method of p type stannous oxide ditch film transistors comprises step:
(1) selects substrate, adopt electron beam evaporation equipment and tin oxide evaporation material,, carry out thermal anneal process then, finish the preparation of channel layer at underlayer temperature condition deposit stannous oxide noncrystal membrane;
(2) preparation gate dielectric layer;
(3) prepare source electrode, drain electrode and gate electrode, make the p type stannous oxide ditch film transistors of top gate structure.
Described thermal anneal process is a quick thermal annealing process, and quick thermal annealing process is a kind of economy and the easy to operate technology that is usually used in the device reprocessing.The present invention finds, when adopting quick thermal annealing process to prepare p type stannous oxide ditch layer, annealing temperature is crossed low or too short channel layer of time presents high-impedance state, then carrier concentration is too high for the too high or overlong time of temperature, these all can make the film crystal tube failure, in order to guarantee that SnO forms effective channel layer, the condition of described thermal anneal process is: annealed 1 minute to 15 minutes in 350 ℃ to 400 ℃ in Ar gas atmosphere.
As preferably:
Described underlayer temperature is a room temperature to 300 ℃.But the low temperature preparation is one of distinguishing feature of broad stopband oxide-base device.
Described source electrode and drain electrode are all selected Ni/Au double-level-metal membrane electrode for use.Ni and SnO film directly can form good Ohmic contact, and Au has advantages of excellent stability, is difficult for oxidation, can form good the contact with lead-in wire.
Described source electrode and drain electrode can adopt commercially available purity be 99.9% graininess Ni evaporation material and Au evaporation expect to utilize electron beam evaporation equipment successively evaporation on conventional electrodes, make Ni/Au double-level-metal membrane electrode.
Described substrate, gate dielectric layer, source electrode, drain electrode and gate electrode all can be selected the existing material in this area for use, utilize this area prior preparation method to be prepared.
The present invention has following advantage:
The preparation of the preparation of channel layer and source electrode and drain electrode is all carried out in electron beam evaporation deposition equipment in the thin-film transistor of the present invention, use electron beam evaporation deposition equipment with respect to existing pulsed laser deposition, but have advantage such as the even film forming of large tracts of land simple to operate.
The present invention is by two-step method, and promptly first low temperature prepares, and back quick thermal annealing process makes that the preparation technology of SnO channel layer is simpler, and the preparation difficulty reduces.
The present invention can use tin oxide (SnO
2) granular ceramic post sintering evaporation material is source material, no given shape restriction need not to carry out specific source material preliminary treatment work, can directly commercial purchase, thereby the reduction of the preparation difficulty of raw material.
The present invention has no special requirements to the selection of substrate, need not epitaxial relationship between deposited film and the substrate, thereby adopt the transistor of the present invention's preparation can adopt top gate structure and bottom grating structure, the latter is with respect to the former, the preparation technology of its electrode is more simple, even need not to adopt photoetching technique, reduce the difficulty of device preparation and saved cost; Next adopts the present invention can realize the preparation of transparent transistors on transparent on-monocrystalline substrate such as glass, has expanded its range of application.
The transistor of the present invention's preparation has higher field-effect mobility, and it can be used for Organic Light Emitting Diode and development oxide-base low-loss compensation logic circuit etc., and application prospect is very wide in the display technology field.
Description of drawings
Fig. 1 is the structural representation of the thin-film transistor of bottom grating structure;
Fig. 2 is the structural representation of the thin-film transistor of top gate structure;
Fig. 3 is the structural representation of the prepared p type stannous oxide ditch film transistors of the embodiment of the invention;
Fig. 4 is the curve of output that adopts the p type stannous oxide ditch film transistors of 350 ℃ of annealing temperature preparations in the embodiment of the invention;
Fig. 5 is the curve of output that adopts the p type stannous oxide ditch film transistors of 400 ℃ of annealing temperature preparations in the embodiment of the invention;
Among Fig. 4 and Fig. 5, the transverse axis and the longitudinal axis are represented source-drain voltage V respectively
DSWith source-drain current I
DS
Fig. 6 is the transfer curve of the p type stannous oxide ditch film transistors of 400 ℃ of annealing preparations in the embodiment of the invention, and the transverse axis and the longitudinal axis are represented gate voltage V respectively
GWith source-drain current I
DS, solid line is used for linear extrapolation and obtains transistorized threshold voltage V
Th
Fig. 7 is the linear zone field-effect mobility μ of the p type stannous oxide ditch film transistors of 400 ℃ of annealing preparations in the embodiment of the invention
LinWith gate voltage V
GGraph of relation.
Embodiment
Present embodiment has been described at SiO
2The process of p type SnO channel thin-film transistor (as shown in Figure 3) of preparation bottom grating structure on the/Si substrate, and 300 ℃ of transistorized performances to 450 ℃ of annealing are compared analysis.
Step 1: select the commercial thermal oxidation silicon chip SiO that buys
2/ p
+-Si (100) is as substrate, wherein SiO
2Layer is as gate dielectric layer, and thickness is 190nm, simultaneously the highly doped p of p type
+-Si substrate can be used as gate electrode again;
Step 2: adopt electron beam evaporation equipment and tin oxide evaporation material, deposit the stannous oxide noncrystal membrane of 100nm under the room temperature condition on gate dielectric layer, carry out thermal anneal process thereafter under Ar gas atmosphere, annealing temperature is 300 ℃～450 ℃, per 50 ℃ of temperature spots, annealing time is 10min;
Step 3: adopt electron beam evaporation equipment and Al template to prepare Ni/Au source electrode and Ni/Au drain electrode, the raceway groove long (L) and wide (W) between leak in the source is respectively 150 μ m and 7500 μ m, makes p type stannous oxide ditch film transistors.
Adopt semiconductor parameter instrument (Keithley 4200) that channel layer transistorized output and transfer characteristic of quick thermal annealing process under different temperatures of above-mentioned preparation characterized respectively, adopt the method for I-V test that the resistivity of channel layer is analyzed simultaneously.
The result shows that the transistors that channel layer is annealed respectively all do not show the field effect feature under 300 ℃ and 450 ℃.X-ray diffraction spectrum characterization result and resistivity analysis in conjunction with channel layer find that amorphous SnO film have many faults of construction in the film before the crystallization, thereby its resistivity is very high, reaches 10 350 ℃ of annealing beginning crystallization
4Ω cm magnitude, thereby cause transistor not show the field effect feature; And SnO begins to resolve into SnO after 450 ℃ of annealing
2And Sn, the resistivity of film is less than 0.1 Ω cm, and carrier concentration is too high in this explanation raceway groove, and transistor is difficult to show the field effect feature equally.After 350 ℃ of medium temperatures and 400 ℃ of annealing, the mobility in hole is relative with concentration moderate in the channel layer, thereby respective transistor all observed p type field-effect transistor feature, as shown in Figure 4 and Figure 5.Comparatively speaking, the performance of 400 ℃ of annealed crystal pipes (as shown in Figure 5) is better than the performance (as shown in Figure 4) of 350 ℃ of annealed crystal pipes.Still because the hole concentration too high relatively (resistivity is about 2 Ω cm) in the latter SnO channel layer causes transistor to be difficult to turn-off (the about 5 μ A of cut-off current), on-off ratio is lower for this.
Transistor 400 ℃ of annealing has shown optimum performance, as shown in Figure 6 and Figure 7.Transistorized saturation region field-effect mobility μ
SatWith linear zone field-effect mobility μ
LinCan calculate by following formula respectively: μ
Sat=2LI
DS/ WC
0(V
G-V
Th)
2, μ
Lin=(dI
Ds/ dV
G) (L/WC
0V
DS), I wherein
DS, V
G, V
DS, V
Th, C
0, the raceway groove that is respectively between the long and source-drain electrode of raceway groove between source-drain current, gate voltage, source-drain voltage, threshold voltage, gate medium unit-area capacitance, the source-drain electrode of L and W is wide.
Can analyze from transistorized transfer characteristic curve and to draw this transistorized V
ThBe respectively-3.5V and 200 μ with on-off ratio
SatWith maximum μ
LinBe respectively 0.46cm
2V
-1s
-1And 0.87cm
2V
-1s
-1, its size is the transistorized field-effect mobility (μ of raceway groove with what reported with the SnO epitaxial film
Sat=0.7cm
2V
-1s
-1And μ
Lin=1.3cm
2V
-1s
-1) comparable.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (5)
1. the preparation method of a p type stannous oxide ditch film transistors comprises step:
(1) selects substrate, and carry out the preparation of gate dielectric layer and gate electrode;
(2) adopt electron beam evaporation deposition equipment and tin oxide evaporation material, under the underlayer temperature condition, on gate dielectric layer, deposit the stannous oxide noncrystal membrane, carry out thermal anneal process then, finish the preparation of channel layer;
Wherein, described thermal anneal process condition is: annealed 1 minute to 15 minutes in 350 ℃ to 400 ℃ in Ar gas atmosphere;
(3) prepare source electrode and drain electrode, make the p type stannous oxide ditch film transistors of bottom grating structure.
2. the preparation method of a p type stannous oxide ditch film transistors comprises step:
(1) selects substrate, adopt electron beam evaporation deposition equipment and tin oxide evaporation material,, carry out thermal anneal process then, finish the preparation of channel layer at underlayer temperature condition deposit stannous oxide noncrystal membrane;
Wherein, described thermal anneal process condition is: annealed 1 minute to 15 minutes in 350 ℃ to 400 ℃ in Ar gas atmosphere;
(2) preparation gate dielectric layer;
(3) prepare source electrode, drain electrode and gate electrode, make the p type stannous oxide ditch film transistors of top gate structure.
3. the preparation method of p type stannous oxide ditch film transistors as claimed in claim 1 or 2 is characterized in that, described underlayer temperature is a room temperature to 300 ℃.
4. the preparation method of p type stannous oxide ditch film transistors as claimed in claim 1 or 2 is characterized in that, described source electrode and drain electrode are Ni/Au double-level-metal membrane electrode.
5. the preparation method of p type stannous oxide ditch film transistors as claimed in claim 4 is characterized in that, the Ni/Au double-level-metal film on described source electrode and the drain electrode carries out in electron beam evaporation deposition equipment.
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