CN106206736B - A kind of transistor and the method for constructing its model - Google Patents
A kind of transistor and the method for constructing its model Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000005457 optimization Methods 0.000 claims description 13
- 238000010276 construction Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 20
- 238000004088 simulation Methods 0.000 abstract description 13
- 238000012360 testing method Methods 0.000 abstract description 12
- 239000010410 layer Substances 0.000 description 72
- QHGNHLZPVBIIPX-UHFFFAOYSA-N tin(II) oxide Inorganic materials [Sn]=O QHGNHLZPVBIIPX-UHFFFAOYSA-N 0.000 description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 230000000875 corresponding effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000002245 particle Substances 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 229910021389 graphene Inorganic materials 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000011160 research Methods 0.000 description 4
- 229910052711 selenium Inorganic materials 0.000 description 4
- 229910052717 sulfur Inorganic materials 0.000 description 4
- 239000005864 Sulphur Substances 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- -1 sulphur compound Chemical class 0.000 description 3
- 229910009053 Sn—O—Sn Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
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- 239000011229 interlayer Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical group [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 150000004770 chalcogenides Chemical class 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical compound [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
- 229910052976 metal sulfide Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
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- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The present invention provides a kind of transistor, which includes Si substrate, channel layer, source electrode and drain electrode, the insulating layer being covered in above channel layer and the grid on insulating layer；Wherein channel layer is the monoatomic layer SnO with semiconductor conductive characteristic, and source and drain extremely has the diatomic layer SnO of metallic conduction characteristic.The present invention also provides a kind of methods by calculating and simulating the model of building transistor.The transistor provided by the invention improves the Ohmic contact of channel layer Yu source-drain electrode side wall since channel layer and source-drain electrode use single two-dimensional material SnO, greatly reduces the contact resistance of the two, improves the thermal diffusivity of transistor；Pass through simulation test, it was demonstrated that transistor has high electron mobility.
Description
Technical field
The present invention relates to a kind of transistors being made of homogenous material tin monoxide, belong to transistor arts.
Background technique
From the 1970s, under the driving of Moore's Law, transistor constantly to miniaturization, is entered and is received
The metrical scale epoch.Traditional silicon-based transistor even can achieve 3nm, several atoms more likely occurs to single atomic crystal
Pipe.However, heat dissipation problem caused by equipment high integration is also further serious due to the influence of contact resistance and leakage current.Moreover,
For the transistor of several atoms, electron mobility is also less than silicon or alternative semiconductor.
It is thus proposed that a kind of possible method, is exactly using two dimensional crystal material as basis material.It is understood that material
The dimension of material and the correlated performance of material are closely bound up.For two-dimensional material, charge transmission is limited in plane, due to quantum
Confinement effect makes it with many interesting properties.Graphene just has electrically and thermally property well so that its
Transparent conductor, high mobility field effect transistor on have very big application prospect.Although graphene has very high at room temperature
Mobility (at room temperature, 105cm2V-1S-1), still, it does not have band gap, this makes it be difficult to apply to digital field effect transistor.
Therefore, it is badly in need of finding a kind of two-dimensional material substitute other than graphene, such as stratiform transient metal sulfide/oxidation at present
Object.These materials are most of all to have certain band gap, therefore being considered can be fine in terms of developing next-generation electronic device
Ground substitutes graphene.
General two-dimensional material, their interlayer have Van der Waals interaction, there is very strong covalent/ion in layer
Key, so that it is with many special physicochemical properties.Currently, for tin list chalcogenide (SnX; X = O, S,
Se, or Te) research of the class material in terms of two-dimensional confinement is also seldom.
Tin is in tin list sulphur compound (SnX;X=O, S, Se, or Te) in electronic structure be 4d105s25p0,
Two electronics of middle tin have given sulphur/oxygen atom.This kind of material includes the two-dimensional material of three peacekeepings.The 5s electricity of tin in this kind of material
Son is not engaged in bonding and forms unshared electron pair.In SnO, these unshared electron pairs are directed toward interlayer, lead to dipole
Interaction between dipole, so that SnO layers of Van der Waals spacing is 2.52.And it is this not at share electron pair
The activity very little in other monosulfides, this makes SnO have unique property compared with other SnX compounds.Therefore,
SnO forms the layer structure of Sn-O-Sn sequence in [001] crystal orientation.Tetragonal lattice, the lattice of unit cell are belonged to for block-like SnO
Constant is a=b=3.8 and c=4.84, belongs to P4/nmm space group.
SnO, which is widely studied, to be applied to prepare high mobility p track thin film transistor (TFT) and CMOS device.Especially appropriate
Under the conditions of, it is as the ideal chose for developing CMOS device, because it has ambipolar conduction.But SnO is limited in two dimension
Research in terms of domain almost without.
Summary of the invention
It is led for the electron mobility of the existing technology encountered in transistor miniaturization process is low, contact resistance is high
The problems such as poor radiation of cause, the present invention is directed to design a kind of transistor, which can be realized height while miniaturization
Electron mobility, good thermal diffusivity.
Based on foregoing invention purpose, the present inventor is by the methods of calculating and simulation in tin list sulphur compound
(SnX;X=O, S, Se, or Te) in seek the building that a kind of two-dimensional material carries out transistor, and meet constructed crystalline substance
Body pipe can be realized the goal of the invention of high electron mobility, good thermal diffusivity while miniaturization.The present inventor passes through anti-
Multiple research calculates and the electrical properties of the nearly two-dimensional confinement of test SnO, obtain monoatomic layer SnO with semiconductor property and
Diatomic layer SnO with metalline.As a result, the technical solution of the present invention is as follows: constructing a kind of transistor, transistor includes:
Si substrate, the channel layer for being formed in Si substrate front surface and source electrode and drain electrode, the insulating layer being covered in above channel layer and
Grid on insulating layer；Wherein channel layer forms Electricity Federation with source electrode and drain electrode respectively around source electrode and drain electrode and in side wall
It connects；And channel layer is the monoatomic layer SnO with semiconductor conductive characteristic, source electrode and drain electrode is double with metallic conduction characteristic
Atomic layer SnO.
The present invention is different using the electric conductivity of different atom number of plies SnO, uses homogenous material SnO as constructed transistor
Channel layer, source electrode and drain electrode, such channel layer and source-drain electrode are in the Ohmic contact that the electrical contact of side wall is homojunction side wall, pole
The big contact resistance for reducing the two, so that constructed transistor has good thermal diffusivity；On the other hand, channel layer with
The Ohmic contact of the homojunction side wall of source-drain electrode improves electronics in the mobility at interface, realizes the invention of high electron mobility
Purpose.
The present invention also provides a kind of construction methods of transistor model, comprising the following steps:
1) Si unit cell is chosen, structure optimization is carried out to it.
2) selecting step 1) optimization after Si substrate, on its (111) face construct monoatomic layer SnO, carry out structure optimization,
And calculate its electrical properties；
3) selecting step 1) optimization after Si substrate, on its (111) face construct diatomic layer SnO, carry out structure optimization,
And calculate its electrical properties；
According to electrical properties possessed by the SnO of the obtained different atomic layers of step 2 and step 3), it is served as a contrast with Si
Bottom, insulating layer, grid are modeled, obtained transistor model.
Detailed description of the invention
Fig. 1 is structural model figure used in the calculating simulation of embodiment 1.Wherein 1 is layer of hydrogen atoms, and 2 be substrate silicon, 3
It is monoatomic layer SnO for diatomic layer SnO, 4.
Fig. 2 is transistor arrangement designed by the present invention.
Fig. 3 is the energy band diagram of the monoatomic layer SnO constructed on (111) face of Si substrate.
Fig. 4 is the energy band diagram of the diatomic layer SnO constructed on (111) face of Si substrate.
Fig. 5 is to carry out the illustraton of model that Current Voltage changes performance simulation test to transistor of the present invention.
Wherein in Fig. 2 and Fig. 5,5 be transistor substrate, and 6 be channel layer, and 7 be source electrode, and 8 be drain electrode, and 9 be insulating layer, and 10 are
Grid, 11 be pole plate.
Fig. 6 is that the test of Current Voltage performance simulation is carried out to transistor of the present invention, and when bias is 0.1V, electric current is with gate voltage
The test result figure of variation.
Fig. 7 be to transistor of the present invention carry out the test of Current Voltage performance simulation, electric current with bias variations test knot
Fruit figure.
Specific embodiment
The present invention is further illustrated below in conjunction with drawings and the specific embodiments.It should be understood, however, that these embodiments are only
It is only for specifically describing use in more detail, but should not be understood as present invention is limited in any form.
Inventor utilizes tin list sulphur compound SnX(SnX;X=O, S, Se, or Te) electronic structure characteristic, with
And wherein SnO forms the layer structure of Sn-O-Sn sequence in [001] crystal orientation and has property only compared with other SnX compounds
Top grade feature studies property of the SnO in terms of two-dimensional confinement repeatedly, passes through calculating, simulation and structure optimization repeatedly
The methods of the diatomic layer SnO that constructs using the monoatomic layer SnO of semiconductor property as channel layer and with metalline be
The transistor of source-drain electrode.And tested by further performance simulation, it was demonstrated that channel layer, source-drain electrode constructed by the present invention are by list
The certain high electron mobility of transistor and good thermal diffusivity that one material SnO is formed.
Specifically, the example for constructing transistor described above is as follows.
Embodiment 1
1) Si primitive unit cell is chosen, wherein its lattice constant a=b=c.It selects three groups of lattice constants, after relaxation, calculates every group of lattice
Obtained energy and corresponding lattice constant are carried out Function Fitting by the corresponding energy of constant, obtain optimal lattice constant, and a=b=
c=2.715 Å。
2) SnO monoatomic layer is constructed on (111) face of Si substrate after step 1) optimization, take lattice constant a=b(z
Direction is vacuum layer, c=65.167) relaxation, corresponding energy is then calculated, optimal lattice constant a=b=3.840 are obtained,
c=65.167Å；Then its electrical properties are calculated.
3) SnO diatomic layer is constructed on (111) face of Si substrate after step 1) optimization, take lattice constant a=b(z
Direction is vacuum layer, c=65.167) relaxation, corresponding energy is then calculated, optimal lattice constant a=b=3.840 are obtained,
c=65.167Å；Then its electrical properties are calculated.
4) by step 2 3) SnO and the Si substrate of obtained monoatomic layer and diatomic layer according to gained electric conductivity into
Row modeling, designs transistor arrangement.Designed transistor is that channel layer and source-drain electrode are formed by homogenous material SnO, wherein ditch
Channel layer is the monoatomic layer SnO that step 2 obtains, and the diatomic layer SnO that source and drain extremely step 3) obtains, the Si of step 1) are crystalline substance
Body tube lining bottom.Such as attached drawing 1, which is inventor in above-mentioned steps 1)~3) structural model used in calculating simulation is carried out,
In sequentially consist of layer of hydrogen atoms, the substrate silicon of bottom, and the monoatomic layer SnO being formed on substrate silicon (111) face
With diatomic layer SnO, wherein layer of hydrogen atoms is to make whole system mould to connect extra silicon key during calculating simulation
The stable condition of crystalloid pipe in actual use.When constructing transistor, the structure used when attached calculating shown in FIG. 1 is simulated, such as
Attached drawing 2 show designed transistor arrangement, and Si constitutes the channel layer of transistor as transistor substrate 5, monoatomic layer SnO
6, diatomic layer SnO constitutes source electrode 7 and the drain electrode 8 of transistor, and SiO is covered on channel layer2As insulating layer 9, Yi Jiwei
Grid 10 above insulating layer.
In the present embodiment, it when the electrical properties that step 2 carries out monoatomic layer SnO are calculated and simulated, obtains such as Fig. 3
Monoatomic layer SnO energy band diagram, the SnO of the monoatomic layer on Si substrate (111) face is of approximately 0.4eV as we can see from the figure
Forbidden band, have semiconductive.When the electrical properties that step 3) carries out diatomic layer SnO are calculated and simulated, pair such as Fig. 4 is obtained
Atomic layer SnO energy band diagram, from the band structure that the diatomic layer SnO on Si substrate (111) face can be seen in the figure, conduction band with
Fermi level intersection, shows metallicity.The present invention is exactly characteristic different when utilizing SnO diatomic layer and monoatomic layer, structure
Build the transistor of channel layer and source-drain electrode with homogenous material.
Transistor performance verifying: by the method for simulation test transistor performance, the transistor of the present embodiment design is verified
Properties.
If the following table 1 is the conducting particles effective mass for the transistor various pieces by simplation verification, being calculated, pass through
Effective mass is tested to determine the mobility of conducting particles, effective mass is smaller, and reaction electron mobility is bigger.X-B, X- in figure
G, B-Z and B-X respectively indicates the direction of the high symmetric points meaning of first Brillouin-Zone, and X-B is 0) to be directed toward B from X(0.5 0.5
(0.5 0 0)；0) X-G is directed toward G (0 0 0) from X(0.5 0.5；0) 0) B-Z is directed toward Z(0 0.5 from B(0.5 0；B-X is from B
(0.5 0 0) it is directed toward X(0.5 0.5 0.5), by comparing it can be concluded that channel monoatomic layer SnO and source-drain electrode diatomic layer
In SnO, the hole effective mass i.e. particle more much smaller than substrate Si layer in the direction X-B is high in the mobility of the direction, therefore can
To determine that transistor that the present invention designs is conducive to improve the electric current from source electrode to drain electrode.Wherein in the direction particle migration of X-B
Rate is high, mainly the p orbit coupling due to the p track of Si and SnO, to be conducive to the migration of particle.This enables transistor
Enough obtain the characteristic of high electron mobility.
Table 1
If Fig. 5 is to carry out the illustraton of model that Current Voltage changes performance simulation test to transistor, by insulating layer 9 in figure
The lower load pole plate 11 of upper and transistor substrate 5 carrys out the grid load gate voltage of analog transistor, by changing load in pole plate
On voltage, can control the energy band of channel layer i.e. monoatomic layer SnO and Si substrate entirety, that is, control their electric conductivity, from
And realize the performance of switch, and by adjusting load in the bias at source electrode and the both ends that drain, the I-V variation diagram of test transistor.
Wherein for when bias of the load at source electrode and the both ends that drain is 0.1V, electric current is with the gate voltage loaded on pole plate in Fig. 6
Variation diagram.It can be seen that increasing quickly as gate voltage increases electric current when gate voltage is greater than 2V, then tending to steady.Fig. 7 is
To transistor of the present invention carry out simulation test electric current with bias variations test result figure, as shown, flow through source electrode and
Voltage change of the electric current of drain electrode with load at both ends.It can see from Fig. 6 and Fig. 7, this variation tendency of I-V meets crystalline substance
The current-voltage characteristic of body pipe.
If the following table 2 is that the work function and diatomic of corresponding monoatomic layer SnO and Si substrate are calculated by simulating
The work function of layer SnO and Si substrate, the difference SnO layers of corresponding barrier height obtained from, it can be seen that having from the table
The monoatomic layer SnO of characteristic of semiconductor on one side barrier height and while diatomic layer SnO with metallic character potential barrier height
Degree.
Table 2
Above-mentioned is the detailed statement for preferred embodiment, it is obvious that the research of technical field
The change that personnel can make form and content aspect unsubstantiality according to above-mentioned step is substantially protected without departing from the present invention
The range of shield, therefore, the present invention are not limited to above-mentioned specific form and details.
Claims (6)
1. a kind of transistor, the transistor includes: Si substrate, the channel layer for being formed in Si substrate front surface, is formed in Si lining
The source electrode and drain electrode of bottom front surface, the insulating layer being covered in above channel layer and the grid on insulating layer；It is wherein described
Channel layer is electrically connected with source electrode and drain electrode formation respectively around source electrode and drain electrode and in side wall；It is characterized by: the channel layer
For the monoatomic layer SnO with semiconductor conductive characteristic, the source electrode and the drain electrode are double former with metallic conduction characteristic
Sublayer SnO.
2. a kind of transistor according to claim 1, it is characterised in that: the monoatomic layer SnO building is in Si (111) face
On lattice constant
3. a kind of transistor according to claim 1, it is characterised in that: the diatomic layer SnO building is in Si (111) face
On lattice constant
4. a kind of construction method of the model of the transistor as described in claims 1 to 3 any one, which is characterized in that including step
It is rapid:
1) Si unit cell is chosen, structure optimization is carried out to it；
2) selecting step 1) Si substrate after optimization, monoatomic layer SnO is constructed on its (111) face, is carried out structure optimization, and is counted
Calculate its electrical properties；
3) selecting step 1) Si substrate after optimization, diatomic layer SnO is constructed on its (111) face, is carried out structure optimization, and is counted
Calculate its electrical properties；
4) electrical properties according to possessed by the SnO of the obtained different atomic layers of step 2) and step 3), by it with Si substrate,
Insulating layer and grid are modeled, and transistor model is obtained.
5. constructing the method for transistor model according to claim 4, it is characterised in that: difference structure in step 2) and step 3)
The conductive characteristic of the monoatomic layer SnO and diatomic layer SnO built, the two are different, and one has semiconductor conductive characteristic, another tool
There is metallic conduction characteristic.
6. constructing the method for transistor model according to claim 5, it is characterised in that: difference structure in step 2) and step 3)
The monoatomic layer SnO and diatomic layer SnO, monoatomic layer SnO built has semiconductor conductive characteristic, and diatomic layer SnO has gold
Belong to conductive characteristic.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764065A (en) * | 2010-01-20 | 2010-06-30 | 中国科学院宁波材料技术与工程研究所 | Preparing method of p-type stannous oxide ditch film transistors |
| CN103606558A (en) * | 2013-11-15 | 2014-02-26 | 中国科学院宁波材料技术与工程研究所 | A bipolarity film transistor |
| US9147824B1 (en) * | 2014-05-08 | 2015-09-29 | International Business Machines Corporation | Reactive contacts for 2D layered metal dichalcogenides |
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|---|---|---|---|---|
| CN101764065A (en) * | 2010-01-20 | 2010-06-30 | 中国科学院宁波材料技术与工程研究所 | Preparing method of p-type stannous oxide ditch film transistors |
| CN103606558A (en) * | 2013-11-15 | 2014-02-26 | 中国科学院宁波材料技术与工程研究所 | A bipolarity film transistor |
| US9147824B1 (en) * | 2014-05-08 | 2015-09-29 | International Business Machines Corporation | Reactive contacts for 2D layered metal dichalcogenides |
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