CN101753142B - Time-to-digital converter and all-digital phase locked loop - Google Patents
Time-to-digital converter and all-digital phase locked loop Download PDFInfo
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- CN101753142B CN101753142B CN200910246684.2A CN200910246684A CN101753142B CN 101753142 B CN101753142 B CN 101753142B CN 200910246684 A CN200910246684 A CN 200910246684A CN 101753142 B CN101753142 B CN 101753142B
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Abstract
A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.
Description
The application require on August 19th, 2009 be submitted to Korea S Department of Intellectual Property 10-2009-0076780 korean patent application priority and be submitted to the 61/118th of United States Patent (USP) trademark office on December 1st, 2008, the priority of No. 693 United States Patent (USP)s, it is openly intactly contained in this, for reference.
Technical field
The equipment consistent with the present invention and method relate to a kind of time-to-digit converter (TDC) and use its all-digital phase-locked loop (ADPLL), more specifically say, relate to and a kind ofly not only can detect two phase differences between input signal, can also detect the transducer and use its all-digital phase-locked loop digit time of difference on the frequency.
Background technology
Along with the development of technology, in advanced treatment technology, all-digital phase-locked loop (ADPLL) is developed to the substitute of charge pump phase lock loop (CPPLL) to overcome the shortcoming of analog circuit.Time-to-digit converter (TDC) is the critical component of ADPLL, and this time-to-digit converter can be carried out the function identical with phase frequency detector (PFD) for CPPLL of the prior art.
But due to its little work (pull-in) scope, the TDC of the prior art that amplifies TDC and the TDC based on ring oscillator such as the TDC based on delay line, random TDC, time is only used as phase detectors (PD).In addition, only, when the difference of two frequencies is minimum, these PD can operate.When reducing loop bandwidth (loop bandwidth) in order to reduce shake, the working range of existing TDC also decreases.
In order to overcome these problems, some application replace TDC and adopt relay system PFD (bang-bangPFD) with detected phase.But, the phase alignment low precision of relay system PFD.Therefore, needing can detected phase error and the two TDC of frequency error.
Summary of the invention
Other shortcomings that exemplary embodiment of the present invention at least solves the problems referred to above at least and/or shortcoming and do not describe.In addition, the present invention does not expect to overcome above-mentioned shortcoming, and exemplary embodiment of the present can not overcome above-mentioned any the problems referred to above.
The ADPLL that an aspect of of the present present invention provides a kind of TDC and used it, described TDC can detect phase difference and the difference on the frequency of two signals.
According to an aspect of the present invention, a kind of time-to-digit converter (TDC) is provided, described TDC comprises: transducer, receive first signal and secondary signal, a plurality of delay elements that use is connected in series postpone secondary signal in phase place, and the secondary signal of delay and first signal are compared and export secondary signal about the phase error of first signal; Phase frequency detector, receives first signal, and one from a plurality of nodes a plurality of delay elements receives the 3rd signal, and exports the phase difference between first signal and the 3rd signal; Frequency detector, is used the output signal of phase frequency detector and secondary signal that secondary signal is output as to digital code about the frequency error of first signal.
Transducer can comprise: delay line, comprises a plurality of delay elements that are connected in series, and receive secondary signal by start node; A plurality of comparators, compare the phase place of the phase place of the node in delay line and first signal; Encoder, is output as digital code by secondary signal about the phase error of first signal based on described a plurality of comparators.
Delay element can be at least one in inverter, buffer, resistor and resistor-capacitor delay circuit.
Comparator can be trigger.
Described TDC also can comprise: output device, if input described frequency error from frequency detector, changes the described phase error of being exported by transducer.
If the phase place of the phase place hysteresis first signal of secondary signal, output device can be changed into minimum value by described phase error, if the phase place of the phase place hysteresis secondary signal of first signal, output device is changed into maximum by described phase error.
Described TDC also can comprise: ring oscillator, with the form of feedback loop, be connected to a plurality of delay elements, and the default frequency of oscillation of output; Counter, uses the frequency of oscillation of being exported by ring oscillator to count the cycle of the cycle of first signal and secondary signal.
One in first signal and secondary signal can be reference frequency.
According to another exemplary embodiment of the present invention, a kind of all-digital phase-locked loop (ADPLL) is provided, described all-digital phase-locked loop comprises: numerically-controlled oscillator, receives digital controlled signal and produce frequency of oscillation; Transducer, the frequency of oscillation that receives reference frequency and produced by numerically-controlled oscillator, a plurality of delay elements that use is connected in series postpone frequency of oscillation in phase place, the frequency of oscillation of delay and reference frequency are compared, and export frequency of oscillation about the phase error of reference frequency, phase frequency detector, receives reference frequency, from the intermediate node a plurality of delay elements, receive the 3rd signal, and export the phase difference between reference frequency and the 3rd signal; Frequency detector, is used the output signal of phase frequency detector and frequency of oscillation that frequency of oscillation is output as to digital signal about the frequency error of reference frequency; Digital rings filter, the frequency error of the phase error based on transducer output and frequency detector output offers numerically-controlled oscillator by digital controlled signal.
Transducer can comprise: delay line, comprises a plurality of delay elements that are connected in series, and receive frequency of oscillation by start node; A plurality of comparators, compare the phase place of the phase place of the node in delay line and reference frequency; Encoder, is output as digital code by frequency of oscillation about the phase error of reference frequency based on a plurality of comparators.
Delay element can be at least one in inverter, buffer, resistor and resistor-capacitor (RC) delay circuit.
Comparator can be trigger.
Transducer also can comprise: output device, if during from frequency detector incoming frequency error, changes the phase error of being exported by transducer.
If the phase place of the phase place hysteresis reference frequency of frequency of oscillation, output device can be changed into minimum value by phase error; If the phase place of the phase place hysteresis oscillation frequency of reference frequency, output device can be changed into maximum by phase error.
Transducer also can comprise: ring oscillator, with the form of feedback loop, be connected to a plurality of delay elements, and the default frequency of oscillation of output; Counter, uses the frequency of oscillation of being exported by ring oscillator to count the cycle of the cycle of reference frequency and frequency of oscillation.
Accompanying drawing explanation
By the description of certain exemplary embodiments of the present invention being carried out below in conjunction with accompanying drawing, above-mentioned and/or other aspects of the present invention and advantage will become clearer, wherein:
Fig. 1 is the circuit diagram of TDC according to an exemplary embodiment of the present invention;
Fig. 2 is the flow chart that the operation of the output device shown in Fig. 1 is shown;
Fig. 3 illustrates the input and output waveform of TDC according to an exemplary embodiment of the present invention;
Fig. 4 illustrates the transfer function of TDC according to an exemplary embodiment of the present invention;
Fig. 5 is the circuit diagram of the TDC of another exemplary embodiment according to the present invention;
Fig. 6 illustrates the transfer function of the TDC of another exemplary embodiment according to the present invention;
Fig. 7 is the block diagram that has more the ADPLL of exemplary embodiment of the present.
Embodiment
With reference to the accompanying drawings, certain exemplary embodiments of the present invention is described in more detail.
In the following description, even if identical label still represents identical element in different accompanying drawings.Provide the feature such as detailed structure and element limiting in specification to help more fully understanding the present invention.But the present invention does not use these concrete features that limit and implements the present invention.In addition, because the unnecessary detailed description of known function and structure will be obscured the present invention, therefore known functional structure is not described in detail.
Fig. 1 is the circuit diagram of time-to-digit converter (TDC) 100 according to an exemplary embodiment of the present invention.With reference to Fig. 1, TDC 100 can comprise phase frequency detector (PFD) 110, transducer 120, frequency detector 130 and output device 150.
In Fig. 1, PFD 110 comprises two d type flip flops and AND logic element.First signal REF is input as the clock signal of one of d type flip flop, and the output CLK (32) of the intermediate node in the delay line 121 of transducer 120 is input as the clock signal of another d type flip flop.Two d type flip flops receive the fixed signal " 1 " as data-signal, and receive the output as the AND logic element of reset signal.
With reference to Fig. 3, the operation of PFD 110 will be described in more detail.As shown in Figure 3, PFD 110 outputs are in the output signal (Up, Dn) of the rising edge variation of two signals (REF, CLK (32)).In Fig. 3, phase place due to leading the 3rd signal CLK (32) of phase place of first signal REF, so PFD110 changes into " 1 " at the rising edge of first signal REF by " Up " signal, and at the rising edge of the 3rd signal CLK (32), " Dn " signal is changed into " 1 ".
Because the value of " Up " signal and " Dn " signal is " 1 ", therefore, two d type flip flops in PFD 110 are reset.Therefore, from the rising edge of the 3rd signal CLK (32) t time of delay that resets in the past
rSTafterwards, PFD 110 changes into " 0 " by " Dn " signal and " Up " signal.
Therefore, the corresponding impulse wave Up of phase difference between PFD 110 exportable and first signal REF and the 3rd signal CLK (32), Dn.
Fig. 3 illustrates the phase place of leading the 3rd signal CLK (32) of phase place of first signal REF.But, if the phase place of the leading first signal REF of phase place of the 3rd signal CLK (32), PFD 110 changes into " 1 " at the rising edge of the 3rd signal CLK (32) by " Dn " signal, and from the rising edge of first signal REF t time of delay that resets in the past
rSTafterwards " Dn " signal is changed into " 0 ".
A plurality of comparators 121 compare the secondary signal CLK (0) postponing to CLK (62) and first signal REF.More specifically, the first signal REF that a plurality of comparators 121 receive as input data signal, and receive secondary signal CLK (0) as the delay of clock signal to CLK (62).Therefore, a plurality of comparators 121 compare the secondary signal CLK of the phase place of first signal REF and delay (0) to the phase place of CLK (62), thereby export a plurality of output signal Q (0) to Q (62).In Fig. 1, a plurality of comparators 121 are implemented as with d type flip flop, also can be implemented as JK flip-flop or latch element.
The encoder 140 based on the comparison a plurality of output Q (0) of device 121 is output as digital code by secondary signal CLK about the phase error of first signal REF to Q (62).More specifically, secondary signal CLK is delayed in phase place, so the secondary signal CLK of delay (0) is to lag behind after the time point phase place of first signal REF of the phase place of CLK (62).Therefore the comparator of secondary signal that, receives the delay of the phase place with hysteresis first signal REF produces the output different from the comparator of first front nodal point.Therefore, encoder can use the time of delay of delay element and the output Q (0) of a plurality of comparator 121 phase difference between two signals to be output as to digital code to Q (62).In Fig. 1, encoder 140 is included in transducer 120, still, also can be implemented as individual components or be included in output device 150.
Fig. 1 illustrates transducer 120 and uses single delay line delay control binary signal CLK.Transducer 120 can increase with two delay lines with different time of delays the resolution of TDC 100.
If output device 150 receives the frequency error being detected by frequency detector 130, output device 150 changes the phase error of transducer 120.With reference to Fig. 2, the operation of output device 150 will be described in more detail.
Fig. 2 illustrates the flow chart of the operation of output device 150.With reference to Fig. 2, output device 150 is determined whether output frequency error (Q of frequency detector 130
dNsignal).If Q
dNsignal value is 1, and output device 150 is the output of encoder 140, that is, the phase error between first signal REF and secondary signal CLK (PD[5:0]) is changed into minimum value (31).Alternatively, output device 150 is determined whether output frequency error (Q of frequency detector 130
uPsignal).If U
uPsignal value is 1, and output device 150 is by the output of encoder 140, that is, the phase error between first signal REF and secondary signal CLK is changed into maximum (+31).Alternatively, if frequency detector 130 output frequency error (Q not
uPsignal or Q
dNsignal), the value of in statu quo output coder 140 output of output device 150.In Fig. 2, first confirm Q
dNwhether signal value is 1.But, can also first confirm Q
uwhether signal value is 1.
Therefore, TDC 100 not only can detect two frequency errors between signal according to an exemplary embodiment of the present invention, can also detected phase error.That is, TDC 100 can have the working range wider than the TDC of prior art according to an exemplary embodiment of the present invention.
In Fig. 1, first signal has been described as the exemplary embodiment of inputting with reference to frequency signal.But secondary signal also can be used as reference frequency signal and inputs with the 3rd signal and also can be used as CLK signal and input.
Fig. 3 illustrates the input and output waveform of TDC 100 according to an exemplary embodiment of the present invention.In Fig. 3, the phase place of the phase place hysteresis first signal REF of secondary signal CLK.
With reference to (a) of Fig. 3, because " Up " signal of PFD 110 is not enough wide, therefore do not export Q
upsignal, correspondingly, the corresponding digitized Q of phase difference (the 0)-Q (62) between output and first signal REF and the secondary signal CLK of delay.
With reference to (b) of Fig. 3, because " Up " signal of PFD 110 is the phase-detection scope (t than transducer 120
pD) wide impulse wave, so the exportable Q of frequency detector 130
upsignal.
As shown in Figure 3, only work as t
pFDwhile thering is wide region, from the Q of the Up signal of sampling
upsignal can prevent phase error Q (0)-Q (62) to be output as 0.This condition can represent by following mathematical expression.
[mathematical expression 1]
t
PFD＞t
PD+t
RST
In mathematical expression 1, t
rSTthe pulse duration of the replacement pulse of PFD 110, t
pDto be converted the phase range that device 120 detects.The retention time nargin of setting and sampler makes above-mentioned calculating become complicated.But, can be by adding the time margin of sampler to t
pFDsolve the problems referred to above.
In exemplary embodiment of the present as shown in Figure 3, secondary signal CLK hysteresis first signal REF.But even when secondary signal CLK leading (leading) first signal REF, input and output waveform has the waveform with the waveform similarity of Fig. 3.
Fig. 4 illustrates the transfer function of TDC 100 according to an exemplary embodiment of the present invention.
Existing phase detectors have this problem in working range, that is, as shown in the top transfer function of Fig. 4, the scope internal symbol that is greater than π in phase error is reversed.
But, the transfer function (H of TDC 100 according to an exemplary embodiment of the present invention
tDC) at phase error (θ
err) be less than t
pFDscope in there is the transfer function (H with existing phase detectors
pD) identical form, that is, at initial point, keep linear.In order to prevent from being greater than in phase error the scope internal symbol reversing of π, if phase error (θ
err) be greater than t
pFDby transfer function (H
tDC) be converted to H
pFD.
Therefore, according to the present invention, be that the symbol of the TDC 100 of exemplary embodiment is not reversed in phase error is greater than the scope of π, and TDC 100 maintenance the same with existing TDC in remaining range is linear, therefore, can solve the problem of working range.
Fig. 5 is the circuit diagram of the TDC 100 ' of another exemplary embodiment according to the present invention.
With reference to Fig. 5, compare with the TDC 100 of Fig. 1, TDC 100 ' also can comprise ring oscillator 151, counter 152 and two triggers 153.
If two triggers 153 are from frequency detector 130 receiver frequency error values, the periodic quantity of two trigger 153 output first signal REF and secondary signal CLK.If two triggers 153 are not from frequency detector 130 receiver frequency error values, two triggers 153 are reset, and do not export the periodic quantity of first signal REF and secondary signal CLK.
Therefore, because the TDC 100 ' of another exemplary embodiment according to the present invention additionally comprises ring oscillator 151 sum counters 152, so TDC 100 ' not only the phase error of exportable first signal REF and secondary signal CLK existence or do not exist, the grade of exportable frequency error also, that is, first signal REF and secondary signal clk cycle.The transfer function of TDC 100 ' shown in Figure 6.
With reference to Fig. 6, when phase error is greater than t
pFDtime, the transfer function of TDC 100 ' has stairstepping.In this case, resolution becomes the cycle of ring oscillator 151.Therefore,, if when TDC 100 ' is used as the parts of all-digital phase-locked loop (ADPLL), can promptly carries out frequency and fix.
Fig. 7 is the block diagram of ADPLL according to an exemplary embodiment of the present invention.
As shown in Figure 7, ADPLL 1000 can comprise TDC 100, digital rings filter 200 and numerically-controlled oscillator 300.
Numerically-controlled oscillator 300 receives digital controlled signal and produces frequency of oscillation.More specifically, numerically-controlled oscillator 300 receives digital controlled signal, and the variable capacitor and the variable inductor that by adjustment, are arranged in numerically-controlled oscillator 300 produce and the corresponding frequency of oscillation of described digital controlled signal.The available circuit based on digital is realized numerically-controlled oscillator 300, and can use the voltage-controlled oscillator (VCO) of prior art to realize numerically-controlled oscillator 300.
The frequency of oscillation that TDC 100 receives reference frequency and produced by numerically-controlled oscillator 300, and detect phase error and the frequency error between reference frequency and frequency of oscillation.More specifically, the frequency of oscillation that TDC 100 receives reference frequency and produced by numerically-controlled oscillator 300, a plurality of delay elements that use is connected in series postpone described frequency of oscillation in phase place, and the frequency of oscillation and the described reference frequency that postpone are compared.TDC 100 can comprise: transducer, the phase error between output reference frequency and frequency of oscillation; Phase frequency detector, receives reference frequency the intermediate node from a plurality of delay elements and receives the 3rd signal, the phase difference between output reference frequency and the 3rd frequency; Frequency detector, is used output signal and the frequency of oscillation of phase frequency detector to be output as digital signal with reference to the frequency error between frequency and frequency of oscillation.
Phase error and frequency error that digital rings filter 200 detects based on TDC 100 offer numerically-controlled oscillator 300 by digital controlled signal.
Above-mentioned exemplary embodiment is only exemplary, and should not be construed as restriction the present invention.This instruction can easily be applied to the equipment of other types.In addition, being intended that of the description of exemplary embodiment of the present is exemplary, is not intended to limit the scope of claim, and is to carry out various selections, modifications and variations to what those skilled in the art know that.
Claims (15)
1. a time-to-digit converter TDC, described time-to-digit converter comprises:
Transducer, receives first signal and secondary signal, uses a plurality of delay elements that are connected in series in phase place, secondary signal to be postponed, and the secondary signal of delay and first signal are compared and export secondary signal about the phase error of first signal;
Phase frequency detector, receives first signal, and one from a plurality of nodes a plurality of delay elements receives the 3rd signal, and exports the phase difference between first signal and the 3rd signal;
Frequency detector, is used the output signal of phase frequency detector and secondary signal that secondary signal is output as to digital code about the frequency error of first signal.
2. TDC as claimed in claim 1, wherein, transducer comprises:
Delay line, comprises a plurality of delay elements that are connected in series, and receives secondary signal by start node;
A plurality of comparators, compare the phase place of the phase place of the node in delay line and first signal;
Encoder, is output as digital code by secondary signal about the phase error of first signal based on described a plurality of comparators.
3. TDC as claimed in claim 2, wherein, delay element is at least one in inverter, buffer, resistor and resistor-capacitor delay circuit.
4. TDC as claimed in claim 2, wherein, comparator is trigger.
5. TDC as claimed in claim 1, also comprises:
Output device, when inputting described frequency error from frequency detector, changes the described phase error of being exported by transducer.
6. TDC as claimed in claim 5, wherein, when the phase place of the phase place hysteresis first signal of secondary signal, output device is changed into minimum value by described phase error,
When the phase place of the phase place hysteresis secondary signal of first signal, output device is changed into maximum by described phase error.
7. TDC as claimed in claim 1, also comprises:
Ring oscillator, is connected to a plurality of delay elements with the form of feedback loop, and the default frequency of oscillation of output;
Counter, uses the default frequency of oscillation of being exported by ring oscillator to count the cycle of the cycle of first signal and secondary signal.
8. TDC as claimed in claim 1, wherein, one in first signal and secondary signal is reference frequency.
9. an all-digital phase-locked loop ADPLL, described all-digital phase-locked loop comprises:
Numerically-controlled oscillator, receives digital controlled signal and exports frequency of oscillation;
Transducer, the frequency of oscillation that receives reference frequency and produced by numerically-controlled oscillator, is used a plurality of delay elements that are connected in series in phase place, frequency of oscillation to be postponed, and the frequency of oscillation of delay and reference frequency are compared, and export frequency of oscillation about the phase error of reference frequency
Phase frequency detector, receives reference frequency, receives the 3rd signal, and export the phase difference between reference frequency and the 3rd signal from the intermediate node a plurality of delay elements;
Frequency detector, is used the output signal of phase frequency detector and frequency of oscillation that frequency of oscillation is output as to digital signal about the frequency error of reference frequency;
Digital rings filter, the frequency error of the phase error based on transducer output and frequency detector output offers numerically-controlled oscillator by digital controlled signal.
10. ADPLL as claimed in claim 9, wherein, transducer comprises:
Delay line, comprises a plurality of delay elements that are connected in series, and receives frequency of oscillation by start node;
A plurality of comparators, compare the phase place of the phase place of the node in delay line and reference frequency;
Encoder, is output as digital code by frequency of oscillation about the phase error of reference frequency based on a plurality of comparators.
11. ADPLL as claimed in claim 10, wherein, delay element is at least one in inverter, buffer, resistor and resistor-capacitor delay circuit.
12. ADPLL as claimed in claim 10, wherein, comparator is trigger.
13. ADPLL as claimed in claim 10, wherein, transducer also comprises:
Output device, if from frequency detector incoming frequency error, change the phase error of being exported by transducer.
14. ADPLL as claimed in claim 13, wherein, if the phase place of the phase place hysteresis reference frequency of frequency of oscillation, output device is changed into minimum value by phase error;
If the phase place of the phase place hysteresis oscillation frequency of reference frequency, output device is changed into maximum by phase error.
15. ADPLL as claimed in claim 10, wherein, transducer also comprises:
Ring oscillator, is connected to a plurality of delay elements with the form of feedback loop, and the default frequency of oscillation of output;
Counter, uses the default frequency of oscillation exported by ring oscillator to count the cycle of the cycle of reference frequency and the frequency of oscillation exported by numerically-controlled oscillator.
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| Application Number | Priority Date | Filing Date | Title |
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| US11869308P | 2008-12-01 | 2008-12-01 | |
| US61/118,693 | 2008-12-01 | ||
| KR1020090076780A KR101632657B1 (en) | 2008-12-01 | 2009-08-19 | Time-to-digital convertoer and all-digital phase locked loop |
| KR10-2009-0076780 | 2009-08-19 |
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| CN101753142B true CN101753142B (en) | 2014-03-19 |
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| US8193963B2 (en) * | 2010-09-02 | 2012-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and system for time to digital conversion with calibration and correction loops |
| KR101300828B1 (en) * | 2010-12-23 | 2013-08-29 | 건국대학교 산학협력단 | Time to digital converter using Successive Approximation and the method thereof |
| CN102832943B (en) * | 2011-06-15 | 2015-06-03 | 联发科技（新加坡）私人有限公司 | Time-to-digital converter |
| CN102291138B (en) * | 2011-07-08 | 2013-11-27 | 东南大学 | Stochastic time-digital converter |
| CN102957422B (en) * | 2011-08-30 | 2015-06-03 | 中国科学院电子学研究所 | Digital time delay lock loop circuit |
| US9197402B2 (en) * | 2012-04-10 | 2015-11-24 | Intel Corporation | Re-circulating time-to-digital converter (TDC) |
| KR101278109B1 (en) * | 2012-04-19 | 2013-06-24 | 서울대학교산학협력단 | Digital phase locked loop having low long-term jitter |
| WO2013180701A1 (en) * | 2012-05-30 | 2013-12-05 | Intel Corporation | Analog-to-digital converter |
| KR101278111B1 (en) * | 2013-04-12 | 2013-06-24 | 서울대학교산학협력단 | Time to digital converter |
| GB2532015B (en) * | 2014-11-04 | 2018-12-26 | Cirrus Logic Int Semiconductor Ltd | Improved analogue-to-digital convertor |
| CN107077099B (en) | 2015-02-03 | 2019-08-16 | 华为技术有限公司 | When m- digital quantizer |
| US9577684B1 (en) * | 2015-11-25 | 2017-02-21 | Intel IP Corporation | High frequency time interleaved digital to time converter (DTC) |
| KR101722860B1 (en) * | 2015-12-09 | 2017-04-03 | 한양대학교 산학협력단 | Digital phase locked loop with high bandwidth using rising edge and falling edge of signal |
| US10768580B2 (en) * | 2017-03-02 | 2020-09-08 | Intel IP Corporation | Time-to-digital converter, digital phase-locked loop, method for operating a time-to-digital converter, and method for a digital phase-locked loop |
| US10520901B2 (en) * | 2018-02-23 | 2019-12-31 | Qualcomm Incorporated | Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation |
| CN110836832B (en) * | 2019-11-20 | 2022-03-29 | 苏州萃智光电设备有限公司 | TDC control system, method and film thickness detection device |
| CN112054800B (en) * | 2020-08-03 | 2023-08-08 | 博流智能科技（南京）有限公司 | Digital time conversion method, digital time converter and digital phase-locked loop |
| CN115016243B (en) * | 2022-05-12 | 2023-03-10 | 北京大学 | Linearity enhancement method for random time-to-digital converter |
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| US6429693B1 (en) * | 2000-06-30 | 2002-08-06 | Texas Instruments Incorporated | Digital fractional phase detector |
| KR100750126B1 (en) * | 2005-08-29 | 2007-08-21 | 삼성전자주식회사 | Phase locked loop circuit and phase locked loop control method |
| US7332973B2 (en) * | 2005-11-02 | 2008-02-19 | Skyworks Solutions, Inc. | Circuit and method for digital phase-frequency error detection |
| TWI328932B (en) * | 2006-11-10 | 2010-08-11 | Ind Tech Res Inst | Cycle time to digital converter |
| KR100852180B1 (en) * | 2006-11-24 | 2008-08-13 | 삼성전자주식회사 | Time-to-digital converter |
| JP2008160594A (en) * | 2006-12-25 | 2008-07-10 | Sharp Corp | Time digital converter and digital phase locked loop device, receiver |
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2009
- 2009-08-19 KR KR1020090076780A patent/KR101632657B1/en active IP Right Grant
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| CN101753142A (en) | 2010-06-23 |
| KR20100062893A (en) | 2010-06-10 |
| KR101632657B1 (en) | 2016-06-23 |
| ATE542300T1 (en) | 2012-02-15 |
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