CN101753131B - Circuit oscillation device for generating and controlling clock signals - Google Patents

Abstract

The invention discloses a circuit oscillation device for generating and controlling clock signals. In the device, a control and offset circuit module is taken as a core, a signal output end thereof is connected with a standard generation circuit module and is also connected with an oscillation generation circuit module and a clock output circuit module; and the output end of the standard generation circuit module is also connected with the oscillation generation circuit module and the clock output circuit module. For adopting a modularization design, the invention has the advantages of simple structure, low power consumption, reusability and cost saving and can integrate in a chip, generate and control the clock signals, enhance the integration level, the stability and the reliability of a circuit, generate a clock of 460.8kHz by adopting the oscillation device circuit, support the effective functions of chip selection and support that an external clock directly inputs and/or uses an external connection crystal so as to generate two working modes of the clock.

Description

Be used for the circuit oscillation device that clock signal produces and controls

Technical field

The present invention relates to the IC design technical field, specifically a kind of circuit oscillation device that is used for clock signal generation and control.

Background technology

Along with the high speed development of domestic IC industry, the technological level of integrated circuit production improved constantly in recent years, and the IC designing technique is constantly brought forth new ideas, and the integrated level of chip is increasingly high, and function is more and more perfect, and performance index are also increasingly high.Hybrid digital-analog integrated circuit design has at present become the difficult point and the focus of IC design industry.Nearly all digital circuit all adopts Sequential Circuit Design now; Clock (CLOCK) is a requisite signal in all sequence circuits; The clock of most of digital circuit is outer and directly imports or realize at inside circuit embedding phase-locked loop (PLL) IP; Phase-locked loop IP exists cost higher, complex structure, the high deficiency of power consumption.

Summary of the invention

The purpose of this invention is to provide a kind of can be simple in structure, low in energy consumption in analog IC design, have reusability, connect external crystal and produce clock be used for that clock signal produces and the circuit oscillation device of control.

To achieve these goals, technical scheme of the present invention is: a kind of circuit oscillation device that is used for clock signal generation and control, and this device is core with control with the biasing circuit module, its signal output part is connected to benchmark generative circuit module; Its signal output part also is connected to vibration generative circuit module and clock output circuit module; Said benchmark generative circuit module output also is connected to vibration generative circuit module and clock output circuit module.

Said control and biasing circuit module receive first and enable control signal (VEN) and first bias current signal (IBIAS); Control enables control signal (VEN1) with biasing circuit module output second and second bias current signal (IBIAS1) causes benchmark generative circuit module; Its output second enables control signal (VEN1) and the 3rd bias current signal (IBIAS2) causes vibration generative circuit module; Its output second enables control signal (VEN1) and the 4th bias current signal (IBIAS3) causes the clock output circuit module; It also exports external crystal control signal (IXTL) and external crystal oscillator signal (OTXL), and with external crystal control signal (IXTL) vibration input and external crystal oscillator signal (OTXL) oscillation output end line be connected.

Said benchmark generative circuit module receives control and enables control signal (VEN1) and second bias current signal (IBIAS1) with second of biasing circuit generation; And receive first and enable control signal (VEN) and outside reference voltage signal (VREF); Benchmark generative circuit module output reference voltage signal (V1) causes vibration generative circuit module and clock output circuit module.

Said vibration generative circuit module receives first and enables control signal (VEN); Receive control and enable control signal (VEN1) and the 3rd bias current signal (IBIAS2), and receive the reference voltage signal (V1) that the benchmark generative circuit generates with second of biasing circuit module generation; Vibration generative circuit module outputting oscillation signal (V2); Vibration generative circuit module and external crystal control signal (IXTL) vibrate input and external crystal oscillator signal (OTXL) oscillation output end line be connected.

Said clock output circuit module receives control and enables control signal (VEN1) and the 4th bias current signal (IBIAS3) with second of biasing circuit module generation, the oscillator signal (V2) that reference voltage signal (V1) that benchmark generative circuit module produces and vibration generative circuit module produce; And generation clock output signal (CLKO).

The present invention has following advantage:

1, the present invention adopts modularized design, and it is simple in structure, and is low in energy consumption, has reusability, can be integrated at chip internal, can produce and control clock signal, and also have the saving cost, improve the advantage of circuit level, stability and reliability.

2, the present invention designs the clock that adopts this pierce circuit can produce 460.8kHz, and supporting pieces selects effective efficiency, and can support the direct input of external clock and use the outside to be connected crystal and to produce two kinds of mode of operations of clock.

Description of drawings

Fig. 1 is an integrated circuit structure chart of the present invention;

Fig. 2 is control of the present invention and biasing circuit modular structure figure;

Fig. 3 is benchmark generative circuit modular structure figure of the present invention;

Fig. 4 is vibration generative circuit modular structure figure of the present invention;

Fig. 5 is clock output circuit modular structure figure of the present invention.

Embodiment

Embodiment

As shown in Figure 1, a kind of circuit oscillation device that is used for clock signal generation and control, this device is core with control with the biasing circuit module, its signal output part is connected to benchmark generative circuit module; Its signal output part also is connected to vibration generative circuit module and clock output circuit module; Said benchmark generative circuit module output also is connected to vibration generative circuit module and clock output circuit module.

Said control and biasing circuit module receive first and enable control signal (VEN) and first bias current signal (IBIAS); Control enables control signal (VEN1) with biasing circuit module output second and second bias current signal (IBIAS1) causes benchmark generative circuit module; Its output second enables control signal (VEN1) and the 3rd bias current signal (IBIAS2) causes vibration generative circuit module; Its output second enables control signal (VEN1) and the 4th bias current signal (IBIAS3) causes the clock output circuit module; It also exports external crystal control signal (IXTL) and external crystal oscillator signal (OTXL), and with external crystal control signal (IXTL) vibration input and external crystal oscillator signal (OTXL) oscillation output end line be connected.

Said benchmark generative circuit module receives control and enables control signal (VEN1) and second bias current signal (IBIAS1) with second of biasing circuit generation; And receive first and enable control signal (VEN) and outside reference voltage signal (VREF); Benchmark generative circuit module output reference voltage signal (V1) causes vibration generative circuit module and clock output circuit module.Said vibration generative circuit module receives first and enables control signal (VEN); Receive control and enable control signal (VEN1) and the 3rd bias current signal (IBIAS2), and receive the reference voltage signal (V1) that the benchmark generative circuit generates with second of biasing circuit module generation; Vibration generative circuit module outputting oscillation signal (V2); Vibration generative circuit module and external crystal control signal (IXTL) vibrate input and external crystal oscillator signal (OTXL) oscillation output end line be connected.Said clock output circuit module receives control and enables control signal (VEN1) and the 4th bias current signal (IBIAS3) with second of biasing circuit module generation, the oscillator signal (V2) that reference voltage signal (V1) that benchmark generative circuit module produces and vibration generative circuit module produce; And generation clock output signal (CLKO).Said clock output circuit module receives second of control and the generation of biasing circuit module and enables control signal VEN1 and the 4th bias current signal IBIAS3, the oscillator signal V2 of reference voltage signal V1 that benchmark generative circuit module produces and the generation of vibration generative circuit module; And generation clock output signal CLKO.

Referring to Fig. 2; Control the first bias current signal IBIAS that is connected outside input with the biasing circuit module by the drain electrode of N type the 20 MOS transistor N20; Its source electrode meets GND, and the grid of the 20 MOS transistor N20 connects the grid of four N type MOS transistors, and (said four N type MOS transistors are: the 17 MOS transistor N17, the 19 MOS transistor N19; The 24 MOS transistor N24, the 25 MOS transistor N25).The source electrode of the 19 MOS transistor N19 meets GND; Its drain electrode links to each other with grid, and receives the source electrode of N type the 18 a MOS transistor N18, and its grid meets the first bias current signal IBIAS of outside input; Its drain electrode links to each other another termination VDD of the 4th resistance R 4 with an end of the 4th resistance R 4.The second bias current signal IBIAS1 is exported in the drain electrode of the 17 MOS transistor N17, and its source electrode meets GND.The source electrode of the 24 MOS transistor N24 meets GND, and its drain electrode meets output the 3rd bias current signal IBIAS2.The source electrode of the 25 MOS transistor N25 meets GND, and its drain electrode meets output the 4th bias current signal IBIAS3.First of outside input enable that control signal VEN connects that two pairs of inverter structures are connected the said inverter structure of grid be: the 15 MOS transistor P15 and the 22 MOS transistor N22 connect into inverter structure; The 16 MOS transistor P16 and the 23 MOS transistor N23 connect into inverter structure); Second of the grid of N type the 21 a MOS transistor N21 enables control signal VEN1 and exports to other module; Its drain electrode meets the first bias current signal IBIAS of outside input; The drain electrode of the 16 MOS transistor links to each other with the drain electrode of the 23 MOS transistor N23, meets the outside signal IXTL that connects crystal of control.Its source electrode meets external signal OTXL.

Referring to Fig. 3; Benchmark generative circuit module uses a pair of P type metal-oxide-semiconductor (present embodiment is the 3rd, the 4th MOS transistor P3, P4) as the difference metal-oxide-semiconductor; The grid of the 3rd MOS transistor P3 meets the reference voltage signal VREF of outside input; The source electrode of said the 3rd, the 4th MOS transistor P3, P4 links to each other; Connect the drain electrode of the first MOS transistor P1 jointly, the drain electrode of the 3rd MOS transistor P3 connects the 5th MOS transistor N5 drain and gate, and the drain electrode of the 4th MOS transistor P4 connects the drain electrode of the 6th MOS transistor N6.The 8th MOS transistor N8 links to each other with the source electrode of the 7th MOS transistor P7, and connects the grid of the 4th MOS transistor P4.The drain electrode of the 7th MOS transistor P7 connects an end of first resistance R 1, another termination GND of first resistance R 1.The grid of the 8th MOS transistor N8 links to each other with drain electrode, and receives the drain electrode of the second MOS transistor P2.The grid of the 11 MOS transistor P11 links to each other with the grid of the 7th MOS transistor P7, is attempted by an end of first capacitor C 1.The drain electrode of the 11 MOS transistor P11 connects an end of first resistance R 1.The source electrode of its source electrode and the tenth MOS transistor N10, and export to other circuit modules as output signal V1.Eight, the grid of ten MOS transistor N8, N10 links to each other, and the drain electrode of receiving N type the 9th a MOS transistor N9, and its grid connects that control and biasing circuit module generate enables control signal VEN1.The drain electrode of the tenth MOS transistor N10 connects an end of second resistance R 2.The drain electrode of P type the 14 a MOS transistor P14 meets the bias current signal IBIAS1 of control and the generation of biasing circuit module.What its grid connect outside input enables control signal VEN.

Referring to Fig. 4; The source electrode of vibration generative circuit module the 47, the 48 MOS transistor N47, P48 meets the reference voltage signal V1 that benchmark generative circuit module generates, and the drain electrode of the 47, the 48 MOS transistor N47, P48 links to each other and exports as signal V2.The outside signal IXTL that connects crystal of control connects the grid of N type the 50 a MOS transistor N50, and its drain electrode links to each other with the drain electrode of P type the 40 a MOS transistor P40, and exports as the signal OXTL of external crystal.One end of second capacitor C 2 connects the signal OXTL of external crystal, and the other end connects exports signal V2.The reference voltage signal V1 that benchmark generative circuit module generates connects the grid of the 45 MOS transistor N45, and the grid of the 46 MOS transistor N46 meets oscillator signal V2, and the source electrode of the 45 MOS transistor N45 connects an end of the 5th resistance R 5.The drain electrode of the 45, the 46 MOS transistor N45, N46 links to each other with source electrode, is attempted by on the 3rd bias current signal IBIAS2 of control and biasing circuit module generation, and is connected the grid of the 51 MOS transistor N51.First of outside input enables the grid that control signal VEN meets P type the 39 a MOS transistor P39; Its drain electrode connects the source electrode of the 42 MOS transistor P42; The drain electrode of P type the 40 a MOS transistor P40 meets the signal OXTL of external crystal; Its grid links to each other with the grid of P type the 41 a MOS transistor P41, is attempted by in the drain electrode of the 39 MOS transistor P39.Control enables the grid that control signal VEN1 is connected on N type the 49 a MOS transistor N49 with second of biasing circuit module generation, and its drain electrode meets output signal V2.

Referring to Fig. 5; The the 33, the 34 MOS transistor N33 of clock output circuit module, the grid of N34 meet the reference voltage signal V1 of benchmark generative circuit module generation and the oscillator signal V2 that vibration generative circuit module generates; Its two source electrode links to each other; Be attempted by on the 3rd bias current signal IBIAS3 of control and biasing circuit module generation, the drain electrode of the 33 metal-oxide-semiconductor N33 links to each other with the drain and gate of the 27 MOS transistor P27.The grid of the 26 MOS transistor P26 links to each other with the grid of the 27 MOS transistor P27, and its drain electrode links to each other with the drain and gate of the 32 MOS transistor N32.The reference voltage signal V1 that benchmark generative circuit module generates connects the grid of the 34 N34; The drain electrode of the 30 MOS transistor P30 links to each other with the drain electrode of the 36 N36; Be attempted by the 31, the 38 MOS transistor P31 of pair of phase inverters connection, the grid of N38, the source electrode of the 31 MOS transistor P31 meets VDD, and the source electrode of the 38 MOS transistor N38 meets GND; Its two drain electrode links to each other, and exports as clock output signal CLKO.The drain electrode of the 37 MOS transistor N37 links to each other with the grid of the 30 MOS transistor P30, and the grid of the 37 MOS transistor N37 connects control and enables control signal VEN1 with second of biasing circuit module generation, and its source electrode meets GND.

The circuit working process is following: under the state of supply voltage VDD input 3.3V, receive first of outside input by control and biasing circuit module and enable control signal VEN, enable control signal VEN and be input as height when first; When being 3.3V; Whole pierce circuit is in normal operating conditions, when first enable control signal VEN be input as low, when promptly meeting GND; Whole pierce circuit module is in off position, and power consumed is very low in this state.By control and biasing circuit module produce other module of control enable control signal and the needed bias current signal of other module work is exported to other each module.In normal operation; Outside reference voltage signal VREF is a 1.235V voltage; Produce reference voltage signal V1 through benchmark generative circuit module; This reference voltage signal V1 is inputed to vibration generative circuit module, and when externally signal IXTL and OXTL connect the 460.8KHz crystal, perhaps IXTL met GND; When OXTL connects the clock pulse of input 460.8KHz; Produce an oscillating voltage signal V2 by vibration generative circuit module, benchmark generative circuit module reference voltage signal V1 that produces and the oscillating voltage signal V2 that vibration generative circuit module produces are inputed to the clock output circuit module, produce the clock output signal CLKO of 460.8KHz by the clock output circuit module.

Claims (1)

1. one kind is used for the circuit oscillation device that clock signal produces and controls, and it is characterized in that: this device is core with control with the biasing circuit module, and its signal output part is connected to benchmark generative circuit module; Its signal output part also is connected to vibration generative circuit module and clock output circuit module; Said benchmark generative circuit module output also is connected to vibration generative circuit module and clock output circuit module;

Said control and biasing circuit module receive first and enable control signal (VEN) and first bias current signal (IBIAS); Control enables control signal (VEN1) with biasing circuit module output second and second bias current signal (IBIAS1) causes benchmark generative circuit module; Its output second enables control signal (VEN1) and the 3rd bias current signal (IBIAS2) causes vibration generative circuit module; Its output second enables control signal (VEN1) and the 4th bias current signal (IBIAS3) causes the clock output circuit module; It also exports external crystal control signal (IXTL) and external crystal oscillator signal (OTXL), and with external crystal control signal (IXTL) vibration input and outside article oscillation body signals (OTXL) oscillation output end line be connected;

Said benchmark generative circuit module receives control and enables control signal (VEN1) and second bias current signal (IBIAS1) with second of biasing circuit generation; And receive first and enable control signal (VEN) and outside reference voltage signal (VREF); Benchmark generative circuit module output reference voltage signal (V1) causes vibration generative circuit module and clock output circuit module;

Said vibration generative circuit module receives first and enables control signal (VEN); Receive control and enable control signal (VEN1) and the 3rd bias current signal (IBIAS2), and receive the reference voltage signal (V1) that the benchmark generative circuit generates with second of biasing circuit module generation; Vibration generative circuit module outputting oscillation signal (V2); Vibration generative circuit module and external crystal control signal (IXTL) vibrate input and external crystal oscillator signal (OTXL) oscillation output end line be connected;

Said clock output circuit module receives control and enables control signal (VEN1) and the 4th bias current signal (IBIAS3) with second of biasing circuit module generation, the oscillator signal (V2) that reference voltage signal (V1) that benchmark generative circuit module produces and vibration generative circuit module produce; And generation clock output signal (CLKO).

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