JP2012134321A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit increase in circuit area thereby to allow a time interval for turning on a plurality of power switches for supplying power to a circuit block to be appropriately controlled.SOLUTION: A semiconductor device comprises a power management unit 11 managing power supply to a circuit block, a plurality of power switches PSWA controlling power supply to the circuit block A12 and a delay generator 13 activated by the power supplied to the circuit block A and generating a delay corresponding to potential of the power supplied to the circuit block A. The power switches are controlled, when controlled to be put into an on-state, so as to be sequentially put into the on-state at intervals of time corresponding to potential of the power to the circuit block A supplied based on outputs from the power management unit 11 and the delay generator 13. In such a manner, the intervals of time for turning on the power switches are automatically controlled corresponding to the potential of the power supplied to the circuit block A to supply the power.

Description

  The present invention relates to a semiconductor device, and more particularly to a power supply control technique related to a semiconductor device.

  In recent years, there has been a strong demand for lower power consumption in semiconductor devices such as LSI, and the number of cases in which a semiconductor device having a power cutoff function (power switch) is employed is increasing. So-called power gating technology that further reduces power consumption by shutting off power supply to unused circuit blocks according to the usage status (use / non-use) of each circuit block of a semiconductor device It is.

  An outline of the power gating technique will be described with reference to FIG. 8A and 8B are diagrams illustrating an example of a semiconductor device to which the power gating technique is applied. 8A and 8B, A to F are circuit blocks, and a power switch is provided for each of the circuit blocks A to F to control power supply. The PMU (Power Management Unit) is a power management unit that performs power management in the semiconductor device, in other words, manages power supply to each of the circuit blocks A to F. The power management unit PMU is always supplied with power.

  For example, as shown in FIG. 8A, during full operation, the power management unit PMU controls the power switch so that power is supplied to all circuit blocks. On the other hand, as shown in FIG. 8B, when the function is stopped and the state is held, the power management unit PMU needs to be operated in order to keep the state among the circuit blocks A to F. The power switch is controlled so that power is supplied only to D. That is, for the circuit blocks A, B, C, E, and F other than the circuit block D, the power switch is controlled to be in an OFF state, and the power supply to these circuit blocks is cut off.

  By shutting off the power supply to the circuit block whose function is stopped using the power gating technique, the leakage current generated in the circuit in the circuit block is significantly reduced, and the power consumption is reduced (FIG. 8C )reference). In FIG. 8C, T81 is a power gating period (period in which power supply to the circuit block is cut off), and T82 is a start-up period when transitioning from the function stop state (power cut-off state) to the operating state. is there. Since power gating technology can further reduce power consumption, it is becoming an indispensable technology especially for portable devices for communication and the like that are demanded to reduce power consumption particularly during standby.

  Here, as a problem to be considered when the power gating technique is used in a semiconductor device, there is a problem related to power supply noise. The problem relating to the power supply noise will be described with reference to FIG. In FIG. 9A, 90 is a semiconductor device, 91 is a power management unit (PMU), 92 is a circuit block A (CBLA), and 93 is a circuit block B (CBLB). CA is a stabilization capacitor of the circuit block A92, and CB is a stabilization capacitor of the circuit block B93.

  The circuit block A92 and the stabilization capacitor CA are connected between a VDDVA power supply line that supplies a power supply potential VDDVA and a VSS power supply line that supplies a reference potential (for example, ground potential) VSS. Further, the VDDVA power supply line and the VDD power supply line for supplying the power supply potential VDD are connected via the power switch PSWA. The VDD power supply line and the VSS power supply line are constantly applied with the power supply potential VDD and the reference potential VSS from the outside, respectively. The power switch PSWA is ON / OFF controlled by a control signal PGA from the power management unit 91, and power is supplied to the circuit block A92 when the power switch PSWA is ON, and to the circuit block A92 when the power switch PSWA is OFF. The power supply of is interrupted.

  Similarly, the circuit block B93 and the stabilization capacitor CB are connected between the VDDVB power supply line that supplies the power supply potential VDDVB and the VSS power supply line. The VDDVB power supply line and the VDD power supply line are connected via the power switch PSWB. The power switch PSWB is ON / OFF controlled by a control signal PGB from the power management unit 91, and power is supplied to the circuit block B93 when the power switch PSWB is ON, and to the circuit block B93 when the power switch PSWB is OFF. The power supply of is interrupted.

  In a semiconductor device to which power gating technology is applied, when a circuit block whose power supply is cut off is used (operated) again, the power switch is turned from an off state to an on state in order to supply power to the circuit block. There is a need. For example, in the semiconductor device 90 shown in FIG. 9A, it is assumed that the circuit block A92 in which the power supply is cut off is operated again in the operation state in which the circuit block B93 is supplied with power. At this time, the power switch PSWA is turned on by the control signal PGA from the power management unit 91, but at the moment when the power switch PSWA is turned on, an inrush current (rush) for charging the stabilization capacitor CA and the like of the circuit block A92. current) flows. This inrush current causes fluctuations in the power supply potential (power supply noise), and the power supply noise supplies, for example, a potential difference PV between the VDD power supply line and the VSS power supply line, in other words, a circuit operating in the semiconductor device 90. The power supply voltage decreases (see FIG. 9B). Thus, the power supply noise generated by the inrush current flowing when the power switch is turned on is propagated to the peripheral circuits, and the power management unit 91 and the circuit block B93 that are operating may malfunction.

  As a method of suppressing power supply noise that occurs when the power switch is turned on, a single power switch is composed of a plurality of small-sized switches, and each switch is turned on at different timings. A method for suppressing the above has been proposed (see, for example, Patent Document 1). FIG. 10A illustrates a configuration example of a semiconductor device in which a power switch is divided into a plurality of small-sized power switches.

  In FIG. 10A, 100 is a semiconductor device, 101 is a power management unit (PMU), 102 is a circuit block A (CBLA), and CA is a stabilization capacitor of the circuit block A102. The semiconductor device 100 is not limited to the illustrated circuit block, and includes a plurality of circuit blocks that can independently cut off the power supply. However, for the sake of convenience of explanation, components other than the circuit block A are omitted. is doing.

  The circuit block A102 and the stabilization capacitor CA are connected between a VDDVA power supply line that supplies a power supply potential VDDVA and a VSS power supply line that supplies a reference potential VSS. Power switches PSWA0, PSWA1, PSWA2, PSWA3,... Are connected in parallel between the VDDVA power supply line and the VDD power supply line that supplies the power supply potential VDD. The VDD power supply line and the VSS power supply line are constantly applied with the power supply potential VDD and the reference potential VSS from the outside, respectively.

  Each of the power switches PSWA0, PSWA1, PSWA2, PSWA3,... Has a small size, and the power noise generated when one power switch is turned on reaches a level causing malfunction of the peripheral circuit. Such a current does not flow. However, since all of the power switches PSWA0, PSWA1, PSWA2, PSWA3,... Are turned on, the power consumption of the circuit block A can be finally supplied. The number of power switches corresponding to the circuit configuration (the load, the size of the stabilization capacitor, etc.) is provided as the power switch. In the following description, the power switch has four power switches PSWA0, PSWA1, PSWA2, and PSWA3. Will be described.

  The power switches PSWA0, PSWA1, PSWA2, and PSWA3 are on / off controlled by control signals PGA0, PGA1, PGA2, and PGA3, respectively. The control signal PGA0 is output from the power management unit 101. The control signal PGA1 is output from the logical product operation circuit (OR circuit) 103-1 as a result of logical product operation of the control signal PGA0 and the control signal PGA0 delayed for a predetermined time by the delay buffer DB1. Further, the control signal PGA2 is output from the OR circuit 103-2 as an operation result obtained by performing an AND operation on the control signal PGA0 and the control signal PGA1 delayed by a predetermined time by the delay buffer DB2. The control signal PGA3 is output from the OR circuit 103-3 as a calculation result obtained by performing an AND operation on the control signal PGA0 and the control signal PGA2 delayed by a predetermined time by the delay buffer DB3.

  As shown in FIG. 10B, when the circuit block A102 is stopped, the control signals PGA0 to PGA3 are at the high level (“H”), and the power switches PSWA0, PSWA1, PSWA2, and PSWA3 are all turned off. Is done. That is, power supply to the circuit block A102 is interrupted, and at this time, the power supply potential VDDVA is lowered to around 0V.

  When the circuit block A102 that has been cut off from power supply is operated again, the power management unit 101 asserts the control signal PGA0 to a low level (“L”). When the control signal PGA0 is asserted to “L”, the power switch PSWA0 is turned on, a current flows to the stabilization capacitor CA of the circuit block A102 via the power switch PSWA0, and charging is started. It rises.

  When the control signal PGA0 asserted to “L” is delayed by the delay buffer DB1 and input to the OR circuit 103-1, the control signal PGA1 is asserted to “L”. When the control signal PGA1 asserted to “L” is delayed by the delay buffer DB2 and input to the OR circuit 103-2, the control signal PGA2 is asserted to “L”. Further, when the control signal PGA2 asserted to “L” is delayed by the delay buffer DB3 and input to the OR circuit 103-3, the control signal PGA3 is asserted to “L”.

  By sequentially asserting the control signals PGA1, PGA2, and PGA3 to “L”, the power switches PSWA1, PSWA2, and PSWA3 are sequentially turned on, and the power supply potential VDDVA gradually increases toward the power supply potential VDD. . When the power supply potential VDDVA reaches a potential at which the circuit block A can operate, the circuit block A starts operating and enters an operating state. When stopping the operating circuit block A, the power management unit 101 deasserts the control signal PGA0 to “H”, so that the control signals PGA0 to PGA3 are deasserted to “H” at the same timing, The power supply to the circuit block A is cut off.

  As described above, in the semiconductor device shown in FIG. 10, one power switch is divided into a plurality of small sizes and configured with a large number of switches. Further, a delay buffer, which is a delay means for estimating the time when the inrush current when one switch is turned on becomes sufficiently small (convergence), is added to turn on the next switch. Then, the operation of turning on each switch is repeated so that the power supply noise is not superimposed (the potential difference PV does not become smaller than a predetermined value), and finally the switches for the size necessary to supply the current consumption of the circuit block are provided. The operation is completed by turning everything on.

JP 2008-34667 A

  In the semiconductor device shown in FIG. 10, when the power supply potential VDDVA is low, the voltage applied to both ends of the power switch, that is, the potential difference between the VDD power supply line and the VDDVA power supply line is large. Very big. Therefore, the size of the power switch must be sufficiently reduced so that the inrush current when turned on is less than or equal to the current that satisfies the standard related to power supply noise, and the time interval for turning on the next power switch is also extremely It becomes long.

  In addition, as the power supply potential VDDVA increases, the potential difference between the VDD power supply line and the VDDVA power supply line decreases, so the current flowing through the power switch per unit size also decreases. For this reason, the size of the power switch for allowing the inrush current when the switch is turned on to satisfy the standard related to power noise can be increased, and the time interval at which the next power switch can be turned on can be shortened.

  Therefore, when one power switch is composed of a plurality of power switches, the time interval required to turn on the power switch at each stage requires a longer time on the front side and a shorter time on the rear side. Therefore, in order to realize the time interval for turning on the power switch on the front stage side, a large amount of delay buffer is required, and the circuit area occupied on the chip increases. Furthermore, although a fast chip (Fast) and a slow chip (Slow) are manufactured due to manufacturing variations of the delay buffer, in order to surely suppress the inrush current, it is matched with the fast chip (Fast). It is necessary to set a delay value. Therefore, in a chip (Slow) that operates slowly, the delay value becomes longer than necessary, and the period (start-up time) during which the circuit block shifts from the stopped state to the operating state becomes longer.

  Although it is conceivable to control the delay time by using a clock counter or the like, a separate clock for turning on the power switch is required, resulting in an increase in man-hours required for the design and logic verification of the semiconductor device.

  According to one aspect of the present invention, a power management unit that manages power supply to a circuit block that can cut off power supply, a plurality of power switches that control power supply to a first circuit block, and a first circuit There is provided a semiconductor device having a delay generator that operates with a power supply supplied to a block and generates a delay corresponding to the potential. When the plurality of power switches are controlled to be turned on to supply power to the first circuit block, the plurality of power switches are configured to supply power to the first circuit block based on outputs of the power management unit and the delay generator. The devices are sequentially turned on at time intervals according to the potential.

  In the disclosed semiconductor device, when the potential of the power supply supplied to the circuit block is low, the time interval for turning on the power switch is lengthened and the potential is increased due to the delay according to the potential of the power supply generated by the delay generator. Accordingly, the time interval for turning on the power switch can be shortened. Therefore, even if a large amount of delay buffer is not used to control each power switch, the delay generator is used to suppress an increase in circuit area and appropriately control the time interval for turning on the power switch. be able to.

It is a figure which shows an example of the semiconductor device in embodiment of this invention. It is a figure which shows the structural example of the semiconductor device in this embodiment. It is a figure which shows the structural example of the ring oscillator activation part shown in FIG. 2, a ring oscillator part, and a level conversion part. It is a figure which shows the operation example of the semiconductor device in this embodiment. It is a figure which shows the truth table of the flip-flop shown in FIG. It is a figure which shows the relationship between the power supply voltage supplied to a ring oscillator, and an oscillation period. It is a figure for demonstrating the starting time according to the manufacture dispersion | variation in this embodiment. It is a figure for demonstrating the outline | summary of a power gating technique. It is a figure for demonstrating the problem regarding the power supply noise which may generate | occur | produce by application of a power gating technique. It is a figure which shows the example of the suppression technique of the power supply noise in a semiconductor device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating an example of a semiconductor device according to an embodiment of the present invention. The semiconductor device according to the present embodiment is a semiconductor device having a plurality of circuit blocks and capable of controlling power supply in units of circuit blocks. In addition, it has a power switch composed of a plurality of small-sized power switches as power switches for controlling power supply to the circuit block, and the small-sized power switches are turned on at different timings. Suppresses the generation of power supply noise due to inrush current.

  FIG. 1A is a diagram illustrating a configuration example of a semiconductor device in this embodiment. In FIG. 1A, 10 is a semiconductor device, 11 is a power management unit (PMU), 12 is a circuit block A (CBLA) capable of shutting off power supply, CA is a stabilizing capacity of the circuit block A12, and 13 is delay generation. (DLG). The semiconductor device 10 includes not only the circuit block shown in the figure but also a circuit block that can cut off a plurality of power supplies.

  The power management unit 11 performs power management in the semiconductor device 10. The power management unit 11 is always supplied with power, and manages power supply to each circuit block included in the semiconductor device 10. The power management unit 11 supplies power to the circuit block corresponding to the power switch by controlling the power switch to the on state, or to the circuit block corresponding to the power switch by controlling the power switch to the off state. Or shut off the power supply.

  The circuit block A12 and the stabilization capacitor CA are connected between a power supply line (VDDVA power supply line) that supplies the power supply potential VDDVA and a power supply line (VSS power supply line) that supplies the reference potential VSS. Power switches PSWA0, PSWA1, PSWA2, and PSWA3 are connected in parallel between the VDDVA power supply line and the power supply line (VDD power supply line) that supplies the power supply potential VDD. The power switches PSWA0, PSWA1, PSWA2, and PSWA3 are, for example, transistors (P channel transistors in the illustrated example). The VDD power supply line and the VSS power supply line are constantly applied with the power supply potential VDD and the reference potential VSS from the outside, respectively. FIG. 1A shows an example in which four power switches PSWA0 to PSWA3 are provided as power switches for controlling power supply to the circuit block A12. However, the present invention is not limited to this. The number of power switches according to the circuit configuration and the like is provided.

  Each of the power switches PSWA0, PSWA1, PSWA2, and PSWA3 is of a small size, and the current at which the power noise generated when one power switch is turned on reaches a level causing malfunction of the peripheral circuit is not Not flowing. Since the power switches PSWA0 to PSWA3 are all turned on, the power switch PSWA0 to PSWA3 have a size that can finally supply the current consumption of the circuit block A.

  The power switches PSWA0, PSWA1, PSWA2, and PSWA3 are ON / OFF controlled by control signals GA0, GA1, GA2, and GA3, respectively. The control signal GA0 is a signal output from the power management unit 11. The control signal GA1 is a signal obtained by performing an AND operation on the control signal GA0 and the delay signal DSA1 by an AND operation circuit (OR circuit) 14-1. The control signal GA2 is a signal obtained by performing an AND operation on the control signal GA0 and the delay signal DSA2 by the OR circuit 14-2. The control signal GA3 is a signal obtained by performing an AND operation on the control signal GA0 and the delay signal DSA3 by the OR circuit 14-3.

  The delay generator 13 operates at the same power supply potential VDDVA that is supplied to the circuit block A whose power supply is controlled by the power switches PSWA0 to PSWA3, and outputs delay signals DSA1, DSA2, and DSA3. The delay signals DSA1 to DSA3 have larger delay values in the order of the delay signals DSA1, DSA2, and DSA3. The delay generator 13 utilizes the voltage dependency of the delay element, and as shown in FIG. 1B, the delay is long when the power supply potential VDDVA is low, and the delay is shortened as the power supply potential VDDVA increases. Generate.

  That is, when the power supply potential VDDVA increases toward the power supply potential VDD, the delay generator 13 changes the delay signals DSA1 to DSA3 from the high level ("H") to the low level (in accordance with the potential of the power supply potential VDDVA). Assert to “L”). For example, the delay generator 13 sets the delay signal DSA1 to “L” when the power supply potential VDDVA reaches the first potential, and sets the delay signal DSA2 to “L” when the second potential higher than the first potential is reached. When the third potential higher than the second potential is reached, the delay signal DSA3 is set to “L”.

  In the semiconductor device shown in FIG. 1A, when power supply is started to the circuit block A12 whose power supply is interrupted, the power management unit 11 asserts the control signal GA0 to “L”. As a result, the power switch PSWA0 at the first stage is turned on, a current flows through the stabilization capacitor CA of the circuit block A12 via the power switch PSWA0, charging starts, and the power supply potential VDDVA rises.

  When the power supply potential VDDVA in the short period after the power switch PSWA0 is turned on is low, that is, when the potential difference between the VDD power supply line and the VDDVA power supply line is large, the delay generator 13 is long because the power supply potential VDDVA is low. Generate a delay. When the power supply potential VDDVA increases and the power supply potential VDDVA increases, that is, when the potential difference between the VDD power supply line and the VDDVA power supply line decreases, the delay generator 13 increases the power supply potential VDDVA. Generates a short delay. Therefore, as shown in FIG. 1C, the power supply potential VDDVA also rises as the power switches PSWA0, PSWA1, PSWA2, and PSWA3 are sequentially turned on, so the time interval for turning on the power switches PSWA0 to PSWA3 is Then, as the process proceeds to the rear stage side (with the rise of the power supply potential VDDVA), it automatically becomes shorter.

  As a result, when the power supply potential VDDVA is low (the potential difference between the VDD power supply line and the VDDVA power supply line is large) and the current flowing through the power switch is large, the time interval for turning on the next power switch is set to be long. . As the power supply potential VDDVA rises, the potential difference between the VDD power supply line and the VDDVA power supply line becomes smaller and the current flowing through the power switch becomes smaller, so the time interval for turning on the next power switch is automatically shortened. Will be set. Therefore, it is possible to supply power to the circuit block in an appropriate start-up time without generating power supply noise that causes the operating circuit to malfunction. In addition, since it is not necessary to provide a large amount of delay buffers as in the prior art, an increase in circuit area can be suppressed.

  When the power supply to the circuit block A12 is cut off, the power management unit 11 sets the control signal GA0 to "H", so that the control signals GA1 to GA3 are controlled regardless of the delay signals DSA1 to DSA3 from the delay generator 13. Becomes “H”. Accordingly, the power switches PSWA0, PSWA1, PSWA2, and PSWA3 are turned off at the same timing when the control signal GA0 from the power management unit 11 becomes “H”, and the power supply to the circuit block A12 is cut off.

FIG. 2 is a diagram illustrating a specific configuration example of the semiconductor device according to the present embodiment.
In FIG. 2, 20 is a semiconductor device, 21 is a power management unit (PMU), 22 is a circuit block A (CBLA), and CA is a stabilization capacitor of the circuit block A22. Reference numeral 23 is a ring oscillator (ROSC) activating unit, 24 is a ring oscillator (ROSC) unit, and 25 is a level converting unit. FFAi (i is a subscript, i = 1 to n is a natural number, the same applies to the following) is a flip-flop with reset, and PSWA0 and PSWAi are power switches for supplying power to the circuit block A12. It is. Note that the semiconductor device 20 includes a plurality of circuit blocks in addition to the illustrated circuit blocks. Further, power supply to the circuit blocks included in the semiconductor device 20 can be cut off in units of circuit blocks.

  The power management unit 21 is always supplied with the power supply potential VDD and performs power management in the semiconductor device 20. The power management unit 21 controls power supply to a circuit block corresponding to the power switch by controlling on / off of the power switch, and manages power supply to each circuit block included in the semiconductor device 20.

  The circuit block A22 and the stabilization capacitor CA are connected between a power supply line (VDDVA power supply line) that supplies the power supply potential VDDVA and a power supply line (VSS power supply line) that supplies the reference potential VSS. Power supply switches PSWA0 and PSWAi are connected in parallel between the VDDVA power supply line and a power supply line (VDD power supply line) that supplies the power supply potential VDD. The power switches PSWA0 and PSWAi are, for example, transistors (P channel transistors in the illustrated example). The VDD power supply line and the VSS power supply line are constantly applied with the power supply potential VDD and the reference potential VSS from the outside, respectively.

  Each of the power switches PSWA0 and PSWAi is of a small size, and no current flows such that the power noise generated when one power switch is turned on reaches a level causing malfunction of the peripheral circuit. The power switches PSWA0 and PSWAi are all turned on, so that the power consumption of the circuit block A can be finally supplied.

  The power switch PSW0 is ON / OFF controlled by a control signal GA0 output from the power management unit 21. The power switch PSWi is supplied with the output Q of the flip-flop FFAi as the control signal GAi, and is turned on / off by the control signal GAi.

  In the flip-flop FFAi, the control signal GA (i−1) is input to the input D, the reset signal RST (control signal GA0) is input to the reset input R, and the oscillation signal OSC is input to the clock input. FIG. 5 shows a truth table of the flip-flop FFAi. When the reset input R is “1” (“H”), the flip-flop FFAi outputs “1” (“H”) as the output Q regardless of other inputs. Further, the flip-flop FFAi has a positive edge (Posedge) when the reset input R is “0” (“L”) and the clock input changes from “0” → “1” (“L” → “H”). The input D is output as the output Q. Note that the flip-flop FFAi holds the output Q when the reset input R is “0” (“L”) and the clock input is not a positive edge (Posedge).

  The ROSC activation unit 23 is for activating the ROSC unit 24 and outputs a signal instructing activation (instructing operation start) to the ROSC unit 24 and the level conversion unit 25. The ROSC unit 24 is a ring oscillator configured using, for example, CMOS transistors, and operates at the power supply potential VDDVA supplied to the circuit block A22. The level conversion unit 25 converts the internal oscillation signal at the level of the power supply potential VDDVA output from the ROSC unit 24 into a signal at the level of the power supply potential VDD and outputs it as the oscillation signal OSC. This is for controlling a circuit (flip-flop FFAi) that operates with the signal of the power supply potential VDD level based on the signal of the power supply potential VDDVA output from the ROSC unit 24. In the semiconductor device illustrated in FIG. 2, the function corresponding to the delay generator 13 illustrated in FIG. 1 is realized by the ROSC activation unit 23, the ROSC unit 24, and the level conversion unit 25.

  FIG. 3 is a diagram illustrating a configuration example of the ROSC activation unit 23, the ROSC unit 24, and the level conversion unit 25 illustrated in FIG.

  The ROSC activation unit 23 includes P-channel transistors Q11 and Q13, N-channel transistors Q12 and Q14, resistors R11 and R12, and a capacitor C11. Here, at least the P channel transistor Q11 and the N channel transistor Q12 are configured using the same transistors as the P channel transistor and the N channel transistor used in the ROSC unit 24.

  The transistor Q11 has a source connected to the VDDVA power supply line, a gate connected to the VSS power supply line, and a drain connected to one end of the resistor R11. The other end of the resistor R11 is connected to the VSS power supply line. The other end of the capacitor C11 having one electrode connected to the VSS power supply line and the gate of the transistor Q12 are connected to a connection point between the drain of the transistor Q11 and one end of the resistor R11. The transistor Q12 has a source connected to the VSS power supply line and a drain connected to one end of the resistor R12. The other end of the resistor R12 is connected to the VDD power supply line. The gates of the transistors Q13 and Q14 are connected to a connection point between the drain of the transistor Q12 and one end of the resistor R12. Transistor Q13 has a source connected to the VDD power supply line and a drain connected to the drain of transistor Q14. The source of the transistor Q14 is connected to the VSS power supply line. The potential at the connection point between the drain of the transistor Q13 and the drain of the transistor Q14 is output as the start signal start.

  In the ROSC activation unit 23, the drain potential not of the transistor Q12 is substantially the power supply potential VDD until the power supply potential VDDVA supplied from the VDDVA power supply line exceeds the threshold value of the transistor. Therefore, the start signal start output from the ROSC activation unit 23 is “L” (VSS).

  When the power supply potential VDDVA supplied from the VDDVA power supply line rises and exceeds the threshold value of the transistor Q11, the drain potential pout of the transistor Q11 becomes “H” (VDDVA). Further, when the power supply potential VDDVA rises and the potential pout exceeds the threshold value of the transistor Q12, the transistor Q12 is turned on, and the potential nout of the drain of the transistor Q12 becomes “L” (VSS). Therefore, the start signal start output from the ROSC activation unit 23 changes from “L” (VSS) to “H” (VDD).

  As described above, the ROSC activation unit 23 detects whether or not the power supply potential VDDVA supplied from the VDDVA power supply line exceeds the threshold value of a transistor used in the ROSC. The ROSC activation unit 23 sets the start signal start to “H” (VDD) when the power supply potential VDDVA exceeds the threshold value of the transistor, and starts when the power supply potential VDDVA does not exceed the threshold value of the transistor. The signal start is set to “L” (VSS).

  The ROSC unit 24 has a plurality of inverters configured by, for example, CMOS transistors, an inverter group 32 in which the plurality of inverters are cascade-connected, and a negative logic for controlling the operating state (activation or stop) of the ROSC unit 24 It has a product (NAND) gate 31. The NAND gate 31 included in the ROSC unit 24 and the plurality of inverters in the inverter group 32 operate at the power supply potential VDDVA supplied from the VDDVA power supply line.

  The NAND gate 31 receives the start signal “start” output from the ROSC activation unit 23, the control signal GAn, and the first output of the inverter group 32, and outputs the calculation result to the input terminal of the inverter group 32. A ring oscillator is formed by the NAND gate 31 and the inverter group 32, and the second output of the inverter group 32 is output as the internal oscillation signal oscp.

  The ROSC unit 24 does not oscillate when the start signal start from the ROSC activation unit 23 is “L”. The ROSC unit 24 oscillates when the start signal start from the ROSC activation unit 23 is “H” and the control signal GAn is “H”, “L” is set as the reference potential VSS, and “H” is supplied as the power source. An internal oscillation signal oscp having the potential VDDVA is output. In the ROSC unit 24, the start signal start from the ROSC activation unit 23 is “H”, but the control signal GAn is “L” (the power switch PSWAn at the last stage is turned on, that is, the power switches PSWA0 to PSWANn). When all are on), the oscillation operation stops.

  Here, the NAND gate 31 in the ROSC unit 24 and the plurality of inverters in the inverter group 32 operate at the power supply potential VDDVA supplied from the VDDVA power supply line. Therefore, as shown in FIG. 6, the ROSC unit 24 oscillates with a long cycle when the power supply potential VDDVA is low, and oscillates with a short cycle as the power supply potential VDDVA increases. That is, the internal oscillation signal oscp output from the ROSC unit 24 is an oscillation signal oscillated at a cycle corresponding to the power supply potential VDDVA. The cycle is long when the power supply potential VDDVA is low, and the cycle is short when the power supply potential VDDVA is high. .

  Note that if the oscillation switch of the ROSC unit 24 is not stopped even when the power switch PSWAn, which is the last stage, is turned on, that is, all of the power switches PSWA0 and PSWAi are turned on, it is necessary to input the control signal GAn to the NAND gate 31. There is no. However, as shown in FIG. 3, by stopping the oscillation operation of the ROSC unit 24 when the power switch PSWAn which is the last stage is turned on, unnecessary oscillation operation is prevented and power consumption is increased. Can be prevented.

  The level conversion unit 25 includes P-channel transistors Q15, Q17, Q19, and Q22, N-channel transistors Q16, Q18, Q20, and Q21, and inverters 33 and 34. Transistor Q15 has a source connected to the VDD power supply line and a drain connected to the drain of transistor Q16. The source of the transistor Q16 is connected to the VSS power supply line, and the internal oscillation signal oscp from the ROSC unit 24 is supplied to the gate. Transistor Q17 has a source connected to the VDD power supply line and a drain connected to the drain of transistor Q18. The source of the transistor Q18 is connected to the VSS power supply line, and the internal oscillation signal oscp from the ROSC unit 24 is supplied to the gate via the inverter 33. The inverter 33 operates with the power supply potential VDDVA supplied from the VDDVA power supply line. The gate of the transistor Q17 is connected to the connection point of the drains of the transistors Q15 and Q16, and the gates of the transistors Q15, Q19, and Q20 are connected to the connection point of the drains of the transistors Q17 and Q18.

  Transistor Q19 has a source connected to the VDD power supply line and a drain connected to the drain of transistor Q20. Transistor Q20 has its source connected to the drain of transistor Q21. The source of the transistor Q21 is connected to the VSS power supply line, and the start signal start from the ROSC activation unit 23 is supplied to the gate. The source of the transistor Q22 is connected to the VDD power supply line, and the start signal start from the ROSC activation unit 23 is supplied to the gate. The connection point of the drains of the transistors Q19 and Q20 and the drain of the transistor Q22 are connected to the input terminal of the inverter 34 that operates at the power supply potential VDD supplied from the VDD power supply line, and the output of the inverter 34 is output as the oscillation signal OSC. The

  When the start signal start from the ROSC activation unit 23 is “L”, the level conversion unit 25 turns on the transistor Q22 and fixes the oscillation signal OSC to “L” (VSS). Then, when the start signal start from the ROSC activation unit 23 becomes “H”, the level conversion unit 25 converts the signal level of the internal oscillation signal oscp from the ROSC unit 24, and changes the level to “L” according to the internal oscillation signal oscp. An oscillation signal OSC is output with "" as the reference potential VSS and "H" as the power supply potential VDD.

  Next, operation of the semiconductor device illustrated in FIG. 2 will be described. FIG. 4 is a diagram illustrating an operation example of the semiconductor device illustrated in FIG. 2, and illustrates a case where the circuit block A <b> 22 in which power supply is interrupted and stopped is put into an operation state.

  When power supply to the circuit block A22 is interrupted, the control signal GA0 output from the power management unit 21 is “H”. At this time, since the reset signal RST input to the reset input R of the flip-flop FFAi is also “H”, the output Q of the flip-flop FFAi, that is, the control signal GAi becomes “H”. Therefore, all of the power switches PSWA0 and PSWAi are turned off.

  In this state, when the power management unit 21 asserts the control signal GA0 to “L” in order to supply power to the circuit block A22, the first-stage power switch PSWA0 is turned on. At the same time, the reset signal RST becomes “L”, the reset of the flip-flop FFAi is released, and the power switch PSWA1 waits with the first positive edge of the oscillation signal OSC as a trigger. On the other hand, when the power switch PSWA0 is turned on, the power supply potential VDDVA supplied through the VDDVA power supply line starts to rise. However, the start signal “start” output from the ROSC activation unit 23 remains “L” during a period when the power supply potential VDDVA is low (when the power supply potential VDDVA does not reach a sufficient level at which the ROSC unit 24 can operate). Therefore, the ROSC unit 24 does not perform an oscillation operation, and the oscillation signal OSC output from the level conversion unit 25 is also fixed to “L”. Thereby, it is possible to prevent an indefinite signal from being propagated to the flip-flop FFAi as the oscillation signal OSC.

  When the power supply potential VDDVA further rises and the ROSC activation unit 23 detects that the threshold value of the P-channel transistor used in the ROSC unit 24 has been exceeded, the potential pout of the drain of the transistor Q11 rises. Further, when the ROSC activating unit 23 detects that the threshold value of the N-channel transistor used in the ROSC unit 24 has been exceeded, the potential nout of the drain of the transistor Q12 falls. As the potential nout of the drain of the transistor Q12 falls, the start signal start output from the ROSC activation unit 23 becomes “H”, and the ROSC unit 24 and the level conversion unit 25 are activated.

  When activated, the ROSC unit 24 starts an oscillation operation and outputs an internal oscillation signal oscp having a period corresponding to the power supply potential VDDVA. Further, the level conversion unit 25 converts the level of the internal oscillation signal oscp at the level of the power supply potential VDDVA into an oscillation signal OSC at the level of the power supply potential VDD and outputs it.

  When the oscillation signal OSC output from the level converter 25 is input to the flip-flop FFAi, the control signal GA1 becomes “L” by the first positive edge in the oscillation signal OSC. As a result, in addition to the power switch PSWA0, the power switch PSWA1 is turned on, and the power switch PSWA2 waits with the next positive edge of the oscillation signal OSC as a trigger. Thereafter, one power switch is turned on by the positive edge of the oscillation signal OSC and the state where the next power switch waits with the next positive edge of the oscillation signal OSC as a trigger is repeated, so that the power switch PSWAi is sequentially turned on. Turns on. When the last-stage power switch PSWAn is turned on, that is, when the control signal GAn becomes “L”, the ROSC unit 24 stops the oscillation operation.

Here, as shown in FIG. 4, as the power supply potential VDDVA increases, the oscillation period of the internal oscillation signal oscp output from the ROSC unit 24 becomes shorter, and the time between positive edges in the oscillation signal OSC. The interval is also shortened. That is, as the value of i increases in the power switch PSWAi (goes to the subsequent stage), the time interval for turning on the power switch PSWAi becomes shorter.

  According to the present embodiment, the operation is performed with the power supply potential supplied to the corresponding circuit block, the delay is long when the power supply potential is low, and the delay is generated so that the delay is shortened as the power supply potential becomes high. The power switches are sequentially turned on using the output of the delay generator. The time interval for turning on the power switch on the preceding stage that is sequentially turned on when the power supply potential supplied to the circuit block is low is lengthened, and the time that is turned on for the power switch on the subsequent stage that is sequentially turned on after the power supply potential is increased. The interval can be shortened. Therefore, even if a large amount of delay buffer is not used to control each power switch, an increase in circuit area can be suppressed with a delay generator of a small circuit, and the time interval for sequentially turning on the power switch can be controlled appropriately. Can do.

  Further, in order to shorten the start-up time required for the transition from the stopped state to the operating state, for example, in the semiconductor device as shown in FIG. 10A, the power supply potential supplied to the circuit block is increased toward the subsequent stage side. Adjustments are made to shorten the time interval for turning on the power switch. This adjustment needs to be performed for each delay buffer provided for each power switch. On the other hand, in this embodiment, the time interval for turning on the power switch can be automatically adjusted by one delay generator in accordance with the power supply potential supplied to the circuit block.

  Further, according to the present embodiment, it is possible to suppress the variation in the startup time according to the manufacturing variation of the semiconductor device. In a chip with a slow operation (Slow), the leakage current flowing in the internal circuit is smaller than that of a chip with a fast operation, so that the potential rise after turning on the power switch is fast in the chip with a slow operation as shown in FIG. . For example, the power supply potential after the time t1 has passed since the power switch is turned on is set to the potential V1 for the slow-operating chip and the potential V2 (V2 <V1) for the fast-operating chip. When the ring oscillator is used as the delay generator as shown in FIG. 3, if the power supply potential is the same, the oscillation frequency of the slow operating chip is the oscillation frequency of the fast operating chip as shown in FIG. 7B. Longer than. However, according to the present embodiment, the power supply potential after the same time has elapsed since the power switch was turned on is higher in the chip with slower operation. Is small as shown in FIG. 7B, and variation in startup time is suppressed.

The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Appendix 1)
A semiconductor device having at least one circuit block and capable of interrupting power supply in units of the circuit block,
A power management unit that manages power supply to the circuit block;
A plurality of power switches for controlling power supply to the first circuit block;
A delay generator that operates with a power source supplied to the first circuit block and generates a delay according to the potential of the power source;
When the plurality of power switches are controlled to be turned on to supply power to the first circuit block, the plurality of power switches are connected to the first circuit block based on outputs of the power management unit and the delay generator. A semiconductor device which is sequentially turned on at time intervals according to the potential of a power supply to be supplied.
(Appendix 2)
When the plurality of power switches are controlled to be turned on to supply power to the first circuit block, one power switch of the plurality of power switches is output from the power management unit. The semiconductor according to claim 1, wherein the semiconductor device is turned on by a control signal, and other power switches of the plurality of power switches are sequentially turned on by the control signal delayed by the output of the delay generator. apparatus.
(Appendix 3)
The semiconductor device according to appendix 1 or 2, wherein the delay generator generates a delay that decreases as the potential of the supplied power source increases.
(Appendix 4)
The plurality of power switches are connected in parallel between a power supply line to which a predetermined potential is externally supplied and a power supply line for supplying power to the first circuit block. The semiconductor device according to any one of?
(Appendix 5)
The delay generator is
An oscillator that operates with a power source supplied to the first circuit block and outputs an oscillation signal having a frequency corresponding to the potential of the power source;
An oscillator activation unit for activating the oscillator;
The semiconductor device according to any one of appendices 1 to 4, further comprising: a level conversion unit that converts an oscillation signal output from the oscillator into a signal for controlling the plurality of power switches. .
(Appendix 6)
6. The semiconductor device according to claim 5, wherein the oscillator activating unit activates the oscillator by detecting that a potential of a power source supplied to the oscillator has reached an operable potential of the oscillator.
(Appendix 7)
It has a plurality of flip-flops that are vertically connected and each clock input is input to the output of the level conversion unit,
A control signal for turning on the plurality of power switches output from the power management unit is input to the flip-flop at the first stage, and the output of each flip-flop controls the corresponding power switch among the plurality of power switches. 7. The semiconductor device according to appendix 5 or 6, wherein the semiconductor device is output as a signal.
(Appendix 8)
8. The semiconductor device according to any one of appendices 5 to 7, wherein the oscillator is a ring oscillator that operates with power supplied to the first circuit block.
(Appendix 9)
9. The semiconductor device according to any one of appendices 1 to 8, wherein the delay generator is stopped when all of the plurality of power switches are turned on.
(Appendix 10)
When the plurality of power switches are controlled to be turned off in order to cut off the power supply to the first circuit block, the same timing is determined based on the output of the power management unit regardless of the output of the delay generator. The semiconductor device according to any one of appendices 1 to 9, wherein the semiconductor device is turned off.

DESCRIPTION OF SYMBOLS 11, 21 Power management unit 12, 22 Circuit block 13 Delay generator 23 Ring oscillator activation part 24 Ring oscillator part 25 Level conversion part CA Stabilization capacity PSWA Power switch VDDVA Power supply line for supplying power to the circuit block

Claims (5)

A semiconductor device having at least one circuit block and capable of interrupting power supply in units of the circuit block,
A power management unit that manages power supply to the circuit block;
A plurality of power switches for controlling power supply to the first circuit block;
A delay generator that operates with a power source supplied to the first circuit block and generates a delay according to the potential of the power source;
When the plurality of power switches are controlled to be turned on to supply power to the first circuit block, the plurality of power switches are connected to the first circuit block based on outputs of the power management unit and the delay generator. A semiconductor device which is sequentially turned on at time intervals according to the potential of a power supply to be supplied.   When the plurality of power switches are controlled to be turned on to supply power to the first circuit block, one power switch of the plurality of power switches is output from the power management unit. 2. The power switch according to claim 1, wherein the power switch is turned on by a control signal, and other power switches of the plurality of power switches are sequentially turned on by the control signal delayed by the output of the delay generator. Semiconductor device.   3. The semiconductor device according to claim 1, wherein the delay generator generates a delay that becomes shorter as a potential of a supplied power source becomes higher. The delay generator is
An oscillator that operates with a power source supplied to the first circuit block and outputs an oscillation signal having a frequency corresponding to the potential of the power source;
An oscillator activation unit for activating the oscillator;
4. The semiconductor according to claim 1, further comprising: a level converter that converts an oscillation signal output from the oscillator into a signal for controlling the plurality of power switches. 5. apparatus.   5. The semiconductor device according to claim 1, wherein operation of the delay generator is stopped when all of the plurality of power switches are turned on. 6.

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