CN101743631B - 硼衍生的材料的沉积方法 - Google Patents

硼衍生的材料的沉积方法 Download PDF

Info

Publication number
CN101743631B
CN101743631B CN2008800245001A CN200880024500A CN101743631B CN 101743631 B CN101743631 B CN 101743631B CN 2008800245001 A CN2008800245001 A CN 2008800245001A CN 200880024500 A CN200880024500 A CN 200880024500A CN 101743631 B CN101743631 B CN 101743631B
Authority
CN
China
Prior art keywords
boron
precursor
network
film
chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008800245001A
Other languages
English (en)
Other versions
CN101743631A (zh
Inventor
J-u·许
M·巴尔塞努
夏立群
D·威蒂
H·M·塞德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN101743631A publication Critical patent/CN101743631A/zh
Application granted granted Critical
Publication of CN101743631B publication Critical patent/CN101743631B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/28Deposition of only one other non-metal element
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832Multiple layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

本发明揭示一种形成含硼膜的方法。该方法包含:将一含硼前体导入一腔室内,以及通过热分解工艺或等离子工艺沉积一包含硼-硼键结的网络于一基板上。该网络可以被后处理,以从该网络去除氢且增加最终含硼膜的应力。该含硼膜具有介于约-10Gpa与约10Gpa之间的应力,并且可以作为硼源层或诱导伸张层。

Description

硼衍生的材料的沉积方法
技术领域
本发明的实施例大体上有关于在基板(例如半导体基板)上形成膜的方法。特别地,本发明的实施例有关于用以在基板上形成含硼膜的方法。
背景技术
自从数十年前引进集成电路器件,集成电路几何形态的尺寸已经显著地减小。自当时,集成电路大致上遵循着两年/一半尺寸的规则(通常称为摩尔定律(
Figure GSB00000776674600011
Law)),其意指芯片上的器件数目每两年会翻一番。今日的制造设施惯常地制造具有90nm特征尺寸的器件,并且明日的设施即将制造具有甚至更小特征尺寸的器件。
在基板上,器件几何形态的持续缩小与器件的致密间隔的持续增加对于改善器件性能已经呈现挑战性。例如,虽然金属-氧化物-半导体场效应晶体管(MOSFET)器件的性能可以通过一些方法来改善(例如减小器件的栅极介电质厚度),小器件要求的非常薄的介电层会使掺杂质从栅极电极穿透栅极介电质而进入下方的硅基板。非常薄的栅极介电质也会增加栅极漏电流,其会增加栅极消耗的功率量且最终损坏晶体管。
使器件中材料的原子晶格应变是近来发展的改善器件性能的替代方法。使原子晶格应变可通过提高半导体材料中的载流子迁移率而改善器件性能。器件的一层的原子晶格可以通过在所述层上方沉积应力膜来应变。例如在栅极电极上方作为蚀刻终止层的应力氮化硅(SiN)层可以被沉积,以在晶体管的沟道区域中诱导应变。此应力的应变诱导的氮化硅层可具有压应力或张应力。
虽然已经发展出具有相当高应力程度的等离子体增强化学气相沉积(PECVD)的氮化硅层,仍存在用以形成膜的方法的需求,其中所述膜具有比氮化硅(氮化硅典型地具有不超过1.7Gpa的张应力)更高的张应力程度。
发明内容
本发明的实施例大致上提供形成含硼膜的方法。在一个实施例中,一种形成含硼膜的方法包括:将含硼前体导入腔室内,并在所述腔室中在不存在等离子体的情况下通过热分解工艺从所述含硼前体在基板上沉积包含硼-硼键的网络。所述网络被后处理以从所述网络去除氢。所述经后处理的网络形成一含硼膜,所述含硼膜包含B12二十面体与/或融合的B12二十面体,并且具有介于约-10Gpa与约10Gpa之间的应力。
在另一实施例中,一种形成含硼膜的方法包括:将含硼前体导入腔室内,以及在所述腔室中在存在等离子体的情况下从所述含硼前体在基板上沉积包含硼-硼键的网络。所述网络形成含硼膜,所述含硼膜包含B12二十面体与/或融合的B12二十面体,并且具有介于约-10Gpa与约10Gpa之间的应力。
在进一步实施例中,本发明提供使用含硼膜的方法。在一个实施例中,含硼膜被用来以硼掺杂位于下方的层。在另一实施例中,一种处理基板的方法包括:在基板上的晶体管结构上方沉积衬里层;在所述衬里层上形成含硼膜;以及在所述含硼膜上沉积盖层。预金属介电层被沉积在所述盖层上。所述预金属介电层、所述盖层、所述含硼膜与所述衬里层接着被蚀刻,以形成到所述晶体管结构的栅极叠层的接触通孔。通过所述蚀刻暴露的含硼膜区域接着被密封。密封所述暴露区域可以包括在所述晶体管结构上方(包括所述含硼膜的暴露区域)沉积介电衬里层,或以氮化或氧化工艺来处理所述暴露区域。
附图说明
本发明的前述特征、详细说明可以通过参照实施例而更加了解,其中一些实施例绘示在附图中。然而,应了解,附图仅绘示本发明的典型实施例,因而不会限制本发明范围,本发明允许其它等效的实施例。
图1为概述含硼前体的聚合反应与最终结构的图表。
图2为显示UV硬化工艺对于根据本发明实施例所沉积的含硼膜的应力的影响的曲线图。
图3为在进行UV硬化工艺之前(如所沉积)与之后(后UV硬化)的含硼膜的FTIR分析。
图4为显示通过单一沉积与UV后处理(即单一沉浸)或多个循环的沉积与UV后处理(即沉浸净化)而获得的膜厚度的比较的曲线图。
图5为显示通过单一沉积与UV后处理(即单一沉浸)或多个循环的沉积与UV后处理(即沉浸净化)而获得的膜应力的比较的曲线图。
图6A-6F绘示根据本发明实施例的集成方案。
掩模间隔漏极具体实施方式
本发明的实施例提供沉积含硼膜(例如氮化硼与碳化硼膜)的方法。含硼膜可以是未掺杂的氮化硼(BN)、未掺杂的碳化硼(BC)膜,或是掺杂的氮化硼或碳化硼膜,诸如氮化硼硅(BSiN)、氮化硼碳(BCN)、氮化硅硼(SiBN)与氮化硼碳硅(BCSiN)膜。含硼膜具有高的内应力(即介于约-10Gpa与约10Gpa之间),诸如大于约2.0Gpa的张应力。相信这些膜的高应力至少部分是来自膜中B12二十面体的存在。具有高张应力(即大于约2.0Gpa的应力)的含硼膜的硼含量可以介于约5原子%与约100原子%之间。张应力一般是随着硼含量而增加。
含硼膜的沉积及其性质
在一个实施例中,含硼膜通过热分解工艺(即非等离子体工艺)以及随后的后处理来沉积。对于热分解工艺,在沉积期间,腔室中基板支撑件的温度可以设定在介于约100℃与约1000℃之间(例如介于约300℃与约500℃之间),并且腔室中压力可以介于约10mTorr与约760Torr之间(例如介于约2Torr与约10Torr之间)。含硼前体以例如介于约5sccm与约50slm之间的流速(例如介于约10sccm与约1slm)被导入腔室,并且被热解。能够用在沉积的腔室的实例为SE与
Figure GSB00000776674600032
GT PECVD腔室,此两者皆可由美国加州圣克拉拉市的应用材料公司(Applied Materials,Inc.)购得。在此提供的处理条件用于300mm
Figure GSB00000776674600033
SE腔室,其中所述腔室具有两分离的处理区域,每一处理区域处理一个基板。因此,每一基板处理区域与基板感受到的流速为流入腔室的流速的一半。
包含硼-硼键的网络是在含硼前体的热解期间形成在基板支撑件上的基板上。基板可以是硅基板、含硅基板或玻璃基板。基板可以是裸基板,或具有一或多个沉积于其上的材料层与/或形成于其中的特征。包括硼-硼键的网络可以具有大于约10Mpa的张应力,并且包括介于约3与约50之间的原子百分比的氢。包含硼-硼键的网络可以是非晶形或具有低程度的结晶性,并且包括通过硼-硼键随机联结的硼环。在一个方面中,非晶形硼:氢网络是通过B2H6聚合形成在基板上,
在形成包含硼-硼键的网络之后,该网络被后处理以从网络去除氢。从网络去除氢可以增加网络的张应力。后处理是从以下组中选择的:等离子体工艺、紫外线(UV)硬化工艺、热退火工艺与以任何顺序的以上组合。例如,包含硼-硼键的网络能够以UV硬化工艺且接着以等离子体工艺来处理。图1绘示含硼前体在聚合期间所发生的反应,这些反应用于在后处理之后形成含硼膜中的包含B12二十面体10的结构。
对于等离子体工艺后处理,可以通过被输送至腔室的喷洒头电极与/或基板支撑件电极的RF功率来提供等离子体。RF功率可以被提供于介于约2W与约5000W之间的功率电平(例如介于约30W与约1000W之间)和介于约100kHz与高达约1M Hz之间的单一低频率(例如介于约300kHz与约400κHz之间),或是介于约2W与约5000W之间的功率电平(例如介于约30W与约1000W之间)和大于约1MHz到高达约60MHz的单一高频率(例如13.6MHz)。替代地,RF功率可以被提供于混合频率,其中所述混合频率包括在介于约2W与约5000W之间的功率电平(例如介于约30W与约1000W之间)的介于约100kHz与约1MHz之间的第一频率(例如约300kHz与约400κHz),和在介于约2W与约5000W之间的功率电平(例如介于约30W与约1000W之间)的大于约1MHz的第二频率(例如例如大于约1MHz到高达约60MHz,例如13.6MHz)。
等离子体工艺可以被执行在包含含氮前体与一种或多种稀释气体的氛围中。可以使用的含氮前体包括N2、NH3与N2H4,并且可以使用的稀释气体包括Ar、He、H2与Xe。在等离子体处理期间,含氮前体可以介于约5sccm与约50slm之间的流速(例如介于约100sccm与约500sccm)被导入腔室。含氮前体可以流入腔室长达一时段,例如介于约1秒与约2小时之间(例如介于约1秒与约60秒之间)。在处理期间,腔室压力可以介于约10mTorr与约760Torr之间,并且腔室中基板支撑件的温度可以介于约20℃与约1000℃之间。能够用于等离子体工艺的腔室的实例为SE与
Figure GSB00000776674600042
GT PECVD腔室。
对于热退火工艺后处理,包含硼-硼键的网络在高于沉积温度的温度下进行退火。例如,网络可以在高于约200℃的温度下退火。在热退火工艺期间,可以在介于约5sccm与约50slm之间的流速(例如介于约10sccm与约1slm之间)将含氮前体导入腔室。含氮前体可以流入腔室长达一时段,例如介于约1秒与约10小时之间(例如介于10秒与约20分钟之间)的时段。在处理期间,腔室压力可以介于约10mTorr与约760Torr之间,并且腔室中基板支撑件的温度可以介于约20℃与约1000℃之间。能够用于热退火工艺的腔室的实例为SE与GT PECVD腔室。
对于UV硬化工艺后处理,能够被使用的示范性的UV硬化工艺条件包括介于约10mTorr与约760Torr之间的腔室压力以及介于约20℃与约1000℃之间的基板支撑件温度。用于UV硬化工艺的基板支撑件温度可以高于、低于或等于形成包含硼-硼键的网络期间的基板支撑件温度。UV辐射可以由任何UV源来提供,例如水银微波弧光灯、脉冲式氙闪光灯、或高效率UV发光二极管阵列。UV辐射可以具有例如介于约170nm与约400nm之间的波长。UV辐射可以具有单一波长,例如175nm。替代地,UV辐射可以由宽带UV源来提供,提供大于200nm的波长。此处理可以包含将包含硼-硼键的网络暴露于介于约1Watt/cm2与约1000Watt/cm2之间的UV辐射,并且所述UV辐射可以提供介于约0.5eV与约10eV之间的光子能量(电子伏特)(例如介于约1eV与约6eV之间)。通常,UV硬化工艺会将包含硼-硼键的网络予以致密化。能够用于执行UV硬化工艺后处理的腔室的实例为NANOCURETM腔室,其可由美国加州圣克拉拉市的应用材料公司(Applied Materials,Inc.)购得。
在UV硬化工艺后处理期间,可以在介于约5sccm与约50sccm之间的流速将含氮前体导入腔室。含氮前体可以流入腔室长达一时段,例如介于约1秒与约2小时之间(例如介于约1秒与约10分钟之间)。
图2是显示UV硬化工艺对于根据本发明实施例所沉积的含硼膜的应力的影响的曲线图。图3是含硼膜在进行UV硬化工艺之前(如所沉积)与之后(后UV硬化)的FTl R分析。表一显示高张应力的含硼膜在进行UV硬化工艺之前与之后的性质的比较。
表一
Figure GSB00000776674600053
Figure GSB00000776674600061
前述所有的后处理从包含硼-硼键的网络去除氢,其进而增加网络的张应力且将网络转变成高应力的含硼膜。前述所有的后处理也造成网络的重新配置,其致使B12二十面体群集的形成且接着B12二十面体群集的融合,进而形成了具有增加的张应力的含硼膜。
前述所有的后处理可以被执行于相同的腔室(其中包含硼-硼键结的网络被沉积此腔室中)或不同的腔室中。若后处理被执行于不同的腔室中,后处理腔室可以是含有沉积腔室的集成式工具的一部分,并且沉积腔室与后处理腔室共享共同的传送腔室。例如,UV硬化后处理可以被执行于NANOCURETM腔室中,所述NANOCURETM腔室为
Figure GSB00000776674600062
平台的一部分,所述
Figure GSB00000776674600063
平台包括沉积网络的沉积腔室。替代地,后处理可以被执行于一不同的腔室中,所述腔室与用以沉积包含硼-硼键的网络的腔室完全分离开。
虽然前述的沉积与后处理步骤被描述成单一沉积步骤和随后的单一后处理步骤,根据本发明其它实施例所提供的含硼膜可以通过多个沉积与后处理循环来形成。在这样的实施例中,包含硼-硼键的网络被沉积到其厚度仅为所欲求最终厚度的部分厚度,并且接着被后处理。沉积与后处理过程可以被执行多次,直到达到欲求的厚度为止。例如,具有约
Figure GSB00000776674600064
至约
Figure GSB00000776674600065
厚度的层(例如约
Figure GSB00000776674600066
至约
Figure GSB00000776674600067
譬如约
Figure GSB00000776674600068
的层)可以被形成在每个循环中。每个循环中的沉积与后处理步骤可以被执行于相同腔室中、共用同一共同传送腔室的不同腔室中或没有共用同一共同传送腔室的不同腔室中。图4显示通过单一沉积与UV后处理(即单一沉浸)或多个循环的沉积与UV后处理(即沉浸净化)而获得的膜厚度的比较。图5显示通过单一沉积与UV后处理(即单一沉浸)或多个循环的沉积与UV后处理(即沉浸净化)而获得的膜应力的比较。
虽然前述实施例中的包含硼-硼键的网络通过热分解工艺来沉积,但在其它实施例中,包含硼-硼键的网络可在等离子体存在的情况下(例如通过等离子体增强化学气相沉积工艺)来沉积。对于腔室中存在等离子体情况下的包含硼-硼键的网络的沉积,含硼前体被导入腔室中。诸如He、H2、N2、Ar或Xe之类的稀释气体也可以被导入腔室中。沉积期间,腔室中基板支撑件的温度可以被设定在介于约100℃与约1000℃之间(例如介于约300℃与约500℃之间),并且腔室中压力可以介于约10mTorr与约760Torr之间(例如介于约2Torr与约10Torr之间)。等离子体是通过RF功率来提供,其中所述RF功率被输送到腔室的喷洒头电极与/或基板支撑件电极。RF功率可以被提供于介于约2W与约5000W之间的功率电平(例如介于约30W与约1000W之间)、介于约100kHz与约1MHz之间的单一低频率(例如约300kHz到约400κHz),或是介于约2W与约5000W之间的功率电平(例如介于约30W与约1000W之间)、大于约1MHz的单一高频率(例如高于约1MHz到约60MHz,譬如13.6MHz)。替代地,RF功率可以被提供于混合频率,所述混合频率包括在约2W与约5000W之间功率电平(例如介于约30W与约1000W之间)的介于约100kHz与约1MHz之间的第一频率(例如约300κHz与约400κHz之间),以及在约2W与约5000W之间功率电平(例如介于约30W与约1000W之间)的大于约1MHz到约60MHz的第二频率(例如13.6MHz)。
包含硼-硼键的网络可以提供所需的含硼膜,而不需要进一步处理此网络。替代地,包含硼-硼键的网络可以被后处理,以改变其组成并形成所需含硼膜。所需含硼膜具有介于约-10Gpa的压应力与约10Gpa的张应力之间的应力。
后处理从以下组中选择:等离子体工艺、紫外线(UV)硬化工艺、热退火工艺与以任何顺序的以上工艺的组合。前述提供的用于通过热分解形成的膜的后处理的等离子体、UV与热退火工艺条件也可以被用于通过等离子体工艺形成的膜的后处理。
能够通过热分解或等离子体工艺而被用来形成包含硼-硼键网络的含硼前体包括乙硼烷(B2H6)、环硼氮烷(B3N3H6)与烷基取代的乙硼烷。可选地,除了含硼前体以外,可以在用以沉积包含硼-硼键的网络的混合物中包括额外的前体,例如含硅前体、含碳前体、和/或含氮前体。
可以使用的含氮前体的实例包括氨(NH3)、联氨(N2H4)。可以使用的含硅前体的实例包括硅烷、三甲硅烷胺(TSA)、三甲基硅烷(TMS)与硅氮烷(silazane),例如六甲基环三硅氮烷(HMCTZ)。可以使用的含碳前体的实例包括具有CxHy通式的碳氢化合物,例如烷类、烯类与炔类。
在一方面中,额外的前体(例如NH3)可以与气体混合物中的含硼前体反应。在另一方面中,额外的前体被捕获在非晶形的网络中,其中所述非晶形网络由含硼前体形成且包含硼-硼键。在后处理期间,被捕获的额外前体可以与网络反应。例如,被捕获在网络中的碳氢化合物的额外前体会与网络反应,以形成硼-碳键结。替代地,被捕获的额外前体作为成孔剂,并且通过后处理而实质上从网络中去除。通过在处理期间去除成孔剂与降低所形成的孔隙度来增加应力。换言之,成孔剂的实质去除在网络中形成了孔隙,并且通过进一步处理,网络会收缩以去除所述孔隙,因而形成了具有提高应力的更加热动力学上有利的降低表面积的膜。
额外前体可以经选择以改变最终含硼膜的化学组成以及其它性质(例如介电性质)。例如,含氮前体可以被用在混合物中以形成氮化硼或经掺杂的氮化硼膜,含硅前体可以被用在混合物中以形成氮化硼硅膜,并且含碳前体可以被用在混合物中以形成碳化硼膜、氮化硼碳膜或氮化硼碳硅膜。
在此提供的没有利用额外前体所沉积的含硼膜是典型的宽带隙半导体,具有大于约4.0eV的能带隙(Eg)。已观察到,向包含硼-硼键的网络中添加氮可以改善网络的介电性质(例如提高介电击穿电压),并且减少经由氮化硼网络形成的漏电流。具有理想介电性质的含硼膜进一步地被叙述在2007年5月23日申请的美国临时专利申请案号60/939,802中,所述临时专利申请在此通过引用被并入本文。在沉积包含硼-硼键的网络期间,或在含氮前体存在情况下的后处理期间(例如UV硬化、等离子体处理或热退火),氮可以被导入含硼膜中。通过使用除了含硼前体以外的含氮前体(例如N2或NH3),或也包括氮的含硼前体(例如环硼氮烷),氮可以被导入含硼膜中。
典型地,当在此提供的含硼膜被沉积在图案化基板上时,在此提供的含硼膜具有大于80%的阶梯覆盖率。含硼膜也具有优良的填隙性质,例如在经填充的间隔中不具有孔隙或细缝形成。
含硼膜应用
在此提供的含硼膜可以被用作硼源层,以用于将一方层掺杂硼。硼源层可以被用来取代离子注入工艺,以将硼导入层中。例如,含硼膜可以被沉积在硅层上且接着被退火,以为了将硼导入硅层而在硅层中形成浅的掺杂硼的结。在希望的硼量被导入下方层之后,含硼膜可以被去除。
在此提供的含硼膜也可以被用作为应变诱导层。例如,含硼膜可以被沉积在栅极结构上方,以在晶体管的沟道区域中诱导应变。诱导应变的含硼膜可以与其下方的衬里层与/或其上方的盖层一起使用。衬里层与盖层的硼含量低于应变诱导的含硼膜的硼含量。相对于较高硼含量的应变诱导的含硼膜,衬里层与盖层的较低的硼含量通过提供更佳的绝缘性质(例如减少的漏电流)而扩展了应变诱导的含硼膜的使用。
衬里层与盖层可以例如是氮化硅、氮化硼或氧化硼层。衬里层可以具有介于约
Figure GSB00000776674600091
与约
Figure GSB00000776674600092
之间的厚度。氮化硼与氧化硼层可以根据任何在此所提供用以形成含硼膜的方法来沉积,区别在于氮化硼与氧化硼层是在足以在氮化硼或氧化层中提供比含硼膜低的硼浓度的条件来沉积。
图6A-6F绘示集成方案,所述集成方案包括高张应力的应变诱导的含硼膜,其中所述含硼膜位于衬里层与盖层之间。图6A显示晶体管结构100,所述晶体管结构100位于基板(未示出)上。晶体管结构100包括栅极叠层102。栅极叠层102包括栅极介电层104与栅极电极层106。硬掩模层108被形成在栅极电极层106上。间隔壁110接触栅极介电层与栅极电极层的侧壁。栅极叠层102在源极区112与漏极区114之间。形成在所述结构中的多个场隔离区116将一种导电类型(例如n型(NMOS))的阱118与另一导电类型(例如p型)的毗邻阱(未示出)隔离。
衬里层120被沉积在结构100上,并且含硼膜122被沉积在衬里层120上。接着,盖层124被沉积在含硼膜上。衬里层120、含硼膜122与盖层124可以分别为在此描述的衬里层、含硼膜与盖层中的任一者。
接着,预金属介电层(PMD)126被沉积在盖层124上,并且通过化学机械抛光(CMP)来处理。预金属介电层126接着被图案化,并且预金属介电层126、盖层124、含硼膜122与衬里曾120被蚀刻以形成到达栅极叠层102的接触通孔128。所得结构显示于图6B。
在形成接触通孔128之后,此结构可以进行两个不同的工艺过程之一。一种过程显示在图6C-6D,以及另一过程显示在图6E-6F。在图6C-6D中所示的过程中,介电衬里层130被沉积在此结构上,如图6C所示。介电衬里层130可以例如是氮化硅层、氮化硼层或氧化硼层。通常,介电衬里层130可以是击穿场大于约3MV/cm的任何其它介电膜。介电衬里层可以具有介于约与约
Figure GSB00000776674600102
之间的厚度。介电衬里层130密封住被接触蚀刻所暴露出的含硼膜122的区域。
介电衬里层130接着从接触通孔底部被蚀刻,并且钨被沉积在此结构上以填充接触通孔128。介电衬里层130可以通过传统的介电质蚀刻工艺或其它蚀刻工艺来蚀刻。然后,钨被化学机械抛光,以去除此结构上过量的钨且将形成在接触通孔中的钨插塞132的上表面予以平坦化。所得结构显示于图6D。
在第6E-6F图显示的顺序中,通过接触蚀刻所暴露出的含硼膜122的区域通过氮化或氧化工艺进行处理,以在暴露区域上建立介电表面134,所述介电表面134密封住所述暴露区域,如图6E所示。可以在去除光阻剂的期间或之后执行氮化或氧化工艺,其中所述光阻剂被用来将预金属介电层126予以图案化以形成接触通孔128。氮化与氧化工艺可以是等离子体工艺、UV硬化工艺、热退火工艺、或其组合。前述用于等离子体、UV硬化与热退火后处理的工艺条件可以被用于氮化与氧化工艺。
氮化工艺包含将含硼膜暴露于含氮前体,以将氮导入膜内。含氮前体可以是例如氮气(N2)、氨(NH3)或联氨(N2H4)。含氮前体能够以稀释气体来稀释,例如氩、氦、氢或氙。
氧化工艺包含将含硼膜暴露于含氧前体,以将氧导入膜内。含氧前体可以是例如氧气(O2)、一氧化二氮(N2O)或二氧化碳(CO2)。
再参照图6E-6F,钨接着被沉积在此结构上以填充接触通孔128。然后,钨被化学机械抛光,以去除此结构上过量的钨且将形成在接触通孔中的钨插塞132的上表面予以平坦化。最终结构显示于图6F。
虽然上文涉及本发明的实施例,在不脱离本发明的基本范围下,可以构想出本发明的其它与进一步实施例,并且本发明范围由所附权利要求书确定。

Claims (18)

1.一种形成含硼膜的方法,包括:
将含硼前体导入腔室内;
在所述腔室中在不存在等离子体的情况下通过热分解工艺从所述含硼前体在基板上沉积包含硼-硼键的网络;
后处理所述包含硼-硼键的网络以从所述网络去除氢,其中所述经后处理的网络形成含硼膜,所述含硼膜具有介于-10Gpa与10Gpa之间的应力。
2.如权利要求1所述的方法,其特征在于,所述后处理包括从以下组中选择的处理:等离子体工艺、UV硬化工艺、热退火工艺、以及上述工艺的组合。
3.如权利要求1所述的方法,其特征在于,还包括使用所述含硼膜以硼来掺杂下方的层。
4.如权利要求1所述的方法,其特征在于,所述包含硼-硼键的网络含有介于3原子%与50原子%之间的氢。
5.如权利要求1所述的方法,其特征在于,还包括将额外前体导入所述腔室内以改变所述含硼膜的组成,其中所述额外前体从以下组中选择:含硅前体、含碳前体、含氮前体、以及上述前体的组合。
6.如权利要求5所述的方法,其特征在于,所述额外前体作为成孔剂,并且通过所述后处理而从所述网络被实质去除,并且通过所述后处理从所述网络去除所述成孔剂增加所述含硼膜中的张应力。
7.如权利要求5所述的方法,其中所述额外前体是含氮前体,所述含氮前体添加氮到所述网络中。
8.如权利要求1所述的方法,其特征在于,所述含硼膜具有大于2Gpa的张应力。
9.一种形成含硼膜的方法,包括:
将含硼前体导入腔室内;
在所述腔室中在存在等离子体的情况下从所述含硼前体在基板上沉积包含硼-硼键的网络,其中所述网络形成含硼膜,所述含硼膜具有介于-10Gpa与10Gpa之间的应力。
10.如权利要求9所述的方法,其特征在于,还包括利用从以下组中选择的处理来后处理所述包含硼-硼键的网络:等离子体工艺、UV硬化工艺、热退火工艺、以及上述工艺的组合。
11.如权利要求9所述的方法,其特征在于,还包括将额外前体导入所述腔室内以改变所述含硼膜的组成,其中所述额外前体从以下组中选择:含硅前体、含碳前体、含氮前体、以及上述前体的组合。
12.如权利要求9所述的方法,其特征在于,所述含硼膜具有大于2Gpa的张应力。
13.一种处理基板的方法,包括:
在基板上的晶体管结构上沉积含硼膜;然后
沉积预金属介电层;
蚀刻所述预金属介电层与所述含硼膜,以形成到达所述晶体管结构的栅极叠层的接触通孔;以及
密封所述含硼膜的通过所述蚀刻所暴露的区域。
14.如权利要求13所述的方法,其特征在于,还包括在沉积所述预金属介电层之前,在所述含硼膜上沉积介电衬里盖层。
15.如权利要求13所述的方法,其特征在于,密封所述含硼膜的区域包括以氮化或氧化工艺来处理所述区域。
16.如权利要求13所述的方法,其特征在于,沉积所述含硼膜包括:
将含硼前体导入腔室内;
在所述腔室中在不存在等离子体的情况下通过热分解工艺从所述含硼前体在基板上沉积包含硼-硼键的网络;
后处理所述包含硼-硼键的网络以从所述网络去除氢,其中所述经后处理的网络形成含硼膜,所述含硼膜具有介于-10Gpa与10Gpa之间的应力。
17.如权利要求13所述的方法,其特征在于,沉积所述含硼膜包括:
将含硼前体导入腔室内;
在所述腔室中在不存在或存在等离子体的情况下通过热分解工艺从所述含硼前体在基板上沉积包含硼-硼键的网络。
18.如权利要求13所述的方法,其特征在于,所述含硼膜具有大于2Gpa的张应力。
CN2008800245001A 2007-07-13 2008-07-03 硼衍生的材料的沉积方法 Expired - Fee Related CN101743631B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US94979607P 2007-07-13 2007-07-13
US60/949,796 2007-07-13
PCT/US2008/069218 WO2009012067A1 (en) 2007-07-13 2008-07-03 Boron derived materials deposition method

Publications (2)

Publication Number Publication Date
CN101743631A CN101743631A (zh) 2010-06-16
CN101743631B true CN101743631B (zh) 2012-12-26

Family

ID=40253517

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008800245001A Expired - Fee Related CN101743631B (zh) 2007-07-13 2008-07-03 硼衍生的材料的沉积方法

Country Status (5)

Country Link
US (1) US7704816B2 (zh)
KR (1) KR20100042644A (zh)
CN (1) CN101743631B (zh)
TW (1) TWI363385B (zh)
WO (1) WO2009012067A1 (zh)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7253125B1 (en) 2004-04-16 2007-08-07 Novellus Systems, Inc. Method to improve mechanical strength of low-k dielectric film using modulated UV exposure
US9659769B1 (en) 2004-10-22 2017-05-23 Novellus Systems, Inc. Tensile dielectric films using UV curing
US7790633B1 (en) 2004-10-26 2010-09-07 Novellus Systems, Inc. Sequential deposition/anneal film densification method
US7510982B1 (en) 2005-01-31 2009-03-31 Novellus Systems, Inc. Creation of porosity in low-k films by photo-disassociation of imbedded nanoparticles
US8282768B1 (en) 2005-04-26 2012-10-09 Novellus Systems, Inc. Purging of porogen from UV cure chamber
US8454750B1 (en) 2005-04-26 2013-06-04 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8980769B1 (en) 2005-04-26 2015-03-17 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8889233B1 (en) 2005-04-26 2014-11-18 Novellus Systems, Inc. Method for reducing stress in porous dielectric films
US8137465B1 (en) 2005-04-26 2012-03-20 Novellus Systems, Inc. Single-chamber sequential curing of semiconductor wafers
US8465991B2 (en) 2006-10-30 2013-06-18 Novellus Systems, Inc. Carbon containing low-k dielectric constant recovery using UV treatment
US7851232B2 (en) * 2006-10-30 2010-12-14 Novellus Systems, Inc. UV treatment for carbon-containing low-k dielectric repair in semiconductor processing
US10037905B2 (en) 2009-11-12 2018-07-31 Novellus Systems, Inc. UV and reducing treatment for K recovery and surface clean in semiconductor processing
US7906174B1 (en) 2006-12-07 2011-03-15 Novellus Systems, Inc. PECVD methods for producing ultra low-k dielectric films using UV treatment
JP5310543B2 (ja) * 2007-03-27 2013-10-09 富士通セミコンダクター株式会社 半導体装置の製造方法
US8242028B1 (en) 2007-04-03 2012-08-14 Novellus Systems, Inc. UV treatment of etch stop and hard mask films for selectivity and hermeticity enhancement
US8084105B2 (en) * 2007-05-23 2011-12-27 Applied Materials, Inc. Method of depositing boron nitride and boron nitride-derived materials
US8337950B2 (en) * 2007-06-19 2012-12-25 Applied Materials, Inc. Method for depositing boron-rich films for lithographic mask applications
US8211510B1 (en) 2007-08-31 2012-07-03 Novellus Systems, Inc. Cascaded cure approach to fabricate highly tensile silicon nitride films
US9456925B2 (en) * 2007-09-06 2016-10-04 Alcon Lensx, Inc. Photodisruptive laser treatment of the crystalline lens
US8148269B2 (en) * 2008-04-04 2012-04-03 Applied Materials, Inc. Boron nitride and boron-nitride derived materials deposition method
US8133793B2 (en) 2008-05-16 2012-03-13 Sandisk 3D Llc Carbon nano-film reversible resistance-switchable elements and methods of forming the same
US7906817B1 (en) 2008-06-06 2011-03-15 Novellus Systems, Inc. High compressive stress carbon liners for MOS devices
US7998881B1 (en) * 2008-06-06 2011-08-16 Novellus Systems, Inc. Method for making high stress boron-doped carbon films
US8569730B2 (en) * 2008-07-08 2013-10-29 Sandisk 3D Llc Carbon-based interface layer for a memory device and methods of forming the same
US8466044B2 (en) * 2008-08-07 2013-06-18 Sandisk 3D Llc Memory cell that includes a carbon-based memory element and methods forming the same
US9050623B1 (en) 2008-09-12 2015-06-09 Novellus Systems, Inc. Progressive UV cure
US8421050B2 (en) * 2008-10-30 2013-04-16 Sandisk 3D Llc Electronic devices including carbon nano-tube films having carbon-based liners, and methods of forming the same
US8835892B2 (en) * 2008-10-30 2014-09-16 Sandisk 3D Llc Electronic devices including carbon nano-tube films having boron nitride-based liners, and methods of forming the same
US20100108976A1 (en) * 2008-10-30 2010-05-06 Sandisk 3D Llc Electronic devices including carbon-based films, and methods of forming such devices
KR101077157B1 (ko) 2009-04-03 2011-10-27 주식회사 하이닉스반도체 상변화 기억 소자의 제조방법 및 이를 이용한 반도체 소자의 제조방법
US8288292B2 (en) 2010-03-30 2012-10-16 Novellus Systems, Inc. Depositing conformal boron nitride film by CVD without plasma
CN103383922A (zh) * 2012-05-03 2013-11-06 中芯国际集成电路制造(上海)有限公司 一种低k介质阻挡层及其形成方法
US9234276B2 (en) 2013-05-31 2016-01-12 Novellus Systems, Inc. Method to obtain SiC class of films of desired composition and film properties
US10832904B2 (en) 2012-06-12 2020-11-10 Lam Research Corporation Remote plasma based deposition of oxygen doped silicon carbide films
US10325773B2 (en) 2012-06-12 2019-06-18 Novellus Systems, Inc. Conformal deposition of silicon carbide films
US20160314964A1 (en) 2015-04-21 2016-10-27 Lam Research Corporation Gap fill using carbon-based films
US10418243B2 (en) 2015-10-09 2019-09-17 Applied Materials, Inc. Ultra-high modulus and etch selectivity boron-carbon hardmask films
WO2017099701A1 (en) * 2015-12-07 2017-06-15 Intel Corporation Gapfill of etch resistant boron carbide
US9847221B1 (en) 2016-09-29 2017-12-19 Lam Research Corporation Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing
US10002787B2 (en) 2016-11-23 2018-06-19 Lam Research Corporation Staircase encapsulation in 3D NAND fabrication
KR102551237B1 (ko) * 2016-12-22 2023-07-03 어플라이드 머티어리얼스, 인코포레이티드 기저 구조 재료에 대한 직접적인 rf 노출 없이 등각성의 밀폐 유전체 캡슐화를 위한 sibn 필름
US11342457B2 (en) * 2017-09-18 2022-05-24 Intel Corporation Strained thin film transistors
JP7005367B2 (ja) * 2018-02-05 2022-02-04 東京エレクトロン株式会社 ボロン系膜の成膜方法および成膜装置
US10840087B2 (en) * 2018-07-20 2020-11-17 Lam Research Corporation Remote plasma based deposition of boron nitride, boron carbide, and boron carbonitride films
KR20230085953A (ko) 2018-10-19 2023-06-14 램 리써치 코포레이션 갭 충진 (gapfill) 을 위한 도핑되거나 도핑되지 않은 실리콘 카바이드 증착 및 원격 수소 플라즈마 노출
US11018139B2 (en) * 2019-08-13 2021-05-25 Micron Technology, Inc. Integrated transistors and methods of forming integrated transistors
US11276573B2 (en) * 2019-12-04 2022-03-15 Applied Materials, Inc. Methods of forming high boron-content hard mask materials
US11935751B2 (en) * 2021-05-25 2024-03-19 Applied Materials, Inc. Boron nitride for mask patterning

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5558908A (en) * 1994-11-07 1996-09-24 Lanxide Technology Company, Lp Protective compositions and methods of making same
US5837607A (en) * 1996-12-05 1998-11-17 Quick; Nathaniel R. Method of making a laser synthesized ceramic electronic devices and circuits
US5994762A (en) * 1996-07-26 1999-11-30 Hitachi, Ltd. Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof
US6165891A (en) * 1999-11-22 2000-12-26 Chartered Semiconductor Manufacturing Ltd. Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
US6228731B1 (en) * 1999-08-16 2001-05-08 Taiwan Semiconductor Manufacturing Company Re-etched spacer process for a self-aligned structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100268895B1 (ko) * 1997-12-27 2000-10-16 김영환 박막트랜지스터 및 이의 제조방법
US20030040171A1 (en) * 2001-08-22 2003-02-27 Weimer Ronald A. Method of composite gate formation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5558908A (en) * 1994-11-07 1996-09-24 Lanxide Technology Company, Lp Protective compositions and methods of making same
US5994762A (en) * 1996-07-26 1999-11-30 Hitachi, Ltd. Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof
US5837607A (en) * 1996-12-05 1998-11-17 Quick; Nathaniel R. Method of making a laser synthesized ceramic electronic devices and circuits
US6228731B1 (en) * 1999-08-16 2001-05-08 Taiwan Semiconductor Manufacturing Company Re-etched spacer process for a self-aligned structure
US6165891A (en) * 1999-11-22 2000-12-26 Chartered Semiconductor Manufacturing Ltd. Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer

Also Published As

Publication number Publication date
WO2009012067A1 (en) 2009-01-22
KR20100042644A (ko) 2010-04-26
US7704816B2 (en) 2010-04-27
US20090017640A1 (en) 2009-01-15
TWI363385B (en) 2012-05-01
CN101743631A (zh) 2010-06-16
TW200915427A (en) 2009-04-01

Similar Documents

Publication Publication Date Title
CN101743631B (zh) 硼衍生的材料的沉积方法
US11289326B2 (en) Method for reforming amorphous carbon polymer film
KR101327923B1 (ko) 보론 니트라이드 및 보론 니트라이드-유도된 물질 증착 방법
US20200365392A1 (en) Deposition of SiN
TWI788311B (zh) 拓撲受限電漿增強循環沉積方法
TW202111148A (zh) 包括介電層之結構、其形成方法及執行形成方法的反應器系統
TWI479044B (zh) 硼膜界面工程
KR101161098B1 (ko) 낮은 에칭 레이트 유전체 라이너들을 이용한 갭충진 향상
TWI541898B (zh) 用於半導體整合之非敏性乾式移除製程
CN113249706A (zh) 用于沉积间隙填充流体的方法及相关系统和设备
JP6845252B2 (ja) ケイ素含有膜の堆積のための組成物及びそれを用いた方法
US20140273530A1 (en) Post-Deposition Treatment Methods For Silicon Nitride
TW201742947A (zh) 用於沉積含矽膜的組合物及其方法
US20140273524A1 (en) Plasma Doping Of Silicon-Containing Films
TW201510268A (zh) 具有所欲成分及膜特性之矽碳化物類薄膜的取得方法
KR20110008209A (ko) 붕소 질화물 및 붕소-질화물 유도 물질들 증착 방법
US9685325B2 (en) Carbon and/or nitrogen incorporation in silicon based films using silicon precursors with organic co-reactants by PE-ALD
WO2006136584A1 (en) Method of forming a high dielectric constant film and method of forming a semiconductor device
CN110776639B (zh) 用于形成热稳定有机硅聚合物膜的方法
US20220076996A1 (en) Methods for depositing gap filing fluids and related systems and devices
JP2007204851A (ja) 半導体装置の製造法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C53 Correction of patent of invention or patent application
CB02 Change of applicant information

Address after: American California

Applicant after: Applied Materials Inc.

Address before: American California

Applicant before: Applied Materials Inc.

C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20121226

Termination date: 20140703

EXPY Termination of patent right or utility model