CN101740614A - Laterally diffused metal oxide semiconductor (LDMOS) structure for protecting channel district by utilizing polysilicon field polar plate - Google Patents
Laterally diffused metal oxide semiconductor (LDMOS) structure for protecting channel district by utilizing polysilicon field polar plate Download PDFInfo
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- CN101740614A CN101740614A CN200810043933A CN200810043933A CN101740614A CN 101740614 A CN101740614 A CN 101740614A CN 200810043933 A CN200810043933 A CN 200810043933A CN 200810043933 A CN200810043933 A CN 200810043933A CN 101740614 A CN101740614 A CN 101740614A
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Abstract
The invention discloses an laterally diffused metal oxide semiconductor (LDMOS) structure for protecting a channel district by utilizing a polysilicon field polar plate, comprising a deep trap, a source electrode, a drain electrode, a grid electrode and the channel district, wherein the source electrode, the drain electrode, the grid electrode and the channel district are in the deep trap; the source electrode and the channel district are positioned at one side of the grid electrode; the drain electrode is positioned at the other side of the grid electrode; the doping types of the source electrode, the deep trap and the drain electrode are the same; the doping types of the source electrode, the deep trap and the channel district are opposite; and the polysilicon field polar plate is arranged above the edge of the channel district and the deep trap, or the polysilicon field polar plate is arranged above the edge of a PN junction of the channel district and the drain electrode. The LDMOS structure can reduce surface electric field between an LDMOS underway and the drain electrode so as to enhance the breakdown voltage of the LDMOS.
Description
Technical field
The present invention relates to a kind of semiconductor device, be specifically related to a kind of high voltage integrated circuit and make device, relate in particular to a kind of LDMOS (Laterally Diffused Metal Oxide Semiconductor) structure of utilizing polysilicon field plate protection channel region.
Background technology
LDMOS (Laterally Diffused Metal Oxide Semiconductor) is a kind of semiconductor device of high-power, is widely used in power integrated circuit.LDMOS structure at present commonly used as depicted in figs. 1 and 2, LDMOS comprises deep trap, source electrode, drain electrode, grid, channel region, all in deep trap, source electrode and channel region are positioned at a side of grid for source electrode, drain electrode, grid and channel region, drain electrode is positioned at the opposite side of grid.The doping type of source electrode, deep trap and drain electrode is identical, and the doping type of source electrode, deep trap and channel region is opposite.During operate as normal, source electrode and channel region connect lower current potential (absolute value), and drain electrode connects higher current potential (absolute value).Because the local surface field away from grid is more concentrated at the channel region edge, channel region is lower in this regional puncture voltage with drain electrode, and this is the maximum operating voltage of limiting device usually.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of LDMOS structure of utilizing polysilicon field plate protection channel region, can reduce the surface field between LDMOS substrate and the drain electrode, to improve the puncture voltage of LDMOS.
For solving the problems of the technologies described above; the invention provides a kind of LDMOS structure of utilizing polysilicon field plate protection channel region; comprise: deep trap, source electrode, drain electrode, grid and channel region; wherein; source electrode, drain electrode, grid and channel region are all in deep trap; source electrode and channel region are positioned at a side of grid, and drain electrode is positioned at the opposite side of grid.The doping type of source electrode, deep trap and drain electrode is identical, and the doping type of source electrode, deep trap and channel region is opposite.Above channel region and deep trap edge, be provided with the polysilicon field plate, or above the PN junction edge of channel region and drain electrode, be provided with the polysilicon field plate.
Described polysilicon field plate covers the PN junction of channel region and deep trap or drain electrode in the form of a ring.
Compare with prior art, the present invention has following beneficial effect: the present invention is owing to increased the polysilicon field plate above the PN junction edge of channel region and deep trap or drain electrode, make the deep trap of polysilicon below or the surface depletion of drain electrode, make that the surface field of channel region and drain electrode is weakened, thereby improved the distribution of surface field, to improve the puncture voltage of LDMOS.So the ceiling voltage of device is improved.
Description of drawings
Fig. 1 is the floor map of existing LDMOS structure;
Fig. 2 is the schematic cross-section of existing LDMOS structure;
Fig. 3 is the floor map that the present invention utilizes the LDMOS structure of polysilicon field plate protection channel region;
Fig. 4 is the schematic cross-section that the present invention utilizes the LDMOS structure of polysilicon field plate protection channel region.
Embodiment
The present invention is further detailed explanation below in conjunction with drawings and Examples.
As shown in Figure 3 and Figure 4, in the present invention, the LDMOS structure, comprise: deep trap, source electrode, drain electrode, grid and channel region, wherein, source electrode, drain electrode, grid and channel region are all in deep trap, source electrode and channel region are positioned at a side of grid, and drain electrode is positioned at the opposite side of grid.The doping type of source electrode, deep trap and drain electrode is identical, and the doping type of source electrode, deep trap and channel region is opposite.Above channel region and deep trap edge, be provided with the polysilicon field plate, or the drain surface below increase polysilicon field plate above the PN junction edge of channel region and drain electrode makes polysilicon exhausts, thereby improved the distribution of surface field, improved the puncture voltage of channel region and drain electrode.
On layout design, the polysilicon field plate done and cover channel region and deep trap circlewise, or cover the PN junction of channel region and drain electrode.Then, pass through the LDMOS manufacture craft flow process of following routine again, just can obtain the LDMOS:1. deep trap injection of polysilicon field plate protection being arranged and pushing away trap at channel region; 2. drain electrode is injected and is pushed away trap; 3. active area is made; 4. the low pressure trap injects; 5. channel region injects; 6. growth of gate oxide layer; 7. polysilicon gate is made; 8.N-low-doped leakage is injected; 9.P-low-doped leakage is injected; 9. side wall is made; 10.P+ inject; 11.N+ inject; 12. opening contact hole; 13. making metal interconnecting wires.
Claims (2)
1. LDMOS structure of utilizing polysilicon field plate protection channel region; comprise deep trap, source electrode, drain electrode, grid and channel region; wherein; source electrode, drain electrode, grid and channel region are all in deep trap; source electrode and channel region are positioned at a side of grid; drain electrode is positioned at the opposite side of grid; the doping type of source electrode, deep trap and drain electrode is identical; the doping type of source electrode, deep trap and channel region is opposite; it is characterized in that; above channel region and deep trap edge, be provided with the polysilicon field plate, or above the PN junction edge of channel region and drain electrode, be provided with the polysilicon field plate.
2. the LDMOS structure of utilizing polysilicon field plate protection channel region as claimed in claim 1, it is characterized in that: described polysilicon field plate covers the PN junction of channel region and deep trap or drain electrode in the form of a ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810043933A CN101740614A (en) | 2008-11-13 | 2008-11-13 | Laterally diffused metal oxide semiconductor (LDMOS) structure for protecting channel district by utilizing polysilicon field polar plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810043933A CN101740614A (en) | 2008-11-13 | 2008-11-13 | Laterally diffused metal oxide semiconductor (LDMOS) structure for protecting channel district by utilizing polysilicon field polar plate |
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| Publication Number | Publication Date |
|---|---|
| CN101740614A true CN101740614A (en) | 2010-06-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200810043933A Pending CN101740614A (en) | 2008-11-13 | 2008-11-13 | Laterally diffused metal oxide semiconductor (LDMOS) structure for protecting channel district by utilizing polysilicon field polar plate |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015169196A1 (en) * | 2014-05-04 | 2015-11-12 | 无锡华润上华半导体有限公司 | Laterally diffused metal oxide semiconductor device and manufacturing method therefor |
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2008
- 2008-11-13 CN CN200810043933A patent/CN101740614A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015169196A1 (en) * | 2014-05-04 | 2015-11-12 | 无锡华润上华半导体有限公司 | Laterally diffused metal oxide semiconductor device and manufacturing method therefor |
| US9837532B2 (en) | 2014-05-04 | 2017-12-05 | Csmc Technologies Fab1 Co., Ltd. | Laterally diffused metal oxide semiconductor device and manufacturing method therefor |
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Application publication date: 20100616 |