CN101740432B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN101740432B CN101740432B CN2008102035438A CN200810203543A CN101740432B CN 101740432 B CN101740432 B CN 101740432B CN 2008102035438 A CN2008102035438 A CN 2008102035438A CN 200810203543 A CN200810203543 A CN 200810203543A CN 101740432 B CN101740432 B CN 101740432B
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Abstract
The invention relates to a method for manufacturing a semiconductor device, comprising the following steps of: measuring wafer deflection after the heat treatment process is carried out; and based on the relation between the wafer deflection and projection departure, if the projection departure which corresponds to the wafer deflection exceeds the process specification, correcting the wafer deflection so as to reduce the projection departure. The method for manufacturing the semiconductor device lowers the deviation generated on the subsequent process production due to the wafer deflection, thereby improving the quality of the semiconductor device.
Description
Technical field
The present invention relates to the manufacturing approach of semiconductor device.
Background technology
At present, various Technologies for Heating Processing are widely used in the production process of semiconductor device.Some Technology for Heating Processing is the various material layers that the chemical reaction during through high temperature forms semiconductor device.With the thermal oxidation technology is example, promptly is to utilize the oxidation reaction under the high temperature to obtain oxide layer.At for example application number is in the manufacturing approach of the semiconductor memory component that provides of 02108135.2 one Chinese patent application; Before forming grid conducting layer, the step that on the semiconductor-based end, forms gate oxide and field oxide earlier through the method for thermal oxidation is just arranged at semiconductor-based the end.
And common thermal oxidation technology normally places boiler tube to carry out wafer; At for example application number is that 01143461.9 one Chinese patent application just provides a kind of thermal-oxidative production process: at first be lower than under the temperature of main thermal-oxidative production process temperature; Wafer is loaded in the boiler tube; And, feed the nitrogen or the argon gas of the big flow be enough to expel aqueous vapor in the boiler tube and oxygen.Then after wafer loaded boiler tube fully, the operating temperature of the boiler tube that raises gradually was to main thermal-oxidative production process temperature, and lasting nitrogen or the argon gas of feeding.Then, under main thermal-oxidative production process temperature, aerating oxygen in boiler tube, and carry out thermal-oxidative production process., gradually reduce the operating temperature of boiler tube, and take out wafer by boiler tube thereafter.
And other Technologies for Heating Processing, rapid thermal anneal process for example then is to have utilized the variation of lattice under the high temperature to improve the quality of formed material layer.At for example application number is in 01806216.4 the one Chinese patent application, has just utilized rapid thermal annealing to repair crystal damage, so that device has good mobility and low leakage current.
Along with the development of semiconductor technology, in order to practice thrift the technology manufacturing cost, the size of wafer is also increasing.Yet, find that in semiconductor technology after wafer was carried out above-mentioned Technology for Heating Processing, wafer regular meeting influenced the accuracy of subsequent technique because of distortion, and finally influenced the quality of semiconductor devices of manufacturing.
Summary of the invention
The problem that the present invention will solve is owing to wafer distortion influences the semiconductor device quality in the present technology.
For addressing the above problem, the present invention provides a kind of manufacturing approach of semiconductor device, comprising:
Wafer distortion amount after the measurement Technology for Heating Processing;
Based on the relation of wafer distortion amount and distortion's amount, if the corresponding distortion's amount of said wafer distortion amount exceeds process specification, then revise said wafer distortion amount, to reduce distortion's amount.
Compared with prior art; The manufacturing approach of above-mentioned disclosed semiconductor device has the following advantages: through the wafer distortion amount after the measurement Technology for Heating Processing; The distortion amount corresponding when the wafer distortion amount exceeds process specification; Revise the wafer amount to reduce distortion's amount, reduce because wafer distortion and deviation that subsequent technique is produced, thereby improved quality of semiconductor devices.
Description of drawings
Fig. 1 is a kind of execution mode figure of the manufacturing approach of semiconductor device of the present invention;
Fig. 2 is an enforcement illustration of measuring the wafer distortion amount in the method shown in Figure 1;
Fig. 3 is the enforcement illustration that obtains diameter wafer and wafer distortion magnitude relation in the method shown in Figure 2;
Fig. 4 is the enforcement illustration that obtains wafer distortion amount and distortion's magnitude relation in the method shown in Figure 1;
Fig. 5 is wafer distortion amount and distortion's magnitude relation curve chart.
Embodiment
With reference to shown in Figure 1, a kind of execution mode of the manufacturing approach of semiconductor device of the present invention comprises the following steps:
Step s1, the wafer distortion amount (wafer bow) after the measurement Technology for Heating Processing;
Step s2 based on the relation of wafer distortion amount and distortion's amount, if the corresponding distortion's amount (overlay) of said wafer distortion amount exceeds process specification (spec), then revises said wafer distortion, to reduce distortion's amount.
Wherein said distortion amount comprises on the photomask deviation of respective aligned mark on the alignment mark and wafer.
When making public; Figure on photomask can project on the wafer; Corresponding one or more groups alignment mark of this figure also can project on the wafer, and photomask was with respect to the position of wafer when the effect of said alignment mark was that assist location is made public next time.Instantly during single exposure; Also have the alignment mark of the photomask pattern position of last time making public on the corresponding photomask in order to mark; Through with corresponding alignment mark on this alignment mark and the wafer; Just can accurately locate the position of the photomask of this exposure, thereby make the photomask pattern of this exposure accurately project to the corresponding position of photomask pattern of exposure last time with respect to wafer.Through after the multiexposure, multiple exposure step, finally each time is projected in wafer figure that the exposure figure on the wafer is combined into and the circuitous pattern of technological design adapts.
When heat-treating technology, the wafer that is under the higher temperature can raise and the generation dilatancy along with temperature.Because the size of wafer current is all bigger; For example the wafer size of main flow has all reached 12 inches; In Technology for Heating Processing; Each zone of wafer may dilatancy in various degree occur because of the difference on being heated, and for example, the core degrees of expansion of wafer makes wafer form bowl-type greater than the degrees of expansion of crystal round fringes part.The distortion of wafer then will cause the position in some specific function zones of crystal column surface that deviation takes place, and influence subsequent technique then.
For example wafer is heated and deforms; Alignment mark on the distortion wafer will produce deviation with respect to the position that is not out of shape corresponding alignment mark on the wafer; Then in the alignment procedures of photomask before exposure and wafer, one or more groups above-mentioned alignment mark can not be aimed at fully, so just possibly cause photomask deviation to occur with aiming at of wafer; Be about to produce distortion, thereby influence the accuracy of photoetching.
Based on this, can think that when wafer makes wafer distortion with the temperature rising wafer distortion amount and said distortion amount should exist necessarily gets in touch.
Influence the accuracy of photoetching process for fear of distortion, after Technology for Heating Processing, measure the deflection of wafer owing to wafer.Based on the relation of wafer distortion amount and distortion amount, if the corresponding distortion's amount of wafer distortion amount exceeds process specification, then revise said wafer distortion amount and reduce distortion's amount, thereby reduce because wafer distortion and influence that technology is produced.
In the above-mentioned execution mode,, thereby can revise said wafer distortion amount through the temperature of adjusting process because the wafer distortion amount is to responsive to temperature.
In one embodiment, with reference to shown in Figure 2, the wafer distortion amount after the measurement Technology for Heating Processing can comprise the following steps:
Step s11, the diameter of measurement wafer;
Step s12 based on the relation of diameter wafer and wafer distortion amount, obtains the corresponding wafer distortion amount of measured diameter.
Wherein, the quantity of said measurement diameter wafer can be decided according to the requirement of technology cost and process time.Because the expansion intensity of variation of wafer each several part when being heated maybe be all inequality, will make that through measuring the mean value that many group diameters obtain the wafer distortion amount data are more accurate.Thereby, satisfying under the prerequisite that technology cost and process time require, the quantity of measuring diameter is many more, and the data of the wafer distortion amount of acquisition are also accurate more, and are also more accurate in the adjustment that subsequent technique carries out to the wafer distortion amount.
In the foregoing description, with reference to shown in Figure 3, the relation of said diameter wafer and wafer distortion amount can obtain through the following step:
Step s121 chooses the wafer test piece and carries out said Technology for Heating Processing;
Step s122, after the measurement Technology for Heating Processing, many groups diameter of wafer test piece and corresponding wafer distortion amount;
Step s123 according to measured many groups diameter and corresponding wafer distortion amount, obtains the relation of diameter wafer and wafer distortion amount.
Wherein, it is identical that the structure of said wafer test piece and actual is heat-treated the crystal circle structure of technology.To organize diameter and corresponding wafer distortion amount be in order to obtain the relation of diameter and wafer distortion amount comparatively accurately more and measure the wafer test piece.
In one embodiment, with reference to shown in Figure 4, the relation of said wafer distortion amount and distortion's amount can obtain through following step:
Step s21 chooses the wafer test piece and carries out said Technology for Heating Processing;
Step s22, after the measurement Technology for Heating Processing, many groups deflection of wafer test piece and corresponding departure data;
Step s23 with measured wafer distortion amount and distortion's amount fitting function, obtains the relation of wafer distortion amount and distortion amount.
Wherein, it is identical that the structure of said wafer test piece and actual is heat-treated the crystal circle structure of technology, also has the functional area that some can supply to measure distortion's amount on it.Through after Technology for Heating Processing, measuring the deviation of each functional area position, and corresponding wafer distortion amount, and can cover the function of both data, thereby obtain the relation that wafer distortion amount and distortion measure with this data fitting with respect to normal place.
In one embodiment, said correction wafer distortion comprises: according to the wafer distortion amount wafer each several part is imposed corresponding temperature, make the wafer each several part be heated inhomogeneous and produce different temperature distortions.
Instance with a fabrication of semiconductor device describes below, so that above-mentioned method, semi-conductor device manufacturing method is clearer.
For example, in a production process of semiconductor device, on the silicon substrate of wafer, accomplish deep trap technology (well formation) afterwards, carry out three layers of grid oxic horizon (triple gate) technology, this technical process is summarized as follows:
At first carry out the cleaning after the deep trap technology, then in high temperature reaction stove or thermal annealing reaction chamber, carry out the oxidation of silicon substrate, this moment, surface of silicon can form layer of oxide layer.Subsequently at oxide layer surface coated photoresistance, the oxide layer that needs are kept covers, and after removing through the wet etching of high selectivity and photoresistance, the oxide layer that is not covered by photoresistance is removed and exposes silicon substrate.In high temperature reaction stove or thermal annealing reaction chamber, carry out oxidation once more, control reaction condition (different with oxidation for the first time, as specifically to decide), generate the grid oxic horizon of another thickness by technological requirement.Next; After repeating steps such as above-mentioned coating photoresistance, etching, removing photoresistance; In high temperature reaction stove or thermal annealing reaction chamber, carry out oxidation (reaction condition of this oxidation is also different with its twice) once more, thereby finally obtain grid oxic horizon at three different-thickness in the different zone of silicon substrate.
After three layers of gate oxidation layer process are accomplished, because wafer possibly be heated and deforms in the oxidizing process, measure the diameter of wafer this moment, to obtain the deflection of wafer behind three layers of gate oxidation layer process.After the deflection that has obtained wafer, can obtain corresponding distortion's amount according to the relation of wafer distortion amount and distortion's amount; Gained distortion amount and process specification are compared; See and whether exceed process specification; If do not exceed process specification, then need not distortion correction to wafer, can directly continue next processing step.And, explain that then the distortion of wafer possibly influence subsequent technique if exceed process specification, be necessary wafer distortion is revised.For example; With reference to shown in Figure 5, be negative with wafer to the deflection of lower recess, suppose that the measured wafer distortion amount that obtains is-1 μ m; Its corresponding distortion amount is 3nm; Then according to process specification among Fig. 5, distortion's amount has exceeded the maximum deviation of the 2.5nm of process specification regulation, thereby is necessary wafer distortion is revised.
Correction for wafer distortion can be adopted following dual mode: 1) before subsequent technique; Increase the step of revising wafer distortion: wafer is placed the adjustable environment of temperature; Through to put on temperature on the wafer control realize wafer distortion correction 2) for the step of not extra increase correction wafer distortion; So that influence the efficient of technology, also can be in follow-up technology with heating steps through controlling and realize to putting on temperature on the wafer.
For example, behind three layers of gate oxidation layer process, be double-deck grid oxide layer technology, its technical process and above-mentioned three layers of gate oxidation layer process are similar, and difference only is only to carry out the grid oxic horizon that twice oxidation technology obtains two different-thickness.Aforesaid; Oxidizing process is carried out in high temperature reaction stove or thermal annealing reaction chamber; Thereby just can be under the prerequisite that satisfies the oxidizing temperature requirement in the process of oxidation; Each zone for the wafer that carries out oxidation reaction applies different temperature, and it is inhomogeneous to make that the each several part that reacts wafer is heated, and makes each several part produce different temperature distortions.
For example, find in the measurement behind three layers of gate oxidation layer process that wafer produces the distortion of depression, and the corresponding distortion's amount of its deflection has exceeded process specification; Then in double-deck grid oxide layer technology,, crystal round fringes is applied higher temperature through temperature control; Make crystal round fringes produce bigger dilatancy; Correspondingly, wafer center is applied lower temperature, make wafer center produce less dilatancy; Thereby make the whole smooth deformation tendency of trend that produces of wafer, reach the purpose of revising wafer distortion.
After double-deck grid oxide layer technology is accomplished, measure the diameter of wafer this moment once more, with the deflection of wafer after the acquisition double-deck grid oxide layer technology.And same distortion's amount through the acquisition correspondence, compare with process specification, judge whether to be necessary wafer distortion is revised.
If be necessary wafer distortion is revised, then with reference to before explanation, both can increase the step of revising wafer distortion newly, also can in follow-up technology with heating steps, revise wafer distortion.
For example, after the said double-deck grid oxide layer technology, be the 3rd layer of gate oxidation layer process.Said the 3rd layer of grid oxic horizon technical process can be with reference to aforementioned three layers of grid oxic horizon and double-deck grid oxide layer technology, and difference is only to carry out the once oxidation process.As the wafer modification method of mentioning in the double-deck grid oxide layer technology; In this oxidizing process; Equally can be under the prerequisite that satisfies the technological temperature requirement; Through the wafer each several part is applied different temperature, it is inhomogeneous to make that the wafer each several part is heated, and reaches the purpose of revising wafer distortion.
Behind the 3rd layer of gate oxidation layer process, measure the diameter of wafer this moment once more, to obtain the deflection of wafer behind the 3rd layer of gate oxidation layer process, obtain corresponding distortion's amount.If according to the comparison of distortion's amount with process specification, discovery need be revised wafer distortion.Then both can increase the step of revising wafer distortion newly, also can in follow-up technology with heating steps, revise wafer distortion.
Certainly, also might there be following situation: for example need carry out the photoetching process of grid in the subsequent technique, thereby if the not newly-increased step of revising wafer distortion possibly will exert an influence to the photoetching of this wafer.Above-mentioned measurement this moment and obtain more being of effect of distortion amount can just be revised wafer distortion when next wafer begins three layers of above-mentioned gate oxidation layer process, with the correction efficient of increase to next wafer temperature distortion accordingly.
In the above-mentioned instance, after each step relates to process of thermal treatment, all carried out relevant detection step for whether carrying out the wafer distortion correction, thereby can obtain between maximum wafer distortion modified spatial.Certainly; Can be according to the restriction of process time and cost; Freely select when to judge whether to carry out the wafer distortion correction; For example can only after three layers of gate oxidation layer process or double-deck grid oxide layer technology, carry out said judgement, assess so that whether the wafer distortion in this technology need be revised.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (6)
1. the manufacturing approach of a semiconductor device is characterized in that, comprising:
Wafer distortion amount after the measurement Technology for Heating Processing;
Based on the relation of wafer distortion amount and distortion's amount, if the corresponding distortion's amount of said wafer distortion amount exceeds process specification, then revise said wafer distortion, to reduce distortion's amount;
Said measurement wafer distortion amount comprises: the diameter of measuring wafer; Based on the relation of diameter wafer and wafer distortion amount, obtain the corresponding wafer distortion amount of measured diameter;
The relation of said diameter wafer and wafer distortion amount obtains through the following step: choose the wafer test piece and carry out said Technology for Heating Processing; After measuring Technology for Heating Processing, many groups diameter of wafer test piece and corresponding wafer distortion amount; According to measured many groups diameter and corresponding wafer distortion amount, obtain the relation of diameter wafer and wafer distortion amount;
The relation of said wafer distortion amount and distortion's amount obtains through following step: choose the wafer test piece and carry out said Technology for Heating Processing; After measuring Technology for Heating Processing, many groups deflection of wafer test piece and corresponding departure data; With measured wafer distortion amount and distortion's amount fitting function, obtain the relation of wafer distortion amount and distortion amount.
2. the manufacturing approach of semiconductor device as claimed in claim 1; It is characterized in that; Said correction wafer distortion comprises: according to the wafer distortion amount wafer each several part is applied corresponding temperature, make the wafer each several part be heated inhomogeneous and produce different temperature distortions.
3. the manufacturing approach of a semiconductor device is characterized in that, comprising:
Three layers of gate oxidation layer process;
Behind three layers of gate oxidation layer process, measure the wafer distortion amount;
Based on the relation of wafer distortion amount and distortion's amount, if the corresponding distortion's amount of said wafer distortion amount exceeds process specification, then revise said wafer distortion, to reduce distortion's amount;
Double-deck grid oxide layer technology;
The 3rd layer of gate oxidation layer process;
Said measurement wafer distortion amount comprises: the diameter of measuring wafer; Based on the relation of diameter wafer and wafer distortion amount, obtain the corresponding wafer distortion amount of measured diameter;
The relation of said diameter wafer and wafer distortion amount obtains through the following step: choose the wafer test piece and heat-treat technology; After measuring Technology for Heating Processing, many groups diameter of wafer test piece and corresponding wafer distortion amount; According to measured many groups diameter and corresponding wafer distortion amount, obtain the relation of diameter wafer and wafer distortion amount;
The relation of said wafer distortion amount and distortion's amount obtains through following step: choose the wafer test piece and heat-treat technology; After measuring Technology for Heating Processing, many groups deflection of wafer test piece and corresponding departure data; With measured wafer distortion amount and distortion's amount fitting function, obtain the relation of wafer distortion amount and distortion amount.
4. the manufacturing approach of semiconductor device as claimed in claim 3 is characterized in that, also comprises:
After double-deck grid oxide layer technology, measure the wafer distortion amount;
Based on the relation of wafer distortion amount and distortion's amount, if the corresponding distortion's amount of said wafer distortion amount exceeds process specification, then revise said wafer distortion, to reduce distortion's amount.
5. the manufacturing approach of semiconductor device as claimed in claim 3 is characterized in that, also comprises:
Behind the 3rd layer of gate oxidation layer process, measure the wafer distortion amount;
Based on the relation of wafer distortion amount and distortion's amount, if the corresponding distortion's amount of said wafer distortion amount exceeds process specification, then revise said wafer distortion, to reduce distortion's amount.
6. like the manufacturing approach of each described semiconductor device of claim 3 to 5; It is characterized in that; Said correction wafer distortion comprises: according to the wafer distortion amount wafer each several part is applied corresponding temperature, make the wafer each several part be heated inhomogeneous and produce different temperature distortions.
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| CN102543740A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for improving alignment uniformity between polycrystalline silicon gate and contact hole |
| CN102931117A (en) * | 2012-11-21 | 2013-02-13 | 苏州矽科信息科技有限公司 | Method for measuring deformation in wafer transmission by using principle of light reflection |
| JP6794880B2 (en) * | 2017-03-14 | 2020-12-02 | 東京エレクトロン株式会社 | Operation method of vertical heat treatment equipment and vertical heat treatment equipment |
| CN109270801B (en) * | 2018-09-29 | 2020-11-27 | 华灿光电（浙江）有限公司 | Exposure method |
| CN109560002A (en) * | 2018-11-30 | 2019-04-02 | 上海华力微电子有限公司 | The monitoring method of silicon wafer warpage degree |
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| CN101206995A (en) * | 2006-12-20 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for monitoring crystal round pallet obliteration performance |
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| CN101206995A (en) * | 2006-12-20 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for monitoring crystal round pallet obliteration performance |
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| JP特开2005-196216A 2005.07.21 |
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