CN101728412A - 电阻式存储器单元和电阻式存储器阵列 - Google Patents
电阻式存储器单元和电阻式存储器阵列 Download PDFInfo
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Abstract
本发明公开了一种位于基底上的电阻式存储器单元和电阻式存储器阵列。所述电阻式存储器单元包括第一栅极、第二栅极、共用掺杂区域、接触窗插塞、位线以及电阻式存储器元件。第一栅极及第二栅极分开配置于所述基底上。第一栅极的第一宽度与第二栅极的第二宽度不同。此外,第一栅极与第二栅极的共用掺杂区域配置于基底中。接触窗插塞电性连接至共用掺杂区域,且位线配置于基底上。此外,电阻式存储器元件连接于接触窗插塞与位线之间。在本发明中,位元密度得以增加。此外,通过控制栅极的宽度,不同数据储存状态的编程电流之间的差异得以增加,且在不受栅极上所施加的栅极电压限制的情况下改变。
Description
技术领域
本发明涉及一种电阻式存储器单元和电阻式存储器阵列。更明确而言,本发明是涉及一种电阻式存储器阵列,其中电阻式存储器单元中的每一者具有至少四个存储器储存状态。
背景技术
非易失性存储器即使在电源被移除时亦维持所储存的数据。因此,非易失性存储器已在电脑、移动通信系统、存储卡等等中得以广泛使用。快闪存储器广泛用于非易失性存储器。在快闪存储器中,通常,存储器单元分别具有堆叠栅极结构。通常,所述堆叠栅极结构中的每一者包含隧穿氧化物层、浮动栅极、栅极间介电层以及控制栅极电极,其均依序堆叠于沟道区域上。为增强快闪存储器单元的可靠性及编程效率,应改良隧穿氧化物层的膜品质,且应增加快闪存储器单元的耦合比率。
最近,开发一种新的非易失性存储器(诸如电阻随机存取存储器(resistance random access memory,RRAM),用于取代快闪存储器。按照惯例,RRAM的单位电阻式存储器单元包含切换装置及串联连接至所述切换装置的数据储存元件。另外,电阻式存储器单元的数据储存元件由可变电阻材料制成,所述材料的电阻率回应于呈穿过其的电流形式的电信号而改变。因此,通过适当地控制穿过可变电阻材料的编程电流,可以电阻形式将数据储存于电阻式存储器单元中。然而,编程电流的量值由外部设定的顺应性限制决定,所述顺应性限制进一步由用作电阻式存储器单元中的切换装置的驱动金属氧化物半导体场效晶体管(metal-oxide-semiconductor field effecttransistor,MOSFET)的栅极电压决定。
发明内容
本发明提供一种位于基底上的电阻式存储器单元。所述电阻式存储器单元包括第一栅极、第二栅极、共同掺杂区域、接触窗插塞、位线以及电阻式存储器元件。第一栅极及第二栅极分开配置于所述基底上。应注意,第一栅极的第一宽度与第二栅极的第二宽度不同。此外,第一栅极与第二栅极的共同掺杂区域配置于基底中。接触窗插塞电性连接至共同掺杂区域,且位线配置于基底上。此外,电阻式存储器元件连接于接触窗插塞与位线之间。
本发明亦提供一种电阻式存储器阵列。所述电阻式存储器阵列包括基底、作为MOSFET栅极的多个平行字线、多个位线以及多个电阻式存储器元件。平行字线对位于基底上,且每一平行字线对包括彼此平行的第一栅极及第二栅极。所述两个栅极亦共用一个共同掺杂区域,例如共同漏极。第一栅极的第一宽度与第二栅极的第二宽度不同。位线配置于基底上且配置于平行栅极对上。电阻式存储器元件分别位于位线与共同掺杂区域之间,且所述每一位线经由电阻式存储器元件其中之一电性连接至共同掺杂区域。
在本发明中,由于共用一个共同掺杂区域的栅极的不等宽度,总共可存在四个存储器状态,其表示针对单个电阻式存储器单元的两个数据位元的状态。因此,位元密度得以增加。此外,通过控制栅极的宽度,不同数据储存状态的编程电流之间的差异得以增加,且在不受栅极上所施加的栅极电压限制的情况下改变。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
本发明包含附图是为了提供对本发明的进一步理解,且随附图并入本说明书中,并构成本说明书的一部分。所述附图说明本发明的实施例,且连同描述内容一起,用以阐释本发明的原理。
图1是示意性地说明根据本发明实施例的电阻式存储器阵列的俯视图。
图2是沿图1中的线I-I截取的横截面图,且绘示根据本发明实施例的电阻式存储器单元。
图3是绘示根据本发明另一实施例的电阻式存储器单元的横截面图。
图4是绘示电阻式存储器单元的电压调变操作与电阻式存储器单元的栅极宽度调变操作之间的差异的源极-漏极电流对比栅极电压的曲线图。
附图标记说明
100:基底
102:掺杂区域
104a:第一掺杂区域
104b:第二掺杂区域
106:平行栅极对
106a:第一栅极
106b:第二栅极
108:位线
110:电阻式存储器元件
202:介电层
204:接触窗插塞
206:顶部电极
208:电阻材料层
210:导电层
W1:第一宽度
W2:第二宽度
具体实施方式
图1是示意性地说明根据本发明实施例的电阻式存储器阵列的俯视图。如图1中所示,提供基底100。基底100中形成有多个掺杂区域102(未图示),所述多个掺杂区域102由隔离区域(亦未图示)隔开。掺杂区域102的导电型与基底100的导电型不同。
如图1中所示,多个平行栅极对106位于基底100上。每一平行栅极对106包括彼此平行的第一栅极106a及第二栅极106b。值得注意的是,每一平行栅极对106中,第一栅极及第二栅极共用掺杂区域102。此外,第一栅极106a的第一宽度w1与第二栅极106b的第二宽度w2不同。再者,第一宽度w1与第二宽度w2的优选比率约为1.5至9。此外,第一宽度w1约为10nm至90nm,且第二宽度w2约为5nm至35nm。在本发明的实施例中,第一宽度w1约为33nm至72nm,且第二宽度w2约为6nm至28nm。此外,在另一实施例中,第一宽度w1与第二宽度w2的总和等于特征尺寸F,而特征尺寸F亦即为最小光刻间距的一半。意即,第一宽度w1及第二宽度w2两者均小于特征尺寸F。
如图1中所示,对于每一平行栅极对106中,有第一掺杂区域104a及第二掺杂区域104b,其配置于基底100中,且分别邻近于第一栅极106a及第二栅极106b,且与第一栅极106a与第二栅极106b之间的共同掺杂区域102不同。换言之,对于图1中所示的存储器阵列中的同一行中的电阻式存储器单元而言,掺杂区域102例如可作为第一栅极106a与第二栅极106b的共同漏极区域。而且,第一掺杂区域104a作为第一栅极106a的源极区域,且第二掺杂区域104b作为第二栅极106b的源极区域。应注意的是,第一掺杂区域104a的导电型与基底100的导电型不同,且第二掺杂区域104b的导电型亦与基底100的导电型不同。而且,第一掺杂区域104a及第二掺杂区域104b例如可接地或连接至电力轨(power rail)。此外每一平行栅极对106彼此以至少一隔离区域(未绘示)相互电性隔离。亦即相邻两平行栅极对106的源极区域(包括掺杂区域104a与104b)彼此于基底100中已至少一隔离区域相互电性隔离。而上述隔离区域包括浅沟槽隔离。
此外,多个位线108配置于基底100上,且横越平行栅极对106。位线的材料例如为导电材料,诸如金属或掺杂多晶硅。而且,多个电阻式存储器元件110分别位于位线108与共同掺杂区域102之间。应注意的是,每一位线108经由电阻式存储器元件110电性连接至共同掺杂区域102其中之一。电阻式存储器元件110的材料可为可变电阻材料,其根据所施加的电压展现出可逆电阻切换。意即,电阻式存储器元件110的材料回应于主要穿过电阻式存储器元件110的电信号而改变电阻。电阻式存储器元件110的材料可为硫化物、金属氧化物或钙钛矿材料。
图2是沿图1中的线I-I截取的横截面图,且绘示根据本发明实施例的电阻式存储器单元。在下文中详细描述单个电阻式存储器单元,且在图1及图2两者中,相同数字标记表示相同元件。如图2中所示,第一栅极106a及第二栅极106b分开配置于基底100上。如先前所提及,第一栅极106a的第一宽度w1与第二栅极106b的第二宽度w2不同。
接着,如图2中所示,第一栅极106a及第二栅极106b具有配置于基底100中位于第一栅极106a与第二栅极106b之间的共同掺杂区域102。接触窗插塞204位于基底100上,且电性连接至共同掺杂区域102。此外,位线108配置于基底100上,且横过第一栅极106a及第二栅极106b。位线108通过介电层202与第一栅极106a及第二栅极106b隔离。而且,电阻式存储器元件110配置于接触窗插塞204及基底100上,且连接接触窗插塞204与位线108之间。
如图2中所示,本发明的电阻式存储器元件110位于介电层202内。在电阻式存储器元件110与位线108之间,可存在作为顶部电极的导电层206。而且,在电阻式存储器元件110与接触窗插塞204之间,可存在作为底部电极的导电层(未图示)。顶部电极206的材料可为铱、铂、氧化铱、氮化钛、氮化钛铝、钌或氧化钌。在实施例中,顶部电极206的材料可为多晶硅。此外,电阻式存储器元件110与接触窗插塞204之间的底部电极(未图示)的材料可为铱、铂、氧化铱、氮化钛、氮化钛铝、钌、氧化钌或多晶硅。
在图2中所示的实施例中,电阻式存储器元件是位于位线108与接触窗插塞204之间且在共同掺杂区域102上方的块状元件。然而,本发明不受电阻式存储器元件的形式限制。图3是绘示根据本发明另一实施例的电阻式存储器单元的横截面图。如图3中所示,本发明的电阻式存储器单元拥有一对形成于基底100上的栅极,包含第一栅极106a及第二栅极106b。介电层202位于基底100上,且如图3中所示,接触窗插塞204穿透介电层202。此外,位线108位于介电层202上,且横过第一栅极106a及第二栅极106b。
在介电层202与位线108之间,存在形成于介电层202上的电阻材料层208。更具体而言,在此实施例中,位于接触窗插塞204正上方且在位线108下方的电阻式存储器元件110是材料层208的一部分。因此,经过共同掺杂区域102与位线108之间的电信号主要穿过电阻式存储器元件110。电阻式存储器元件110的电阻率回应于上述电信号而改变,且电阻式存储器元件110作为可至少在两个电阻率值之间改变的可变电阻器。
具有电阻式存储器元件110的材料层208的材料可为金属氧化物、钙钛矿材料(诸如庞磁阻性(colossal magnetoresistive,CMR)材料),或高温超导(high temperature superconducting,HTSC)材料,诸如PrCaMnO3(PCMO)。在实施例中,所述金属氧化物包含氧化铪。而且,所述金属氧化物可由化学式MxOy表示,其中M、O、x、y分别表示过渡金属、氧、过渡成分及氧成分。此外,所述金属可为铝、钽、镍、铌、铬、铜、铁、钴、铪、锆或钛。另外,导电层210配置于位线108与材料层208之间。导电层210作为电阻式存储器元件110的顶部电极。顶部电极210的材料可为铱、铂、氧化铱、氮化钛、氮化钛铝、钌或氧化钌。在实施例中,顶部电极210的材料例如是多晶硅。
在本发明中,对于单个电阻式存储器单元而言,具有不同宽度的两个栅极共用作为共同漏极区域的共同掺杂区域,使得本发明所提供的电阻式存储器单元为用于根据不同编程层次存储多位的多阶存储单元(multi-level cell,MLC)。此外,通过使用具有根据不同操作层次而改变的可变电阻的电阻式存储器单元,本发明所提供的电阻式存储器单元亦可用以作为多阶开关或多阶选择器。通常,具有较小栅极宽度(诸如第二宽度w2)的金属氧化物半导体场效晶体管(MOSFET)与具有较大栅极宽度(诸如第一宽度w1)的金属氧化物半导体场效晶体管(MOSFET)相比,在相同施加电压下可产生较大驱动电流。因此,每一电阻式存储器阵列中的电阻式存储器单元可由三个不同电流位准驱动,包含较小电流与较大电流的总和、较小电流以及较大电流。在分别具有三个电流位准的操作下,对应地产生电阻式存储器元件的三个不同的电阻状态。因此,电阻式存储器元件的三个电阻状态进一步与未经程式化的状态组合,以得出总共四个状态。
具体而言,当将同一栅极电压V1施加至分别具有第一栅极106a及第二栅极106b的两个MOSFET,使得所述两个MOSFET被开启时,穿过电阻式存储器元件110的电信号以穿过第一栅极下的第一沟道的第一电流与穿过第二栅极下的第二沟道的第二电流的总和电流的形式呈现。为回应于上述总和电流的形式的电信号,电阻式存储器元件110的电阻切换至第一电阻R1。或者,当具有第一栅极106a的MOSFET关闭,且具有第二栅极106b的MOSFET以电压V1开启时,穿过电阻式存储器元件110的电信号仅以第二晶体管的电流的形式呈现。为回应于此电信号,电阻式存储器元件110的电阻切换为第二电阻R2。另外,当具有第一栅极106a的MOSFET以栅极电压V1开启,且具有第二栅极106b的MOSFET关闭时,穿过电阻式存储器元件110的电信号仅以第一晶体管的电流的形式呈现。为回应于所述电信号,电阻式存储器元件110的电阻切换为第三电阻R3。此外,当电阻式存储器单元处于未经程式化的状态时,则电阻式存储器元件的电阻表示为第四电阻R4。因此,第一电阻、第二电阻、第三电阻以及第四电阻分别表示两个数据位元的状态。
在本发明中,通过控制同一电阻式存储器单元内的栅极的宽度,可容易达成将一个以上位元数据储存于有限尺寸的存储器单元中的目的。图4是线性(三极管)操作下源极-漏极电流对比栅极电压的曲线图,绘示电阻式存储器单元的电压调变操作与电阻式存储器单元的栅极宽度调变操作之间的差异。画有空心圆圈表示针对两种情况的每一者的最大及半最大电流的自然选择。如图4中所示,对于同一电阻式存储器单元中的栅极的宽度彼此相等的电压调变操作,当电压为3.3V时,最大源极-漏极电流不如针对栅极宽度调变情况大。显然,使用不同栅极宽度(意即,栅极宽度调变操作)比针对同一栅极宽度使用不同栅极电压(意即,电压调变操作)有利,因为栅极宽度调变的可用源极-漏极电流较大。此外,通过缩短栅极的宽度,可用源极-漏极电流可进一步增加。而且,通过针对不同栅极宽度、不同源极-漏极电压或不同位线电压施加不同栅极电压,可存取额外中间存储状态,其增加位元密度。
本领域一般技术人员将明白,可在不脱离本发明的范畴或精神的情况下,对本发明的结构作各种修改及改变。虽然本发明已以实施例披露如上,然而其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视所附的权利要求所界定者为准。
Claims (12)
1.一种位于基底上的电阻式存储器单元,包括:
第一金属氧化物半导体场效晶体管及第二金属氧化物半导体场效晶体管,该第一金属氧化物半导体场效晶体管与该第二金属氧化物半导体场效晶体管分别具有配置于该基底上的第一栅极及第二栅极,其中该第一栅极的第一宽度与该第二栅极的第二宽度不同,且该第一金属氧化物半导体场效晶体管及该第二金属氧化物半导体场效晶体管共用共同掺杂区域;
接触窗插塞,电性连接至该共同掺杂区域;
位线,其配置于所述基底上;以及
电阻式存储器元件,连接于该接触窗插塞与该位线。
2.如权利要求1所述的电阻式存储器单元,其中该第一宽度与该第二宽度的比率约为1.5至9。
3.如权利要求1所述的电阻式存储器单元,其中该第一宽度约为10nm至90nm。
4.如权利要求1所述的电阻式存储器单元,其中该第二宽度约为5nm至35nm。
5.如权利要求1所述的电阻式存储器单元,其中该电阻式存储器元件在该位线下沿该位线延伸。
6.如权利要求1所述的电阻式存储器单元,其中该电阻式存储器元件的材料包含金属氧化物。
7.一种位于基底上的电阻式存储器阵列,包括:
多对金属氧化物半导体场效晶体管,位于该基底上,其中每一对金属氧化物半导体场效晶体管共用形成于该对金属氧化物半导体场效晶体管中的共同掺杂区域,且每一对金属氧化物半导体场效晶体管包括彼此平行的第一栅极及第二栅极,且该第一栅极的第一宽度与该第二栅极的第二宽度不同;
多个位线,配置于该基底上,且横过每一对金属氧化物半导体场效晶体管中的该第一栅极及该第二栅极;以及
多个电阻式存储器元件,分别位于该些位线与该些共同掺杂区域之间,其中每一位线经由该电阻式存储器元件中的电性连接至每一共同掺杂区域。
8.如权利要求7所述的电阻式存储器阵列,其中该第一宽度与该第二宽度的比率约为1.5至9。
9.如权利要求7所述的电阻式存储器阵列,其中该第一宽度约为10nm至90nm。
10.如权利要求7所述的电阻式存储器阵列,其中该第二宽度约为5nm至35nm。
11.如权利要求7所述的电阻式存储器阵列,其中该电阻式存储器元件的材料包含金属氧化物。
12.如权利要求7所述的电阻式存储器阵列,其中该电阻式存储器元件以线型形式在每一位线下且沿每一该些位线配置。
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US12/264,225 US20100108980A1 (en) | 2008-11-03 | 2008-11-03 | Resistive memory array |
US12/264,225 | 2008-11-03 |
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