CN101727014B - Photoetching method for controlling characteristic dimension and photoetching system thereof - Google Patents
Photoetching method for controlling characteristic dimension and photoetching system thereof Download PDFInfo
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- CN101727014B CN101727014B CN2008102252270A CN200810225227A CN101727014B CN 101727014 B CN101727014 B CN 101727014B CN 2008102252270 A CN2008102252270 A CN 2008102252270A CN 200810225227 A CN200810225227 A CN 200810225227A CN 101727014 B CN101727014 B CN 101727014B
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Abstract
The invention provides a photoetching method for controlling a characteristic dimension and a photoetching system thereof. The photoetching method comprises the following steps: photoetching semiconductor chips with photoresist layers through a process factor of a target value to form at least two mask patterns of different characteristic dimensions on each semiconductor chip; measuring and calculating a characteristic dimension difference value of any two mask patterns of the different characteristic dimensions; calculating an actual value of the process factor according to the characteristic dimension difference value and linear relationship between the characteristic dimension difference value and the process factor; adjusting the target value of the process factor according to magnitude relationship between the target value and the actual value of the process factor; and photoetching n semiconductor chips with the photoresist layers by utilizing the adjusted target value of the process factor. The method has the advantages of reducing the error of the characteristic dimension of the photoetch mask pattern and improving the accuracy of the mask pattern.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of photoetching method of controlling features size and etching system.
Background technology
In semiconductor was made, along with dwindling of dimensions of semiconductor devices, (CD) was also more and more littler for the characteristic dimension of semiconductor devices, so the also more and more difficult control of the degree of accuracy of CD.Because the error of CD directly has influence on the performance of device, so the CD error Control is just more and more important.In the manufacture process of semiconductor devices, usually at first on semiconductor wafer, apply photoresist layer, form mask pattern by photoetching, under the sheltering of mask pattern, carry out etching, thereby in semiconductor wafer, obtain the etching figure wanted, so the error of mask pattern CD directly has influence on the degree of accuracy of etching figure.Because the production run of semiconductor devices is to adopt the mode of streamline, for example, the photoetching base station is finished after the photoetching of bulk of semiconductor crystal chips, can carry out photoetching to the next group semiconductor wafer.As shown in Figure 1, finish in the prior art after the photoetching of bulk of semiconductor crystal chips, generally be by back staff manual analyzing photoetching semiconductor wafer on the error of mask pattern CD, judge whether to exceed acceptability limit, when exceeding acceptability limit, the parameter of photoetching base station is adjusted, be used for the next group semiconductor wafer is carried out photoetching,, directly carry out photoetching next time if do not exceed acceptability limit then do not adjust parameter.Because the efficient that the staff analyzes is lower, therefore the number of times of analyzing is limited, and have only and when exceeding acceptability limit, just carry out feedback adjusting, like this when the error of the mask pattern CD on the semiconductor wafer is in acceptability limit, just do not carry out feedback adjusting, so just can not effectively reduce the error of next group semiconductor wafer mask pattern CD in photoetching.
In open day on October 15th, 2003, notification number CN1449577, title: in the method for performing final critical dimension control and the Chinese patent of device, provide a kind of method and device of carrying out last characteristic dimension control, be used for improving the degree of accuracy of etching CD, reduce error.This method is obtained continuous data from semiconductor wafer after carrying out metal deposition process, photoetching process or etching technics; Carry out final characteristic dimension control adjusting process with described continuous data, comprising continuous data is associated with this semiconductor wafer, according to this incidence relation driven dimension error, and the parameter of Correction and Control input, for example can revise, feed back then the exposure dose and the exposure focal length of lithography step.
But the problem that said method exists is that the degree of accuracy of the exposure metering and the focal length that exposes is adjusted complexity than difficult control, and can't reduce the error of mask pattern CD at the situation with the mask pattern of two kinds of different CD of formation on the semiconductor wafer.
Summary of the invention
In order to address the above problem, the invention provides a kind of photoetching method and etching system of controlling features size, reduced the error of the mask pattern CD that forms after the photoetching, improved the degree of accuracy of mask pattern.
The photoetching method of controlling features size of the present invention comprises step:
Utilize the process factor of desired value that the semiconductor wafer that the n sheet has photoresist layer is carried out photoetching, form the mask pattern of at least two kinds of different characteristic sizes on each chip semiconductor wafer, wherein n is a natural number;
Extract the described semiconductor wafer of a slice at least, measure and calculate the characteristic dimension difference of the mask pattern of any two kinds of described different characteristic sizes;
According to described characteristic dimension difference, and the linear relationship of described characteristic dimension difference and described process factor, the actual value of calculating process factor;
According to the desired value of process factor and the magnitude relationship of actual value, the desired value of the adjusting process factor;
Utilize the desired value of adjusted process factor that the semiconductor wafer that the n sheet has photoresist layer is carried out photoetching.
Optionally, the linear relationship of described characteristic dimension difference and process factor, computing method are:
The linear relationship of described characteristic dimension difference and process factor, computing method are:
Process factor with first desired value is carried out photoetching to the semiconductor wafer that the n sheet has photoresist layer, forms the mask pattern of at least two kinds of different characteristic sizes on each chip semiconductor wafer, and wherein n is a natural number;
Extract the described semiconductor wafer of a slice at least, measure and calculate the characteristic dimension difference of the mask pattern of any two kinds of described different characteristic sizes;
Change first desired value of process factor;
At least above-mentioned steps is carried out in circulation, the first desired value difference of the process factor of photoetching each time in the lithography step of carrying out above-mentioned steps wherein, the semiconductor wafer difference of photoetching each time;
Obtain the linear relationship of described characteristic dimension difference and process factor according to first desired value of characteristic dimension difference that obtains and corresponding process factor thereof.
Optionally, the desired value method of the described adjusting process factor is:
Calculate the desired value of process factor and the difference of actual value, when actual value greater than desired value, desired value is deducted described difference as the new desired value of process factor; When actual value less than desired value, desired value is added the above difference as the new desired value of process factor.
Optionally, the light source of described exposure adopts the mode of ring illumination.
Optionally, described process factor is the external process factor or the internal process factor.
Optionally, an opening figure on the corresponding mask of the mask pattern of each described characteristic dimension, the method for described exposure is the reckling in the described opening figure of alignment.
Corresponding the present invention also provides a kind of etching system of controlling features size, comprises photoetching base station, characteristic dimension measurement mechanism, deviation calculation device, process factor calculation element and feedback assembly, wherein,
The photoetching base station comprises exposure system and developing apparatus, and described exposure system is used to utilize the process factor of desired value that the semiconductor wafer with photoresist layer is exposed;
Described developing apparatus is used for the semiconductor wafer after the exposure system exposure is developed, and forms the mask pattern of at least two kinds of different characteristic sizes in the photoresist layer on the described semiconductor wafer of each sheet;
The characteristic dimension measurement mechanism is used to measure the characteristic dimension of the mask pattern of any two kinds of described different characteristic sizes that obtain after the photoetching of photoetching base station;
The deviation calculation device is used for the characteristic dimension difference of the mask pattern of any two kinds of described different characteristic sizes that the calculated characteristics dimension measuring device measures;
The process factor calculation element is used for according to described characteristic dimension difference, and the linear relationship of described characteristic dimension difference and described process factor is calculated the actual value of process factor;
Feedback assembly is used for the described actual value of comparison process factor and the magnitude relationship of described desired value, and determine the value that the desired value of process factor should be adjusted to according to described magnitude relationship, and the value that should adjust to feeds back to the exposure system of photoetching base station as new desired value.
Optionally, the light source of described exposure system is a ring illumination.
Optionally, described process factor is the external process factor or the internal process factor.
The advantage of technique scheme is: the characteristic dimension of the mask pattern by measuring any two kinds of different characteristic sizes that photoetching obtains, obtain described characteristic dimension difference, utilize the linear relationship of described characteristic dimension difference and described characteristic dimension difference and process factor, the desired value of the adjusting process factor, carry out photoetching next time with the process factor of new desired value then, thereby reduce the error of characteristic dimension of the mask pattern of photoetching next time.
In a technical scheme, utilize first desired value of process factor to carry out photoetching, the characteristic dimension of the mask pattern by measuring any two kinds of different characteristic sizes that photoetching obtains, obtain described characteristic dimension difference, the step of described photoetching and measurement is carried out in circulation then, the first desired value difference of the process factor of photoetching each time in carrying out the lithography step of above-mentioned steps wherein, the semiconductor wafer difference of photoetching each time, thereby obtain first desired value and the characteristic of correspondence dimension difference of many group process factor, utilize described first desired value and corresponding described characteristic dimension difference to obtain the linear relationship of described characteristic dimension difference and process factor at last, utilize the linear relationship that obtains more described characteristic dimension difference and process factor that this method can be easy, for the process factor adjustment that exposes in the photoetching provides foundation.
Description of drawings
Fig. 1 is the synoptic diagram of a kind of photoetching method in the prior art;
Fig. 2 is the process flow diagram of the photoetching method embodiment of controlling features size of the present invention;
Fig. 3-Fig. 4 is an employed exposure system synoptic diagram among the photoetching method embodiment of controlling features size of the present invention;
Fig. 5 is a semiconductor wafer surface synoptic diagram after the photoetching among the photoetching method embodiment of controlling features size of the present invention;
Fig. 6 is the synoptic diagram of photoetching method one embodiment of controlling features size of the present invention;
Fig. 7 is the synoptic diagram of etching system one embodiment of controlling features size of the present invention.
Embodiment
Because the production run of semiconductor devices is to adopt the mode of streamline, for example after the photoetching of finishing bulk of semiconductor crystal chips, can carry out photoetching to the next group semiconductor wafer.Finish in the prior art after the photoetching of bulk of semiconductor crystal chips, it generally is CD error by the mask pattern after the photoetching of staff's manual analyzing, judge whether to exceed acceptability limit, when exceeding acceptability limit, the parameter of photoetching base station is adjusted, be used for the next group semiconductor wafer is carried out photoetching, if do not exceed acceptability limit then do not adjust parameter and directly carry out photoetching next time.Because the efficient that the staff analyzes is lower, therefore the number of times of analyzing is limited, and have only and when exceeding acceptability limit, just carry out feedback adjusting, like this when the error of mask pattern CD on the semiconductor wafer is in acceptability limit, just do not carry out feedback adjusting, so just can not effectively reduce the error of next group semiconductor wafer photoetching.
Think after inventor's research: in the manufacturing of semiconductor devices, make a plurality of semiconductor devices, for example 2,10,100 because on a semiconductor wafer, understand usually.So just need be on a semiconductor wafer once photoetching form the multiple mask pattern of different CD, but can only alignment a kind of CD wherein in exposure process at the exposure of the mask pattern of multiple different CD, will cause the CD of the figure that does not have alignment to have like this than mistake.For example, a photoetching forms the mask pattern of 90nm and 100nm, if the mask pattern of alignment 100nm then should just may be offset 90nm far away for the mask pattern of 90nm after the photoetching.In the process of photoetching, the used exposure system of exposing generally includes exposure light source, lens and mask.During exposure, exposure light source sees through the opening figure on the mask, and the picture of opening figure is become to lens, sees through lens then and arrives on the photoresist layer on the semiconductor wafer, and photoresist layer is exposed.Described opening figure is called process factor (sigma) at the area of the central plane imaging of lens and the ratio of central plane.Because process factor can influence the resolution of exposure system imaging, therefore can adjust the CD of the mask pattern of photoetching formation by the adjusting process factor.
In conjunction with above-mentioned research, a kind of desired value of inventor, thereby the method for the CD error of mask pattern after the adjustment photoetching by the process factor in the adjustment step of exposure.
The photoetching method of controlling features size of the present invention comprises step:
Utilize the process factor of desired value that the semiconductor wafer that the n sheet has photoresist layer is carried out photoetching, form the mask pattern of at least two kinds of different characteristic sizes on each chip semiconductor wafer, wherein n is a natural number;
Extract the described semiconductor wafer of a slice at least, measure and calculate the characteristic dimension difference of the mask pattern of any two kinds of described different characteristic sizes;
According to described characteristic dimension difference, and the linear relationship of described characteristic dimension difference and described process factor, the actual value of calculating process factor;
According to the desired value of process factor and the magnitude relationship of actual value, the desired value of the adjusting process factor;
Utilize the desired value of adjusted process factor that the semiconductor wafer that the n sheet has photoresist layer is carried out photoetching.
Wherein, the linear relationship of described characteristic dimension difference and process factor, computing method are:
Process factor with first desired value is carried out photoetching to the semiconductor wafer that the n sheet has photoresist layer, forms the mask pattern of at least two kinds of different characteristic sizes on each chip semiconductor wafer, and wherein n is a natural number;
Extract the described semiconductor wafer of a slice at least, measure and calculate the characteristic dimension difference of the mask pattern of any two kinds of described different characteristic sizes;
Change first desired value of process factor;
At least above-mentioned steps is carried out in circulation, the first desired value difference of the process factor of photoetching each time in the lithography step of carrying out above-mentioned steps wherein, the semiconductor wafer difference of photoetching each time;
Obtain the linear relationship of described characteristic dimension difference and process factor according to first desired value of characteristic dimension difference that obtains and corresponding process factor thereof.
Wherein, the desired value method of the described adjusting process factor is:
Calculate the desired value of process factor and the difference of actual value, when actual value greater than desired value, desired value is deducted described difference as the new desired value of process factor; When actual value less than desired value, desired value is added the above difference as the new desired value of process factor.
Wherein, the light source of described exposure adopts the mode of ring illumination.
Wherein, described process factor is the external process factor or the internal process factor.
Wherein, the mask pattern of each described characteristic dimension is corresponding to an opening figure on the mask, and the method for described exposure is the reckling in the described opening figure of alignment.
Corresponding the present invention also provides a kind of etching system of controlling features size, comprises photoetching base station, characteristic dimension measurement mechanism, deviation calculation device, process factor calculation element and feedback assembly, wherein,
The photoetching base station comprises exposure system and developing apparatus, and described exposure system is used to utilize the process factor of desired value that the semiconductor wafer with photoresist layer is exposed;
Described developing apparatus is used for the semiconductor wafer after the exposure system exposure is developed, and forms the mask pattern of at least two kinds of different characteristic sizes in the photoresist layer on the described semiconductor wafer of each sheet;
The characteristic dimension measurement mechanism is used to measure the characteristic dimension of the mask pattern of any two kinds of described different characteristic sizes that obtain after the photoetching of photoetching base station;
The deviation calculation device is used for the characteristic dimension difference of the mask pattern of any two kinds of described different characteristic sizes that the calculated characteristics dimension measuring device measures;
The process factor calculation element is used for according to described characteristic dimension difference, and the linear relationship of described characteristic dimension difference and described process factor is calculated the actual value of process factor;
Feedback assembly is used for the described actual value of comparison process factor and the magnitude relationship of described desired value, and determine the value that the desired value of process factor should be adjusted to according to described magnitude relationship, and the value that should adjust to feeds back to the exposure system of photoetching base station as new desired value.
Wherein, the light source of described exposure system is a ring illumination.
Wherein, described process factor is the external process factor or the internal process factor.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Embodiment one
Please refer to Fig. 2.
S110: utilize the process factor of desired value that the semiconductor wafer that the n sheet has photoresist layer is carried out photoetching, on each chip semiconductor wafer, form the mask pattern of at least two kinds of different characteristic sizes.
At first, in order after photoetching, to obtain the mask pattern of ideal dimensions, need for step of exposure parameter be set in this step, utilize exposure system to expose in the present embodiment, therefore need parameter be set for exposure system, the setting of this parameter is relevant with the ideal dimensions of required mask pattern, and those skilled in the art can be provided with the desired value (σ) of process factor (sigma) according to the ideal dimensions of required mask pattern, and exposure light source wavelength (λ), numerical aperture parameters such as (NA).
In the present embodiment will be with at least two kinds of different ideal dimensions exposures, form the mask pattern of at least two kinds of different characteristic sizes, because the opening figure on the mask plate of the more little correspondence of mask pattern is more little usually, resolution is low more, therefore preferably process factor is made as the required process factor of mask pattern corresponding opening figure than small-feature-size, for example two of mask pattern kinds of ideal dimensions are 129nm and 172nm, and then process factor is set to the required process factor desired value of mask pattern that characteristic dimension is 129nm.
In addition as Fig. 4, the described light source of Fig. 5 can adopt circular illumination or ring illumination, because adopt ring illumination can improve the degree of accuracy of exposure, therefore adopt ring illumination in the present embodiment, therefore process factor also just is divided into the internal process factor (sigma-inner) and the external process factor (sigma-outer), the known internal process factor is less than the external process factor, because the difference of the internal process factor and the external process factor is fixing, (just the internal process factor is than the little fixed numbers of the external process factor), just adjusted one another also can be corresponding adjust together, therefore in the present embodiment, described process factor can be wherein any one.In the present embodiment, two kinds of ideal dimensions of mask pattern are 129nm and 172nm, the wavelength of exposure light source (λ) is set to 193nm, numerical aperture (NA) is 0.78, the desired value (σ) of the internal process factor (sigma-inner) is 0.536, and the desired value (σ) of the external process factor (sigma-outer) is 0.74.
Then, with the process factor of desired value the semiconductor wafer that the n sheet has photoresist layer is exposed, wherein n is a natural number.
In the present embodiment, at first provide n chip semiconductor wafer 100, wherein n is a natural number, for example can be 1,10 or 27 etc.Described semiconductor wafer 100 can be monocrystalline silicon, polysilicon or amorphous silicon; Described semiconductor wafer 100 also can be silicon, germanium, gallium arsenide or silicon Germanium compound; This semiconductor wafer 100 can also have epitaxial loayer or insulation course silicon-on.
This semiconductor wafer 100 can also comprise rhythmo structure, and for example described rhythmo structure can be conductive layer-insulating medium layer from bottom to up, can also be grid oxide layer-grid layer.Have photoresist layer 102 on the described semiconductor wafer 100, photoresist layer 102 can adopt method well known to those skilled in the art to form, for example spin-coating method.
Described light source can adopt circular illumination or ring illumination, adopts ring illumination in the present embodiment.The opening figure and the markers align in the exposure system that begin to be provided with on the mask in exposure also are called alignment, so just can form required mask pattern at the ad-hoc location on the photoresist layer of semiconductor wafer, it is 122 main mask pattern that the main opening figure of for example aiming at CD and be 122nm can form CD, and aiming at CD is that the secondary opening figure of 172nm can form the secondary mask pattern that CD is 122nm.In the photoresist layer of a slice semiconductor wafer, to form the mask pattern of two kinds of characteristic dimensions, when just main mask pattern and secondary mask pattern, usually can only alignment one of them.Because the more little resolution of the CD of opening figure to photoetching after the CD influence of mask pattern big more, therefore guarantee the accuracy of the mask pattern photoetching of less CD, Bao Guang method is the reckling in the described opening figure of alignment in the present embodiment, for example is the opening figure of 122nm in the present embodiment for alignment CD.Exposure method can adopt method well known to those skilled in the art, for example scan exposure.
Then, described n chip semiconductor wafer is developed, on each chip semiconductor wafer, form the mask pattern of at least two kinds of different characteristic sizes.This step can adopt method well known to those skilled in the art to carry out.On each chip semiconductor wafer, obtain the mask pattern of two kinds of different characteristic sizes after developing, just main mask pattern and secondary mask pattern, for example ideal dimensions is two kinds of mask patterns of 172nm and 129nm in the present embodiment, because the error of photoetching, correspondence obtains as shown in Figure 5 after development, the characteristic dimension of main mask pattern 520 (Major) is 135.0nm, and the characteristic dimension of secondary mask pattern 510 (Minor) is 171.5nm.
In the above-mentioned lithography step, except that described main mask pattern and secondary mask pattern, can also form the mask pattern of other size simultaneously, for example the mask pattern of 180nm and 200nm.
S120: extract the described semiconductor wafer of a slice at least, measure and calculate the characteristic dimension difference of the mask pattern of two kinds of described different characteristic sizes.
From the semiconductor wafer that development is finished, extract a slice or multi-disc, and from the semiconductor wafer of extracting out the mask pattern of at least two different characteristic sizes of arbitrary extracting, for example, measure CD in the present embodiment for extracting different main mask pattern and the secondary mask patterns of characteristic dimension.Measuring process can utilize method well known to those skilled in the art to measure, for example adopt optical signature dimensional measurement equipment (Optical CD, OCD) measure at the mask pattern of well-regulated mask pattern compact district, utilize the interference of folded light beam, form one group of spectral line clocklike, by analyzing these spectral lines, obtain the CD of two kinds of mask patterns.For example the characteristic dimension of main mask pattern is 135.0nm, and the characteristic dimension of secondary mask pattern is 171.5nm.
In above-mentioned steps, can extract a plurality of main mask patterns measurement CD for more accurate, ask average then, can extract a plurality of secondary mask patterns equally and measure CD, ask average then from a semiconductor wafer.
Calculate the difference (bias) of main mask pattern and secondary mask pattern CD then, described difference is an absolute value, bias=171.5nm-135.0nm=36.5nm for example, bias=|135.0nm-171.5nm|=|-36.5nm|=36.5nm.Can also extract a plurality of semiconductor wafers in addition, repeat the step of the difference of above-mentioned measurements and calculations CD, then the difference of CD asked average once more.
S130: according to described characteristic dimension difference, and the linear relationship of described characteristic dimension difference and described process factor, the actual value of calculating process factor.
According to the bias that obtains in the top step, for example in the present embodiment, bias=36.5nm.Because process factor (sigma) and described characteristic dimension difference (bias) have linear relationship, therefore can utilize method well known to those skilled in the art to obtain the linear function of process factor (sigma) and described characteristic dimension difference (bias), for example be: sigma * 80.186-24.424=bias.Thereby can draw sigma=0.76, just the actual value of process factor is 0.76.
The linear relationship of described process factor and described characteristic dimension difference, method obtains below utilizing in the present embodiment:
Wherein said difference is an absolute value.
At first: the process factor with first desired value is carried out photoetching to the semiconductor wafer that the n sheet has photoresist layer, forms the mask pattern of at least two kinds of different characteristic sizes on each chip semiconductor wafer.
This step is identical with step S110, and wherein first desired value can be different with desired value, and for example first desired value can be calculated according to the pairing process factor of the bigger mask pattern of characteristic dimension, for example is 0.92.
Then: extract the described semiconductor wafer of a slice at least, measure and calculate the characteristic dimension difference of the mask pattern of two kinds of described different characteristic sizes.
This step is identical with step S120.
Then: first desired value that changes process factor.
Can increase or reduce first desired value,, for example increase to 0.95 or be reduced to 0.87 for example with desired value.
Then: at least above-mentioned steps is carried out in circulation, the first desired value difference of the process factor of photoetching each time in the lithography step of carrying out above-mentioned steps wherein, the semiconductor wafer difference of photoetching each time.
Carry out first desired value that above-mentioned steps can obtain a process factor (sigma), and two mask patterns of described first desired value correspondence difference (bias) of the characteristic dimension (Minor) of the characteristic dimension of main mask pattern (Major) and secondary mask pattern just, carry out at least above-mentioned steps in circulation then, can obtain first desired value of at least two groups and reach the first desired value characteristic of correspondence dimension difference, be the experimental data in the present embodiment shown in for example following form:
Then: the linear relationship that obtains described characteristic dimension difference and process factor according to first desired value of characteristic dimension difference that obtains and process factor.
In the present embodiment, described light source adopts ring illumination, and described source imaging is an annular to described lens.Sigma comprises sigma-inner and sigma-outer like this, because the characteristic dimension difference of sigma-inner and sigma-outer is fixed, therefore when calculating the linear relationship of bias and sigma, can set sigma and be sigma-inner or sigma-outer one of them.
In the present embodiment, first desired value with outside process factor (sigma-outer) is a horizontal ordinate as shown in Figure 6, with described characteristic dimension difference is ordinate, set up coordinate axis, the point of the representative of the experimental data in the above table is drawn in the coordinate plane, connect above-mentioned point, just obtain straight line, this straight line has just been represented the linear relationship of process factor and described characteristic dimension difference.For example, the linear equation of measuring and calculate this straight line is: sigma * 80.186-24.424=bias.
First desired value that also can utilize following step to calculate process factor obtains the linear relationship of described characteristic dimension difference and process factor:
Get any two groups in the above-mentioned experimental data, first group process factor desired value is that the CD characteristic dimension difference of 1, the first group of master's mask pattern of σ and secondary mask pattern is bias1.
First group process factor desired value is that the CD characteristic dimension difference of 2, the second groups of master's mask patterns of σ and secondary mask pattern is bias2.
Bring above-mentioned bias1, σ 1 and bias2 and σ 2 into linear function bias=σ * a+b, wherein a, b are unknown number.
Thereby obtain the linear function of two sigma and bias:
0.92×a+b＝48.8；
0.87×a+b＝45.5；
Can obtain a ≈ 80.186, b ≈-24.424, thus the linear relationship that obtains sigma and bias is: sigma * 80.186-24.424=bias.
S140: according to the desired value of process factor and the magnitude relationship of actual value, the desired value of the adjusting process factor.
The relatively actual value and the desired value of process factor are if actual value is greater than desired value then reduce desired value; If actual value is less than desired value then increase desired value.
For example adopt following method in the present embodiment:
Calculate the poor of the actual value of process factor and desired value:
Actual value is 0.76, and desired value is 0.74, so deviation is 0.76-0.74=0.02.Deduct deviation with desired value then, 0.74-0.02=0.72 just is as new desired value.
S150: utilize the desired value of adjusted process factor that the semiconductor wafer that the n sheet has photoresist layer is carried out photoetching.
Change semiconductor wafer, utilize the desired value of adjusted process factor that semiconductor wafer is carried out photoetching.
Can also repeatedly change semiconductor wafer afterwards, carry out above-mentioned lithography step.Thereby the characteristic dimension difference of the mask pattern by measuring two kinds of different characteristic sizes that photoetching obtains on semiconductor wafer after the photoetching each time, and the linear relationship of described characteristic dimension difference and process factor, the adjusting process factor, make it more near ideal value, be used to then carry out photoetching next time, thereby reduce the error of the mask pattern CD of photoetching next time.
And in such scheme, utilize first desired value of process factor to carry out photoetching, two kinds of characteristic dimensions of the mask pattern on the same semiconductor wafer that obtains are then measured, obtain the characteristic dimension difference, then change first desired value and carry out photoetching again, and measure described characteristic dimension difference, the step of above-mentioned photoetching and measurement is carried out in circulation, utilize first desired value of the process factor of repeatedly photoetching at last, and described characteristic dimension difference obtains the linear relationship of described characteristic dimension difference and process factor, utilize the linear relationship that obtains more described characteristic dimension difference and process factor that this method can be easy, for the process factor adjustment that exposes in the photoetching provides foundation.
In the above-described embodiments, the CD characteristic dimension difference of described main mask pattern and secondary mask pattern is an absolute value.
Embodiment two
With reference to figure 7, a kind of etching system of controlling features size comprises photoetching base station 200, characteristic dimension measurement mechanism 210, deviation calculation device 220, process factor calculation element 230 and feedback assembly 240, wherein,
Developing apparatus is used for the semiconductor wafer after the exposure is developed, and forms the mask pattern of at least two kinds of different characteristic sizes in the photoresist layer on each chip semiconductor wafer;
Characteristic dimension measurement mechanism 210 is used to measure the characteristic dimension of the mask pattern of any two kinds of described different characteristic sizes that obtain after the photoetching;
Process factor calculation element 240 is used for according to described characteristic dimension difference, and the linear relationship of described characteristic dimension difference and described process factor is calculated the actual value of process factor;
Wherein, the light source of described exposure system is a ring illumination.
Wherein, described process factor is the external process factor or the internal process factor.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (7)
1. the photoetching method of a controlling features size is characterized in that, comprises step:
Utilize the process factor of desired value that the semiconductor wafer that the n sheet has photoresist layer is carried out photoetching, form the mask pattern of at least two kinds of different characteristic sizes on each chip semiconductor wafer, wherein n is a natural number;
Extract the described semiconductor wafer of a slice at least, measure and calculate the characteristic dimension difference of the mask pattern of any two kinds of described different characteristic sizes;
Change the desired value of process factor; At least above-mentioned steps is carried out in circulation, the desired value difference of the process factor of photoetching each time in the lithography step of carrying out above-mentioned steps wherein, the semiconductor wafer difference of photoetching each time; Obtain the linear relationship of described characteristic dimension difference and process factor according to the desired value of characteristic dimension difference that obtains and corresponding process factor thereof; According to described characteristic dimension difference, and the linear relationship of described characteristic dimension difference and described process factor, the actual value of calculating process factor;
Calculate the desired value of process factor and the difference of actual value, when actual value greater than desired value, desired value is deducted described difference as the new desired value of process factor; When actual value less than desired value, desired value is added the above difference as the new desired value of process factor;
Utilize the desired value of described new process factor that the semiconductor wafer that the n sheet has photoresist layer is carried out photoetching.
2. the photoetching method of controlling features size as claimed in claim 1 is characterized in that, the light source of described exposure adopts the mode of ring illumination.
3. the photoetching method of controlling features size as claimed in claim 2 is characterized in that, described process factor is the external process factor or the internal process factor.
4. as the photoetching method of any described controlling features size of claim 1 to 3, it is characterized in that the mask pattern of each described characteristic dimension is corresponding to an opening figure on the mask, the method for described exposure is the reckling in the described opening figure of alignment.
5. the etching system of a controlling features size is characterized in that, comprises photoetching base station, characteristic dimension measurement mechanism, deviation calculation device, process factor calculation element and feedback assembly, wherein,
The photoetching base station comprises exposure system and developing apparatus, and described exposure system is used to utilize the process factor of desired value that the semiconductor wafer with photoresist layer is exposed;
Described developing apparatus is used for the semiconductor wafer after the exposure system exposure is developed, and forms the mask pattern of at least two kinds of different characteristic sizes in the photoresist layer on the described semiconductor wafer of each sheet;
The characteristic dimension measurement mechanism is used to measure the characteristic dimension of the mask pattern of any two kinds of described different characteristic sizes that obtain after the photoetching of photoetching base station;
The deviation calculation device is used for the characteristic dimension difference of the mask pattern of any two kinds of described different characteristic sizes that the calculated characteristics dimension measuring device measures;
The process factor calculation element is used for according to described characteristic dimension difference, and the linear relationship of described characteristic dimension difference and described process factor is calculated the actual value of process factor;
Feedback assembly is used for the described actual value of comparison process factor and the magnitude relationship of described desired value, and determine the value that the desired value of process factor should be adjusted to according to described magnitude relationship, and the value that should adjust to feeds back to the exposure system of photoetching base station as new desired value.
6. the etching system of controlling features size as claimed in claim 5 is characterized in that, the light source of described exposure system is a ring illumination.
7. the etching system of controlling features size as claimed in claim 6 is characterized in that, described process factor is the external process factor or the internal process factor.
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| CN2008102252270A CN101727014B (en) | 2008-10-28 | 2008-10-28 | Photoetching method for controlling characteristic dimension and photoetching system thereof |
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| CN101727014B true CN101727014B (en) | 2011-11-30 |
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| CN102540740A (en) * | 2010-12-22 | 2012-07-04 | 无锡华润上华半导体有限公司 | Photoetching method and energy feedback system |
| CN102427045B (en) * | 2011-11-02 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | Original position moisture-generation process real-time detection method |
| CN103681393B (en) * | 2012-09-18 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Lithographic method |
| CN104037072B (en) * | 2014-06-12 | 2017-07-25 | 上海华力微电子有限公司 | The optimization method of ion implanting layer pattern feature sizes |
| CN112331576A (en) * | 2014-10-03 | 2021-02-05 | 科磊股份有限公司 | Validating metrology targets and their design |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1285109C (en) * | 2000-07-25 | 2006-11-15 | 先进微装置公司 | Method and apparatus for performing final critical dimension control |
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| CN1285109C (en) * | 2000-07-25 | 2006-11-15 | 先进微装置公司 | Method and apparatus for performing final critical dimension control |
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