CN103681393B - Lithographic method - Google Patents

Lithographic method Download PDF

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Publication number
CN103681393B
CN103681393B CN201210348144.7A CN201210348144A CN103681393B CN 103681393 B CN103681393 B CN 103681393B CN 201210348144 A CN201210348144 A CN 201210348144A CN 103681393 B CN103681393 B CN 103681393B
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etching
substrate
etched features
live width
sub
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CN103681393A (en
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黄怡
周俊卿
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A kind of lithographic method, comprising: provide a batch substrate, and substrate surface is formed with mask layer and has litho pattern photoresist layer; N-1 substrate is etched, forms etched features; Measure the live width of etched features in any M substrate in a described N-1 substrate, determine the first etching parameters according to the mean value of etched features live width and the difference of target size in M substrate; Measure the bottom live width of litho pattern on N number of substrate surface photoresist layer, the difference according to itself and target size determines the second etching parameters; Determine that the N number of substrate of etching is to form the etching condition needed for etched features according to the first etching parameters and the second etching; Be mask with N number of substrate surface photoresist layer, adopt the etching condition needed for the N number of substrate of etching to etch the mask layer of N number of substrate surface and substrate, form etched features.Lithographic method of the present invention accurately can control size and the pattern of etched features, reduces the difference of etched features on batch substrate.

Description

Lithographic method
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of lithographic method.
Background technology
Super large rule touch integrated circuit (VeryLargeScaleIntegratedCircuit, VLSI) interconnection capability usually needing the metal level of more than one deck to provide enough, the interconnection of this multiple layer metal interlayer and the connection between device active region and external circuitry are realized by the through hole of filled conductive material, and for ensureing the stability of devices function, require nothing electrical connection between through hole, make to become extremely important to the strict control of via etch process.
Existing technique forms through hole and mainly comprises the steps: to provide substrate, forms mask layer and photoresist layer successively from the bottom to top at substrate surface; By the graphical described photoresist layer of exposure imaging technique, photoresist layer forms litho pattern; To be formed with the photoresist layer of litho pattern for mask, mask layer and substrate are etched, form through hole.Wherein, described mask layer is for improving the quality that is formed at litho pattern in photoresist layer or as the hard mask etched substrate, improving the quality being formed at through hole in substrate.
Identical with target size in order to make to be formed at the actual size of through hole in substrate, (ADI is checked after will developing after exposure imaging technique, AfterDevelopInspection), obtain the live width being formed at litho pattern on photoresist layer, and the live width of litho pattern and target size are compared, determine the etching condition that substrate is etched; To carry out after the etch process etching rear inspection (AEI, AfterEtchInspection), obtain the live width of through hole in substrate, and the live width of through hole and target size are compared, judge whether the through hole formed meets the requirements.
The live width of the litho pattern obtained in existing technique typically refers to the middle part live width of litho pattern, and is that mask etches mask layer and substrate with photoresist layer, form through hole top live width be determined by the bottom live width of litho pattern.When the top live width of litho pattern, middle part live width and bottom live width are inconsistent, when the middle part live width of each through hole is identical, the bottom live width of its correspondence might not be identical, make the top live width of formed through hole different, cause the live width of formed through hole bigger than normal or less than normal, and then cause being positioned at the connector that to need below through hole to be covered by substrate or interconnection line exposes, or the connector that need expose or interconnection line cannot come out, to form the rate of finished products of semiconductor device low, unstable properties.
Summary of the invention
The problem that the present invention solves is to provide a kind of lithographic method, improves the control to etching technics, accurately control form size and the pattern of etched features, reduce the difference of etched features on same batch of substrate.
For solving the problem, the invention provides a kind of lithographic method, comprising:
There is provided a batch substrate, each substrate surface is formed with mask layer and photoresist layer from the bottom to top successively, and described photoresist layer has litho pattern;
The mask layer on N-1 substrate and surface thereof is etched, forms etched features;
Measure the live width of etched features in any M substrate in a described N-1 substrate, obtain the mean value of etched features live width in a described M substrate, and itself and target size are compared, determine the first etching parameters needed for the N number of substrate of etching according to difference;
Measure the bottom live width of litho pattern on N number of substrate surface photoresist layer, and itself and target size are compared, determine the second etching parameters needed for the N number of substrate of etching according to difference;
The first etching parameters needed for the N number of substrate of etching and the second etching parameters are carried out weight addition, determines the adjustment amount of the etching condition to N-1 substrate, obtain the N number of substrate of etching to form the etching condition needed for etched features;
Be mask with the photoresist layer of N number of substrate surface, adopt the mask layer of etching condition to N number of substrate and surface thereof needed for the N number of substrate of etching to etch, form etched features;
Wherein, N be greater than or equal to 2 positive integer, M be greater than or equal to 1 positive integer, and M is less than or equal to N.
Compared with prior art, technical solution of the present invention has the following advantages:
When etching N number of substrate, consider simultaneously litho pattern in N number of substrate surface photoresist layer bottom live width and in any M substrate of front etching the live width of etched features, determine the adjustment amount of the etching condition to N-1 substrate, obtain the etching condition of the N number of substrate of etching, and then with obtained etching condition, N number of substrate is etched, form etched features; By the continuous adjustment to etching condition, make to be formed at the live width of etched features in substrate and move closer to target size, the size being formed at etched features in substrate avoiding the factor such as unstable properties and etching condition because of litho pattern varying topography, etching apparatus on substrate each in batch substrate to cause or pattern there are differences, improve the control to etching technics, and then improve etching precision.
Further, when etching N number of substrate, first etched features in any M substrate of front etching is divided into first kind etched features and Equations of The Second Kind etched features in position in the substrate according to it, and to be measured by optical critical dimension and critical size scanning electron microscopy measurement two kinds of methods measure the top live width of first kind etched features and the top live width of Equations of The Second Kind etched features and bottom live width respectively, and then determine first etching parameters of etching the needed for N number of substrate; Again the bottom live width of litho pattern in N number of substrate surface photoresist layer is measured, and itself and target size are compared, determine second etching parameters of etching needed for N number of substrate; Finally the first etching parameters and the second etching parameters are carried out weight addition, determine the adjustment amount of the etching condition to N-1 substrate, obtain the etching condition of the N number of substrate of etching.When determining the adjustment amount to the etching condition of N-1 substrate by the first etching parameters and the second etching parameters, can adjust simultaneously be formed with the top live width of etched features in N number of substrate and bottom live width, reach adjustment form the object of etched features pattern, improve the degree of control to etching technics.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of a lithographic method of the present invention execution mode;
Fig. 2 is the substrate flow schematic diagram in lithographic method of the present invention embodiment;
Fig. 3 and Fig. 4 is the graph of a relation of the flow of each etching gas in the first etching condition and the opening live width variable quantity of mask layer split shed;
Fig. 5 is the graph of a relation of etched features top live width variable quantity and bottom live width variable quantity in the power of each frequency power source in the second etching condition and substrate.
Embodiment
Just as described in the background section, existing lithographic method is when forming etched features, after exposure imaging technique to photoresist layer in litho pattern develop after check, obtain the middle part live width of litho pattern, and middle part live width and target size are compared, adjust the etching condition etching to be formed etched features to substrate.But, because the top live width of etched features is determined by the bottom live width of litho pattern, and for the equal litho pattern of middle part live width, bottom it, live width might not be equal, cause the top live width of formed etched features not necessarily equal, and then to cause on same batch of substrate form etched features top live width differ greatly, to form the rate of finished products of semiconductor device low, unstable properties.
For above-mentioned defect, inventor provide a kind of lithographic method, before N number of substrate is etched, the bottom live width of litho pattern on the live width of the etched features of M substrate any in N-1 substrate of front etching and N number of substrate surface photoresist layer is compared with target size respectively, determine first etching parameters of etching needed for N number of substrate and the second etching parameters, and then determine the adjustment amount of the etching condition to N-1 substrate, obtain the N number of substrate of etching to form the etching condition needed for etched features, then with photoresist layer on N number of substrate for mask, adopt the etching condition of etching the needed for N number of substrate, etch along the mask layer of litho pattern to N number of substrate and surface thereof, form etched features.
Lithographic method of the present invention is according to litho pattern pattern on the pattern of the etched features of M substrate any in N-1 substrate of front etching and N number of substrate, the etching condition of N-1 substrate is adjusted, then etching is carried out to N number of substrate and form etched features, the live width making to be formed at etched features in substrate is consistent with target size gradually, improve the control to etching technics, and then improve etching precision.
With reference to figure 1, the schematic flow sheet of a lithographic method of the present invention execution mode, comprising:
Step S1, provides a batch substrate, and each substrate surface is formed with mask layer and photoresist layer from the bottom to top successively, and described photoresist layer has litho pattern;
Step S2, etches the mask layer on N-1 substrate and surface thereof, forms etched features;
Step S3, measure the live width of etched features in any M substrate in a described N-1 substrate, obtain the mean value of etched features live width in a described M substrate, and itself and target size are compared, determine the first etching parameters needed for the N number of substrate of etching according to difference;
Step S4, measures the bottom live width of litho pattern on N number of substrate surface photoresist layer, and itself and target size is compared, determine the second etching parameters needed for the N number of substrate of etching according to difference;
Step S5, carries out weight addition by the first etching parameters needed for the N number of substrate of etching and the second etching parameters, determines the adjustment amount of the etching condition to N-1 substrate, obtains the N number of substrate of etching to form the etching condition needed for etched features;
Step S6, is mask with the photoresist layer of N number of substrate surface, adopts the mask layer of etching condition to N number of substrate and surface thereof needed for the N number of substrate of etching to etch, form etched features.
With reference to figure 2, be the substrate flow schematic diagram in lithographic method of the present invention embodiment, below in conjunction with Fig. 2, lithographic method of the present invention be described in detail.
Before carrying out etching technics, first provide a batch substrate, and form mask layer and photoresist layer successively from the bottom to top at each substrate surface; Again described batch of substrate is delivered to lithographic equipment 100 place, in the photoresist layer of each substrate surface, form litho pattern successively.
In the present embodiment, described batch of substrate refers to, sometime in section, be carried out the multiple substrates processed by lithographic equipment, etching apparatus or measuring equipment; Because lithographic equipment, etching apparatus or the measuring equipment performance of itself in section is sometime more or less the same, therefore, the pattern being formed at litho pattern on same batch of substrate or etched features is more or less the same; By measuring equipment to substrate each in batch substrate carry out measuring to obtain the departure of measurement result little.
In the present embodiment, the material of described mask layer can be bottom antireflective coating (bottomanti-reflectivecoating, be called for short BARC), reflect at substrate surface to prevent the laser in lithographic equipment in a lithographic process, photoresist layer outside litho pattern is exposed, improve form the accuracy of litho pattern.
In other embodiments, the material of described mask layer can also be the materials such as silica, silicon nitride or silicon oxynitride.Before substrate is etched, first litho pattern in photoresist layer is transferred on mask layer, in mask layer, forms the opening corresponding with etched features in substrate, then with photoresist layer and mask layer for mask, substrate is etched, formation etched features.Described mask layer, as hard mask when etching substrate, makes the etched features pattern that is formed in substrate better.
After litho pattern is formed on batch substrate, start the etching technics of this batch of substrate.
It should be noted that, due to the unsteadiness of lithographic equipment 100 or photoetching process, cause litho pattern possibility on each substrate inconsistent, if do not check it and directly etch substrate according to predetermined etching condition, the etched features obtained after the inconsistent meeting of litho pattern directly causes etching inconsistent.Therefore, before each substrate is etched, need the litho pattern on each substrate be measured.The above-mentioned method measured litho pattern on substrate is that optical critical dimension is measured.Because the follow-up top live width being formed at etched features in substrate is only relevant with the bottom live width of litho pattern on substrate, therefore in the present embodiment, only need to measure the bottom live width of litho pattern on each substrate.
First the lithographic method of the 1st substrate in batch substrate is described.
In the present embodiment, described batch of substrate comprises control wafer, and it is as the substrate that in this batch of substrate, first is carried out etching (or being called the 1st substrate).Due to less than the etched features formed in front etching as a reference, predetermined etching condition can only be adjusted, as the etching condition of its reality according to litho pattern in its photoresist layer.Usual control wafer, only for understanding the state of etching apparatus 300, does not carry out follow-up device making technics to it.
Concrete, form litho pattern in described control wafer photomask surface glue-line after, first control wafer is delivered to rear checkout facility 200 place of development, measure the bottom live width of litho pattern in control wafer, and itself and target size are compared, adjust predetermined etching condition according to difference, obtain the etching condition of etching needed for control wafer; Again described control wafer is delivered to etching apparatus 300, with the photoresist layer on control wafer surface for mask, successively the mask layer on control wafer surface and control wafer are etched along litho pattern, in control wafer, form etched features.
It should be noted that: in the ideal case, formed etched features top live width, middle part live width should be consistent with the bottom live width of litho pattern in the opening live width of mask layer split shed and photoresist layer with bottom live width.Therefore, the top live width of the bottom live width of litho pattern, the opening live width of opening and etched features, middle part live width are all identical with the target size of bottom live width.
Also it should be noted that: because each substrate is different from the material of its mask layer on the surface, required etching condition, lithographic method are also different.Substrate is being etched, when forming etched features, is comprising the steps: further
With the photoresist layer of substrate surface for mask, along litho pattern, the first etching is carried out to mask layer, to exposing substrate;
With the photoresist layer of substrate surface for mask, along litho pattern, the second etching is carried out to substrate, form etched features.
Accordingly, when carrying out the first etching, the etching condition of etching apparatus 300 is the first etching condition; When carrying out the second etching, the etching condition of etching apparatus 300 is the second etching condition.
Form etched features in control wafer after, etching technics is carried out to the 2nd substrate.
First, control wafer is delivered in the rear checkout facility 400 of etching, to measure the live width of etched features in control wafer.
In the present embodiment, after described etching, checkout facility 400 comprises optical critical dimension measurement (OpticalCriticalDimension, referred to as OCD) board and critical size scanning electron microscopy (CriticalDimensionScanningElectronicMicroscope, referred to as CDSEM).Wherein, the measuring principle of OCD board is: on substrate to be measured, project a branch of polarised light, and described polarised light forms reverberation after reflection, obtains one group of spectrum line, comprise the information of measure portion in this spectrum line from reverberation.For ensureing the precision that OCD board is measured, on substrate, the density of etching pattern should be comparatively intensive.And CDSEM operation principle is: the electron beam irradiated from electron gun is converged by collector lens, arrive on the pattern of determination object through perforate (aperture), detector is utilized to catch the secondary electron of releasing and be transformed to the signal of telecommunication, obtain two dimensional image, the high-precision critical size measuring determination object based on two-dimensional image information.For ensureing the certainty of measurement of CDSEM, on substrate, the density of etching pattern should be comparatively loose.
Therefore, when checking the live width of formed etched features, in order to ensure the precision measured, substrate is divided into device compact district and device puffs according to the dense degree of etched features in substrate.Wherein, described device compact district can refer to that the ratio of spacing and etched features target size between adjacent etched figure in substrate is less than or equal to the region of 10:1, and described device puffs can refer to that the ratio of spacing and etched features target size between adjacent etched figure in substrate is greater than the region of 10:1.Accordingly, the etched features be formed in substrate comprises the first kind etched features being positioned at device compact district and the Equations of The Second Kind etched features being positioned at device puffs, and described first kind etched features is identical with the shape of Equations of The Second Kind etched features.
When the live width by etching etched features in rear checkout facility 400 pairs of substrates is measured, by OCD board, the top live width of first kind etched features in substrate is measured, by CDSEM, the top live width of Equations of The Second Kind etched features in substrate and bottom live width are measured.
The live width of etched features is measured in control wafer, after obtaining in control wafer the top live width of first kind etched features and the top live width of the second etched features and bottom live width, it is compared with target size respectively, the first sub-etching parameters needed for etching the 2nd substrate is determined according to the top live width of first kind etched features and the difference of target live width, the second sub-etching parameters needed for etching the 2nd substrate is determined according to the top live width of Equations of The Second Kind etched features and the difference of target size, the 3rd sub-etching parameters needed for etching the 2nd substrate is determined according to the bottom live width of Equations of The Second Kind etched features and the difference of target size, the first sub-etching parameters of described etching the 2nd needed for substrate, second sub-etching parameters and the 3rd sub-etching parameters form first etching parameters of etching the 2nd needed for substrate.
In the present embodiment, described first sub-etching parameters and the second sub-etching parameters include the power ratio of each frequency power source in the flow-rate ratio of each gas in etch period, etching gas flow, etching gas, the pressure of chamber, etching power or etching power supply.
Described 3rd sub-etching parameters comprises the power ratio of each frequency power source in etching power or etching power supply.
After the wire width measuring completing etched features in control wafer, then, 2nd substrate is delivered to the rear checkout facility 200 of development, the bottom live width of litho pattern on the 2nd substrate is measured by OCD board, and itself and target size are compared, determine the second etching parameters needed for etching the 2nd substrate according to difference.
In the present embodiment, described second etching parameters comprises the power ratio of each frequency power source in the flow-rate ratio of each gas in etch period, etching gas flow, etching gas, the pressure of chamber, etching power or etching power supply.
Again then, the first etching parameters needed for etching the 2nd substrate and the second etching parameters are carried out weight addition, determine the adjustment amount of the etching condition to control wafer (the 1st substrate), and adjust according to the etching condition of determined adjustment amount to etching apparatus 300, make the etching condition of the etching condition of etching apparatus 300 needed for etching the 2nd substrate.
In the present embodiment, due to the second etching condition when etching condition comprises the first etching condition of etching mask layer on substrate and etches substrate, accordingly, the adjustment amount of the etching condition of etching apparatus 300 is comprised the adjustment amount of the first etching condition and the adjustment amount to the second etching condition.
For the 2nd substrate, it can obtain according to following formula the adjustment amount of the first etching condition of control wafer:
T 2=T FF(1-λ OCD)+T FBλ OCD+ΔT
Wherein, T 2for the adjustment amount of the first etching condition to control wafer; T fFfor etching the second etching parameters needed for the 2nd substrate, T fBfor etching the first sub-etching parameters needed for the 2nd substrate; The second sub-etching parameters of Δ T needed for etching the 2nd substrate, the performance (model, service time etc.) of itself and the impact that etches the 2nd substrate first when adjusting the second etching condition of control wafer by the 3rd sub-etching parameters needed for etching the 2nd substrate and etching apparatus itself is relevant; λ oCDbe the first sub-etching parameters T fBweight, and λ oCDmeet 0.1≤λ oCD≤ 0.9.
Second etching condition of the 2nd substrate can obtain according to following formula:
P=P 1(1-λ CDSEM)+P 2λ CDSEM
Wherein, second etching condition of P needed for etching the 2nd substrate; P 1for the second etching condition needed for etching control wafer; P 2for the adjustment amount to the second etching condition needed for etching control wafer, and P 2=P fB, P fBfor etching the 3rd sub-etching parameters needed for the 2nd substrate; λ cDSEMfor the adjustment amount P to the second etching condition needed for etching control wafer 2weight, and 0.1≤λ cDSEM≤ 0.9.
Then, the adjustment amount T of the first etching condition to control wafer is utilized 2the first etching condition etched in etching apparatus 300 in control wafer needed for mask layer is adjusted to the first etching condition described in mask layer on etching the 2nd substrate, the second etching condition etched needed for control wafer is adjusted to the second etching condition P needed for etching the 2nd substrate in etching apparatus 300.
Finally, 2nd substrate is delivered to etching apparatus 300, with the 2nd substrate surface photoresist layer for mask, first with the first etching condition etched needed for the 2nd substrate, the first etching is carried out to the mask layer on the 2nd substrate, with the second etching condition etched needed for the 2nd substrate, the second etching is carried out to the 2nd substrate again, in the 2nd substrate, form etched features.
Form etched features in the 2nd substrate after, etch with to the lithographic method of the 2nd substrate successively to the 3rd substrate, the 4th substrate ... N number of substrate ... etch, until all form etched features in each substrate of described batch of substrate.
Below to etch N number of substrate, the lithographic method of other substrates in batch substrate (when N is the positive integer being greater than 2) is described further.
Before N number of substrate is etched, in N-1 substrate, form etched features.Although the etching condition of etching the needed for N number of substrate is by carrying out the etching condition of N-1 substrate adjusting acquisition in etching apparatus 300, in N-1 substrate, the pattern of etched features more can embody the state (namely in N-1 substrate, the pattern of etched features has more reference value for the etching of N number of substrate) of etching apparatus 300, but consider that etching apparatus 300 itself or etching technics may exist error, in order to avoid affecting the etching of N number of substrate because N-1 substrate etching technique makes a mistake, when determining the etching condition of N number of substrate, the pattern of etched features in the pattern of etched features and N-1 substrate in any M substrate in N-1 substrate before simultaneously considering, the etching condition of adjustment etching N-1 substrate.Wherein, M be more than or equal to 1 positive integer, and M is less than or equal to N.
Preferably, described M substrate selects N-M the substrate having carried out etching to N-1 substrate.This is because: in the present embodiment, by constantly adjusting acquisition to the etching condition of etched substrate at the etching condition of the substrate of rear etching, for N number of substrate, N-M substrate to the etching condition of N-1 substrate and N number of substrate etching condition closer to, in N-M substrate to N-1 substrate, the etching of pattern to N number of substrate of etched features has more reference value.
When etching N number of substrate, comprise the steps:
First, the top live width of first kind etched features in N-M substrate to a N-1 substrate M substrate is measured by the OCD board etched in rear checkout facility 400; Obtain the mean value of the first etched features top live width in M substrate again, and itself and target size are compared, obtain by the determined first sub-etching parameters of the top live width of first kind etched features in M substrate according to difference, and the top live width of first kind etched features in N-1 substrate is compared with target size, obtain by the determined first sub-etching parameters of the top live width of first kind etched features in N-1 substrate according to difference; Again by by the determined first sub-etching parameters of the top live width of first kind etched features in M substrate with carry out weight by the determined first sub-etching parameters of the top live width of first kind etched features in N-1 substrate and be added, obtain the first sub-etching parameters of etching the needed for N number of substrate.
In the present embodiment, the first sub-etching parameters of described etching needed for N number of substrate obtains according to following formula:
T FB=T L1λ 1+T L2λ 2
Wherein, T fBfor etching the first sub-etching parameters needed for N number of substrate, T l1for by the mean value of the top live width of first kind etched features in M substrate and the determined first sub-etching parameters of the difference of target size, T l2for by the top live width of first kind etched features in N-1 substrate and the determined first sub-etching parameters of the difference of target size; λ 1be the first sub-etching parameters T l1weight, λ 2be the first sub-etching parameters T l2weight, and λ 1and λ 2meet 0.3≤λ 1≤ 0.5,0.5≤λ 2≤ 0.7 and λ 1+ λ 2=1.
In the present embodiment, when obtaining the first sub-etching parameters needed for the N number of substrate of etching, consider the top live width of first kind etched features in the top live width of first kind etched features in N-M substrate to N-1 substrate and N-1 substrate respectively, make the first sub-etching parameters of the obtained N number of substrate of etching more accurate.
Then, top live width and the bottom live width of Equations of The Second Kind etched features in N-M substrate to N-1 substrate is measured by etching CDSEM in rear checkout facility 400, obtain the mean value of top live width and the mean value of bottom live width of Equations of The Second Kind etched features in M substrate, and it is compared with target size respectively, determine the second sub-etching parameters needed for the N number of substrate of etching and the 3rd sub-etching parameters according to difference.
It should be noted that, in the present embodiment, etch the second sub-etching parameters needed for N number of substrate except outside the Pass the mean value of top live width and the difference of target size with Equations of The Second Kind etched features in M substrate has, also relevant on factors such as the performances (model, service time etc.) of its first impact etched, etching apparatus itself with when being adjusted the second etching condition of N number of substrate by the 3rd sub-etching parameters needed for the N number of substrate of etching.
Again then, after N number of substrate being delivered to development, checkout facility 200(is as OCD board), measure the bottom live width of litho pattern on N number of substrate surface photoresist layer, and itself and target size are compared, determine the second etching parameters needed for the N number of substrate of etching according to difference.
Then, the first sub-etching parameters, the second sub-etching parameters and the second etching parameters needed for the N number of substrate of etching are carried out weight addition, determine the adjustment amount of the first etching condition to N-1 substrate, and the first etching condition in etching apparatus 300 is adjusted to the first etching condition needed for the N number of substrate of etching by the first etching condition etched needed for N-1 substrate; And, the 3rd sub-etching parameters needed for the N number of substrate of etching determines the second etching condition needed for the N number of substrate of etching, and the second etching condition in etching apparatus 300 is adjusted to the second etching condition needed for the N number of substrate of etching by the second etching condition etched needed for N-1 substrate.
Wherein, the adjustment amount of the first etching condition of N-1 substrate is obtained according to following formula:
T N=T FF(1-λ OCD)+T FBλ OCD+ΔT
Wherein, T nfor carrying out the adjustment amount of the first etching condition of the first etching to N-1 substrate; T fFfor etching the second etching parameters needed for N number of substrate; T fBfor etching the first sub-etching parameters needed for N number of substrate; The second sub-etching parameters of Δ T needed for the N number of substrate of etching, it is relevant with the performance (model, service time etc.) of the impact etched N number of substrate first when being adjusted the second etching condition of N-1 substrate by the 3rd sub-etching parameters needed for the N number of substrate of etching and etching apparatus itself; λ oCDbe the weight of the first sub-etching parameters, and λ oCDmeet 0.1≤λ oCD≤ 0.9.
Etch the second etching condition needed for N number of substrate to obtain according to following formula:
P=P N-1(1-λ CDSEM)+P Nλ CDSEM
Wherein, second etching condition of P needed for the N number of substrate of etching; P n-1for etching the second etching condition needed for N-1 substrate; P nfor the adjustment amount to the second etching condition needed for etching N-1 substrate, and P n=P fB, P fBfor etching the 3rd sub-etching parameters needed for N number of substrate; λ cDSEMfor the adjustment amount P to the second etching condition needed for etching N-1 substrate nweight, and 0.1≤λ cDSEM≤ 0.9.
Finally, N number of substrate is delivered to etching apparatus 300 in Fig. 2, to etch the first etching condition needed for N number of substrate and the second etching condition carries out the first etching and the second etching to the mask layer on N number of substrate and N number of substrate respectively, in N number of substrate, form etched features.
It should be noted that, after N number of substrate etching completes, first can determine that whether N number of substrate is last substrate in this batch of substrate.As last substrate that N number of substrate is in this batch of substrate, then carried out the measurement of etched features live width without the need to delivering to the rear checkout facility 400 of etching; As last substrate that N number of substrate is not in this batch of substrate, then after needing to be delivered to etching, checkout facility 400 carries out the measurement of etched features live width, repeats the step of the N number of substrate of above-mentioned etching, until this batch of substrate has all etched.
Fig. 3 and Fig. 4 is the graph of a relation of etched features top live width variable quantity in the flow of each gas in etching gas and substrate; Fig. 5 is the power of each frequency power source and the graph of a relation of etched features top live width variable quantity and bottom live width variable quantity in etching power supply.
As shown in Figure 3, the material of described mask layer is BARC, is passing through CF 4and CHF 3mist when the first etching is carried out to mask layer, as CF in etching gas 4with CHF 3flow be respectively 150 (sccm)/0 (sccm), 130 (sccm)/20 (sccm), 110 (sccm)/40 (sccm) and 90 (sccm)/60 (sccm) time, the opening live width variable quantity of corresponding mask layer split shed is 50.4nm, 48.8nm, 41.5nm and 36.1nm.That is, CF in etching gas 4with CHF 3flow and opening live width variable quantity meet the linear relationship of Fig. 3 cathetus 301.
As shown in Figure 4, the material of described mask layer is silica, silicon nitride or silicon oxynitride, is passing through CF 4and CHF 3mist when the first etching is carried out to mask layer, as CF in etching gas 4with CHF 3flow be 20 (sccm)/100 (sccm), 40 (sccm)/80 (sccm) and 60 (sccm)/60 (sccm) time, the opening live width variable quantity of corresponding mask layer split shed is 48.8nm, 51.1nm and 54.3nm.That is, CF in etching gas 4with CHF 3flow and opening live width variable quantity meet the linear relationship of Fig. 4 cathetus 401.
From Fig. 3 and Fig. 4, can by regulating CF in etching gas 4with CHF 3flow regulate the removal amount of mask layer in the first etching, and then regulate the opening live width being formed at mask layer split shed, with reach when carrying out the second etching to substrate adjustment the object of top live width of formation etched features.
As shown in Figure 5, when carrying out the second etching to substrate, when the power of 2MHz and 60MHz two kinds of frequency power source be 0 (w)/200 (w), 100 (w)/100 (w) and 200 (w)/0 (w) time, in corresponding substrate, the variable quantity of the top live width of etched features is 28.8nm, 35.0nm and 40.8nm, and in corresponding substrate, the variable quantity of the bottom live width of etched features is 48.1nm, 47.4nm and 46.7nm.Namely, in the power of 2MHz and 60MHz two kinds of frequency power source and substrate, the variable quantity of the top live width of etched features meets the linear relationship of straight line 501, and in the power of 2MHz and 60MHz two kinds of frequency power source and substrate, the variable quantity of the bottom live width of etched features meets the linear relationship of straight line 503.Carrying out in the second etching process, due to comparatively difficult to the etching of etched features top substrate to the etching of etched features base substrate, by the power of adjustment 2MHz and 60MHz two kinds of frequency power source, can when live width impact in etched features top be less on substrate, increase its bottom live width, thus make the bottom live width of formed etched features consistent with top live width, improve the pattern of formed etched features.
In the present embodiment, described etched features can be through hole, groove or other semiconductor device graph, and the present invention does not limit this.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (13)

1. a lithographic method, is characterized in that, comprising:
There is provided a batch substrate, each substrate surface is formed with mask layer and photoresist layer from the bottom to top successively, and described photoresist layer has litho pattern;
The mask layer on N-1 substrate and surface thereof is etched, forms etched features;
Measure the live width of etched features in any M substrate in a described N-1 substrate, obtain the mean value of etched features live width in a described M substrate, and itself and target size are compared, determine the first etching parameters needed for the N number of substrate of etching according to difference;
Measure the bottom live width of litho pattern on N number of substrate surface photoresist layer, and itself and target size are compared, determine the second etching parameters needed for the N number of substrate of etching according to difference;
The first etching parameters needed for the N number of substrate of etching and the second etching parameters are carried out weight addition, determines the adjustment amount of the etching condition to N-1 substrate, obtain the N number of substrate of etching to form the etching condition needed for etched features;
Be mask with the photoresist layer of N number of substrate surface, adopt the mask layer of etching condition to N number of substrate and surface thereof needed for the N number of substrate of etching to etch, form etched features;
Wherein, N be greater than or equal to 2 positive integer, M be greater than or equal to 1 positive integer, and M is less than or equal to N-1.
2. lithographic method as claimed in claim 1, it is characterized in that, described batch of substrate comprises control wafer, when etching a batch substrate, first etches control wafer, and then etches other substrates in batch substrate except control wafer; Etch control wafer, the step forming etched features comprises:
Measure the bottom live width of litho pattern on control wafer photomask surface glue-line, and itself and target size are compared, adjust predetermined etching condition according to difference, obtain the etching condition of etching needed for control wafer;
Be mask with the photoresist layer on control wafer surface, adopt the mask layer of etching condition to control wafer and surface thereof needed for etching control wafer to etch, form etched features.
3. lithographic method as claimed in claim 1, it is characterized in that, described substrate comprises device compact district and device puffs, and the etched features being positioned at device compact district is first kind etched features, and the etched features being positioned at device puffs is Equations of The Second Kind etched features.
4. lithographic method as claimed in claim 3, it is characterized in that, described first etching parameters comprises the first sub-etching parameters, the second sub-etching parameters and the 3rd sub-etching parameters, determines that the step of first etching parameters of etching the needed for N number of substrate comprises:
Measure the top live width of first kind etched features in a described M substrate, obtain the mean value of the top live width of first kind etched features in a described M substrate, and itself and target size are compared, determine the first sub-etching parameters needed for the N number of substrate of etching according to difference;
Measure top live width and the bottom live width of Equations of The Second Kind etched features in a described M substrate, obtain the mean value of the top live width of Equations of The Second Kind etched features in a described M substrate and the mean value of bottom live width, and compare with target size respectively, determine the second sub-etching parameters needed for the N number of substrate of etching and the 3rd sub-etching parameters respectively according to difference.
5. lithographic method as claimed in claim 4, it is characterized in that, described first sub-etching parameters, the second sub-etching parameters and the second etching parameters include the power ratio of each frequency power source in the flow-rate ratio of each gas in etch period, etching gas flow, etching gas, the pressure of chamber, etching power or etching power supply.
6. lithographic method as claimed in claim 4, is characterized in that, described 3rd sub-etching parameters comprises the power ratio of each frequency power source in etching power or etching power supply.
7. lithographic method as claimed in claim 4, is characterized in that, the method measuring the top live width of first kind etched features in a described M substrate is that optical critical dimension is measured.
8. lithographic method as claimed in claim 4, is characterized in that, before measuring, in M substrate, the top live width of Equations of The Second Kind etched features and the method for bottom live width are critical size scanning electron microscopy measurement.
9. lithographic method as claimed in claim 4, is characterized in that, etch the mask layer on N number of substrate and surface thereof, and the step forming etched features comprises:
With the photoresist layer of N number of substrate surface for mask, carry out the first etching, to exposing N number of substrate along the mask layer of litho pattern to N number of substrate surface;
With the photoresist layer of N number of substrate surface for mask, along litho pattern, the second etching is carried out to N number of substrate, form etched features.
10. lithographic method as claimed in claim 9, is characterized in that, obtains the N number of substrate of etching and comprises with the step forming the etching condition needed for etched features:
The first sub-etching parameters, the second sub-etching parameters and the second etching parameters needed for the N number of substrate of etching are carried out weight addition, determine the adjustment amount of the first etching condition N-1 substrate being carried out to the first etching, obtain first etching condition needed for mask layer of the N number of substrate surface of etching;
According to the 3rd sub-etching parameters of N number of substrate, determine the adjustment amount of the second etching condition N-1 substrate being carried out to the second etching, obtain second etching condition of etching the needed for N number of substrate.
11. lithographic methods as claimed in claim 10, it is characterized in that, the first sub-etching parameters, the second sub-etching parameters and the second etching parameters needed for the N number of substrate of etching are carried out weight addition, determine that adjustment amount N-1 substrate being carried out to the first etching condition of the first etching obtains according to following formula:
T N=T FF(1-λ OCD)+T FBλ OCD+ΔT,
Wherein, T nfor carrying out the adjustment amount of the first etching condition of the first etching to N-1 substrate; T fFit is the second etching parameters; T fBit is the first sub-etching parameters; Δ T is the second sub-etching parameters; λ oCDbe the weight of the first sub-etching parameters, and λ oCDmeet 0.1≤λ oCD≤ 0.9.
12. lithographic methods as claimed in claim 11, is characterized in that, described first sub-etching parameters T fBobtain according to following formula:
T FB=T L1λ 1+T L2λ 2
Wherein, T l1for by the mean value of the top live width of first kind etched features in N-M substrate to N-1 substrate and the determined first sub-etching parameters of the difference of target size, T l2for by the top live width of first kind etched features in N-1 substrate and the determined first sub-etching parameters of the difference of target size; λ 1be the first sub-etching parameters T l1weight, λ 2be the first sub-etching parameters T l2weight, and λ 1and λ 2meet 0.3≤λ 1≤ 0.5,0.5≤λ 2≤ 0.7 and λ 1+ λ 2=1.
13. lithographic methods as claimed in claim 10, is characterized in that, needed for the N number of substrate of etching the
Two etching conditions obtain according to following formula:
P=P N-1(1-λ CDSEM)+P Nλ CDSEM
Wherein, second etching condition of P needed for the N number of substrate of etching; P n-1for etching the second etching condition needed for N-1 substrate; P nfor the adjustment amount to the second etching condition needed for etching N-1 substrate, and P n=P fB, P fBfor etching the 3rd sub-etching parameters needed for N number of substrate; λ cDSEMfor the adjustment amount P to the second etching condition needed for etching N-1 substrate nweight, and 0.1≤λ cDSEM≤ 0.9.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101599433A (en) * 2008-06-03 2009-12-09 中芯国际集成电路制造(北京)有限公司 Semiconductor etching method and etching system
CN101727014A (en) * 2008-10-28 2010-06-09 中芯国际集成电路制造(北京)有限公司 Photoetching method for controlling characteristic dimension and photoetching system thereof
CN102237298A (en) * 2010-04-27 2011-11-09 中芯国际集成电路制造(上海)有限公司 Method for improving stability of through hole etching

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* Cited by examiner, † Cited by third party
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JPH03107845A (en) * 1989-09-21 1991-05-08 Fujitsu Ltd Method for inspecting resist pattern
JP4455936B2 (en) * 2003-07-09 2010-04-21 富士通マイクロエレクトロニクス株式会社 Semiconductor device manufacturing method and etching system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101599433A (en) * 2008-06-03 2009-12-09 中芯国际集成电路制造(北京)有限公司 Semiconductor etching method and etching system
CN101727014A (en) * 2008-10-28 2010-06-09 中芯国际集成电路制造(北京)有限公司 Photoetching method for controlling characteristic dimension and photoetching system thereof
CN102237298A (en) * 2010-04-27 2011-11-09 中芯国际集成电路制造(上海)有限公司 Method for improving stability of through hole etching

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