CN101706551A - Testing circuit for forecasting failure of back bias voltage unstability of integrated circuit - Google Patents
Testing circuit for forecasting failure of back bias voltage unstability of integrated circuit Download PDFInfo
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- CN101706551A CN101706551A CN200910218654A CN200910218654A CN101706551A CN 101706551 A CN101706551 A CN 101706551A CN 200910218654 A CN200910218654 A CN 200910218654A CN 200910218654 A CN200910218654 A CN 200910218654A CN 101706551 A CN101706551 A CN 101706551A
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Abstract
The invention discloses a testing circuit for forecasting a failure of back bias voltage unstability of an integrated circuit, which mainly comprises a measuring tube (3), a constant current bias circuit, a voltage reference circuit, a rotary comparator circuit, a two-way switch circuit and a switching tube (12), wherein the measuring tube (3) is used for measuring threshold voltage shift; the constant current biasing circuit provides constant current bias for the measuring tube (3); the voltage reference circuit provides reference voltage for the rotary comparator; and the two-way switch circuit makes the measuring tube (3) switched between degradation and testing. In the degradation period, the switching tube (12) switches off the rotary comparator circuit, the constant current bias circuit and the voltage reference circuit to reduce power consumption; in the testing period, the switching tube (12) switches on the rotary comparator circuit, the constant current bias circuit and the voltage reference circuit, and when the source-drain voltage of the measuring tube is greater than the reference voltage, the rotary comparator outputs high level so as to forecast that the integrated circuit is about to fail. The testing circuit can be used for forecasting the failure of back bias voltage unstability effect.
Description
Technical field
The invention belongs to the electronic circuit technology field, relate to negative bias instability inefficacy real-time prediction circuit, can be used for the test and the life forecast of big/ultra-large above integrated circuit.
Background technology
At present, the reliability testing technology of integrated circuit obtains application and development more and more widely, as fields such as aerospace electron, aviation electronics, automotive electronics.Along with development of integrated circuits, the SOC (system on a chip) SOC that comprises holonomic systems such as central processing unit, storer and peripheral circuit is very helpful for the electromagnetic interference (EMI) of elevator system performance, minimizing system energy consumption, reduction system and the integrated level of raising system, it has not only complied with the compact trend of product, and efficient integrated performance is being arranged, so just substituting the main solution of integrated circuit and becoming the inexorable trend that current microelectronic chip develops.Yet this has brought difficulty also for the failure testing of integrated circuit.Because SOC is baroque integrated circuit, embedded character and complicated relation make SOC can not carry out fault detect, failure prediction and life prediction as traditional integrated circuit.
The integrated level and the power density of modern integrated circuits constantly increase, and the temperature of integrated circuit is very high during circuit working.Be in PMOSFET under the high temperature when negative bias stress appears in grid, the problem that threshold voltage shift can take place, leakage current reduces and mutual conductance is degenerated, thus influence the function of circuit even cause ic failure.Problem of Failure at this negative bias instability causes does not also have the real-time prediction technology at this failure mode at present.
Summary of the invention
The objective of the invention is to the Problem of Failure that under the negative bias instability effect, takes place at integrated circuit, the test circuit that provides real-time prediction integrated circuit negative bias instability to lose efficacy carries out real-time testing and carries out fault alarm the inefficacy that integrated circuit causes under negative bias instability stress with realization.
The object of the present invention is achieved like this:
One. know-why
During integrated circuit work, the threshold voltage that is in the PMOSFET under the negative bias instability stress can drift about, thereby the present invention adopts monitoring PMOSFET variations in threshold voltage to come the integrated circuit under the influence of negative bias instability effect is carried out Failure Alarm.In the test circuit of the present invention, the grid of the measuring tube PMOSFET that will be used to test and drain electrode short circuit, and the source end that adopts steady current to be carried in PMOSFET setovers to it, makes it be in state of saturation.When this PMOSFET is in negative bias instability stress following time, the absolute value of its threshold voltage constantly increases.At this moment, the voltage between leak in this PMOSFET source also constantly increases, and the variation of PMOSFET drain-source voltage equals variations in threshold voltage.Along with continuing of negative bias instability stress, when the drift value of PMOSFET threshold voltage continues to increase, voltage and setting voltage between hysteresis loop comparator leaks the PMOSFET source compare, if the voltage between leak in the PMOSFET source is greater than setting value, hysteresis loop comparator will be exported high level, indicate that integrated circuit is about to lose efficacy.
Two, circuit structure
The test circuit that forecast integrated circuit negative bias instability of the present invention lost efficacy, comprise measuring tube PMOSFET, two NMOSFET and power supply are formed constant current bias circuit, PMOSFET and two NMOSFET form reference circuits, five NMOSFET and six PMOSFET form the hysteresis loop comparator circuit, three two-way switch circuit, phase inverter, switching tube PMOSFET; This measuring tube PMOSFET is used to measure threshold voltage shift; This constant current bias circuit provides constant biasing to PMOSFET; The reference circuits of this PMOSFET and two NMOSFET compositions provides reference voltage for the hysteresis loop comparator circuit, and biasing is provided for the grid of NMOSFET; Three two-way switch circuit switch measuring tube PMOSFET between stress is degenerated and tested; Phase inverter is anti-phase with the gate stress of measuring tube PMOSFET, and is transferred to its drain electrode; This switching tube PMOSFET closes hysteresis loop comparator circuit, constant current bias circuit and reference circuits during measuring tube PMOSFET is in stress, to reduce power consumption; During test, switching tube is opened hysteresis loop comparator circuit, constant current bias circuit and reference circuits, and the voltage between leak in measuring tube PMOSFET source is greater than reference voltage V
REFThe time, hysteresis loop comparator circuit output high level is indicating that integrated circuit is about to lose efficacy.
The present invention has following advantage:
(1) test circuit of the present invention adopts the hysteresis loop comparator circuit that the drift value of measuring tube threshold voltage is judged, the false alarm of having avoided the recovery Effects in the inefficacy of negative bias instability to cause.
(2) test circuit of the present invention adopts the constant current bias circuit in the circuit that measuring tube is setovered, and current source need not additionally be provided.
(3) test circuit of the present invention adopts the reference circuits in the circuit reference voltage to be provided for the hysteresis loop comparator circuit, and Voltage Reference need not additionally be provided.
(4) be between the stress catagen at measuring tube, hysteresis loop comparator circuit, constant current bias circuit and reference circuits in the test circuit of the present invention are in holding state, have reduced the power consumption of integrated circuit demand.
(5) test circuit of the present invention places integrated circuit with the degenerative process of measuring tube, directly adopt the electric stress that device experienced in the integrated circuit to impose on measuring tube, and the temperature stress of measuring tube experience is also identical with integrated circuit, has reacted the change procedure of integrated circuit temperature stress in real time.
Description of drawings
Fig. 1 is test philosophy figure of the present invention;
Fig. 2 is test circuit figure of the present invention;
Fig. 3 is the added stress configurations figure of negative bias instability failure testing pipe of the present invention;
Fig. 4 negative bias instability of the present invention lost efficacy and forecast the test circuit analogous diagram.
Concrete embodiment
Describe principle of the present invention and test circuit in detail below in conjunction with accompanying drawing.
With reference to Fig. 1, under negative bias instability stress, the threshold voltage of PMOSFET can drift about, and the present invention is based on this phenomenon and comes the negative bias instability lost efficacy and forecast.PMOSFET3 is a measuring tube among Fig. 1, its grid and drain electrode short circuit, and this moment, measuring tube was in state of saturation, and constant current source 2 links to each other with its source electrode, applies constant biasing to it.Voltage on 4 of PMOSFET 3 source electrodes is:
V wherein
ThBe initial threshold voltage, C
OxBe the oxide layer electric capacity of unit area, μ is a carrier mobility, I
DSBe drain saturation current, W is the channel width of PMOSFET 3, and L is the channel length of PMOSFET 3,
γ is the lining parital coefficient, ψ
FBe the substrate silicon Fermi potential, V
BSBe lining source voltage.
When drift takes place in threshold voltage under negative bias instability stress, its drift value Δ V
ThAbsolute value just equal 4 variation delta V that go up voltages
oIf, V
oContinue to increase, measuring tube PMOSFET 3 will lose efficacy.
With reference to Fig. 2, test circuit of the present invention comprises: measuring tube, constant current bias circuit, reference circuits, hysteresis loop comparator circuit, three two-way switch circuit K1～K3, phase inverter 24 and switching tube PMOSFET 12.This constant current bias circuit is by NMOSFET 7, and NMOSFET 8 forms with power supply, and this reference circuits is by PMOSFET 9, NMOSFET 10 and NMOSFET 11 form, and this hysteresis loop comparator circuit is by five NMOSFET 17～19,21,23 and six PMOSFET 13～16,20,22 form.NMOSFET 7 in the circuit, and NMOSFET 8, and PMOSFET 9, and NMOSFET 10, and NMOSFET 11 is grid leak short circuit structure.These test circuit elements all adopt the standard CMOS process design layout, and are compatible fully with other integrated circuit diagram technology, and are integrated in the integrated circuit diagram.The annexation of entire circuit is as follows:
NMOSFET 7 and NMOSFET 8 are connected in series, and the drain electrode of this NMOSFET 8 connects power supply, form constant current bias circuit.
The drain electrode of PMOSFET 9 links to each other with NMOSFET 10 drain electrodes, and the source electrode of NMOSFET 10 links to each other with the drain electrode of NMOSFET 11, the source ground of NMOSFET 11, and the reference circuits of composition is for hysteresis loop comparator provides reference voltage V
REF
The source electrode of PMOSFET 13 joins with the source electrode of PMOSFET 14 and links to each other with the drain electrode of switching tube PMOSFET 12, the grid of PMOSFET 13 links to each other with the grid of PMOSFET 14 and the drain electrode of PMOSFET 13 respectively, the drain electrode of PMOSFET 14 links to each other with the drain electrode of PMOSFET 16, and PMOSFET 13 and PMOSFET 14 are load current source of NMOSFET 17.
The source electrode of PMOSFET 15 joins with the source electrode of PMOSFET 16 and links to each other with the drain electrode of switching tube PMOSFET 12, the grid of PMOSFET 15 links to each other with the grid of PMOSFET 16 and the drain electrode of PMOSFET 16 respectively, the drain electrode of PMOSFET 15 links to each other with the drain electrode of PMOSFET 13, and PMOSFET 15 and PMOSFET 16 are load current source of NMOSFET 18.
The gate bias of NMOSFET 19 is provided by the drain voltage of NMOSFET 10, and drain electrode links to each other with the source electrode of NMOSFET 17, source ground, and it is the tail current source of hysteresis loop comparator.
The drain electrode of PMOSFET 20 links to each other with the drain electrode of NMOSFET 21, and source electrode connects the drain electrode of switching tube PMOSFET12, and grid links to each other with the drain electrode of PMOSFET 13.Grid and the drain electrode of NMOSFET 21 are joined, and link to each other the source ground of NMOSFET 21 with the grid of NMOSFET 23.
The drain electrode of PMOSFET 22 links to each other with the drain electrode of NMOSFET 23, and source electrode connects the drain electrode of switching tube PMOSFET12, and grid links to each other with the drain electrode of PMOSFET 16.The source ground of NMOSFET (23).
In the test circuit, measuring tube PMOSFET 3 is used to measure threshold voltage shift.Because measuring tube is integrated in the integrated circuit diagram, their residing temperature stresses are identical, therefore only need to apply negative bias stress to measuring tube.The integrated circuit duration of work, two-way switch circuit K1, K2, K3 switch to K1a respectively, K2a, K3a, the source electrode of measuring tube connects power supply, and grid meets electric stress V
Stress, drain electrode meets V
StressInversion signal. studies show that, if apply static stress to measuring tube, the life-span of measuring tube will reduce significantly, can not react the actual life of integrated circuit, therefore test circuit of the present invention applies as shown in Figure 3 negative bias stress to measuring tube, wherein the stress wave shown in Fig. 3 a 5 loads on the grid of measuring tube, phase inverter 24 is anti-phase with waveform 5, obtain the waveform 6 shown in Fig. 3 b, and this waveform is loaded on the drain electrode of measuring tube, source electrode with measuring tube connects power supply again, measuring tube is under the dynamic negative bias stress. this kind stress has been considered recovery Effects, can the degeneration of actual response integrated circuit under negative bias instability stress. between the measuring tube catagen, the test signal of switching tube 12 grids is a high level, switching tube 12 ends, the hysteresis loop comparator circuit, constant current bias circuit and reference circuits are in holding state, have reduced the power consumption of integrated circuit demand.
During measurement, the test signal of switching tube 12 grids switches to low level, and this switching tube is opened.Simultaneously, two-way switch circuit K1, K2, K3 switch to K1b, K2b, K3b respectively.The source electrode of measuring tube PMOSFET 3 connects constant current bias circuit, its grid and drain electrode while ground connection, the voltage V between PMOSFET 3 sources leakage this moment
Out`Be transferred to the grid of the NMOSFET 17 in the hysteresis loop comparator circuit.The voltage V between if leak in measuring tube PMOSFET3 source
Out`Less than V
REF, PMOSFET 22 ends, and NMOSFET 23 opens, and Out is ordered and is output as low level.Degenerate under negative bias instability stress when measuring tube, make the voltage V between the leakage of measuring tube PMOSFET 3 sources
Out`Greater than V
REFThe time, PMOSFET 22 opens, and NMOSFET 23 ends, and Out order and is output as high level as shown in Figure 4, is indicating that integrated circuit is about to inefficacy.
Claims (10)
1. test circuit that forecasts that integrated circuit negative bias instability lost efficacy, it is characterized in that: it comprises measuring tube PMOSFET (3), two NMOSFET (7,8) form constant current bias circuit with power supply, PMOSFET (9) and two NMOSFET (10,11) form reference circuits, five NMOSFET (17,18,19,21,23) with six PMOSFET (13,14,15,16,20,22) form the hysteresis loop comparator circuit, three two-way switch circuit (K1, K2, K3), phase inverter (24), switching tube PMOSFET (12); This NMOSFET (7), NMOSFET (8), PMOSFET (9), NMOSFET (10), NMOSFET (11) is grid leak short circuit structure; This measuring tube PMOSFET (3) is used to measure threshold voltage shift; This constant current bias circuit provides constant biasing for PMOSFET (3); This PMOSFET (9) provides reference voltage for the hysteresis loop comparator circuit with the reference circuits that two NMOSFET (10,11) form, and biasing is provided for the grid of NMOSFET (19); (K1, K2 K3) switch PMOSFET (3) to three two-way switch circuit between stress is degenerated and tested; Phase inverter (24) is anti-phase with the gate stress of PMOSFET (3), and is transferred to its drain electrode; This switching tube PMOSFET (12) closes hysteresis loop comparator circuit, constant current bias circuit and reference circuits during PMOSFET (3) is in stress, to reduce power consumption; During test, switching tube (12) is opened hysteresis loop comparator circuit, constant current bias circuit and reference circuits, and the voltage between leak in PMOSFET (3) source is greater than reference voltage V
REFThe time, hysteresis loop comparator circuit output high level is indicating that integrated circuit is about to lose efficacy.
2. test circuit according to claim 1, it is characterized in that: between the stress catagen, the source electrode of measuring tube PMOSFET (3) connects power supply, and grid and drain electrode connect the opposite stress voltage of phase place respectively, during test, (K1, K2 K3) switch three two-way switch circuit simultaneously, the source electrode of measuring tube PMOSFET (3) is received by two NMOSFET (7,8) with power supply composition constant current bias circuit, its grid and drain electrode while ground connection, the voltage transmission between its source leakage this moment is given the hysteresis loop comparator circuit.
3. test circuit according to claim 1, it is characterized in that: NMOSFET (7) and NMOSFET (8) are connected in series, the drain electrode of this NMOSFET (8) connects power supply, form constant current bias circuit, the source electrode of this NMOSFET (7) links to each other with the drain electrode of PMOSFET (3), provides steady current to measuring tube.
4. test circuit according to claim 1, it is characterized in that: the drain electrode of PMOSFET (9) links to each other with NMOSFET (10) drain electrode, the source electrode of NMOSFET (10) links to each other with the drain electrode of NMOSFET (11), the source ground of NMOSFET (11), the reference circuits of forming is for hysteresis loop comparator provides reference voltage V
REF
5. test circuit according to claim 1, it is characterized in that: the source electrode of PMOSFET (13) joins with the source electrode of PMOSFET (14) and links to each other with the drain electrode of switching tube PMOSFET (12), PMOSFET (13) grid links to each other with the grid of PMOSFET (14) and the drain electrode of PMOSFET (13) respectively, and the drain electrode of PMOSFET (14) links to each other with the drain electrode of PMOSFET (16).
6. test circuit according to claim 1, it is characterized in that: the source electrode of PMOSFET (15) joins with the source electrode of PMOSFET (16) and links to each other with the drain electrode of switching tube PMOSFET (12), PMOSFET (15) grid links to each other with the grid of PMOSFET (16) and the drain electrode of PMOSFET (16) respectively, and the drain electrode of PMOSFET (15) links to each other with the drain electrode of PMOSFET (13).
7. test circuit according to claim 1, it is characterized in that: the source electrode of NMOSFET (17) links to each other with the source electrode of NMOSFET (18), the drain electrode of this NMOSFET (17) links to each other with the drain electrode of PMOSFET (13), and the grid of NMOSFET (17) links to each other with the drain electrode of NMOSFET (7); The drain electrode of this NMOSFET (18) links to each other with the drain electrode of PMOSFET (16), and the grid of NMOSFET (18) links to each other with the drain electrode of NMOSFET (11).
8. test circuit according to claim 1 is characterized in that: the grid of NMOSFET (19) links to each other with the drain electrode of NMOSFET (10), and the drain electrode of NMOSFET (19) links to each other with the source electrode of NMOSFET (17), the source ground of NMOSFET (19).
9. test circuit according to claim 1, it is characterized in that: the drain electrode of PMOSFET (20) links to each other with the drain electrode of NMOSFET (21), the source electrode of PMOSFET (20) connects the drain electrode of switching tube PMOSFET (12), and the grid of PMOSFET (20) links to each other with the drain electrode of PMOSFET (13); The grid of this NMOSFET (21) links to each other the source ground of NMOSFET (21) mutually in succession and with the grid of NMOSFET (23) with drain electrode.
10. test circuit according to claim 1, it is characterized in that: the drain electrode of PMOSFET (22) links to each other with the drain electrode of NMOSFET (23), the source electrode of PMOSFET (22) connects the drain electrode of switching tube PMOSFET (12), and the grid of PMOSFET (22) links to each other with the drain electrode of PMOSFET (16); The source ground of this NMOSFET (23).
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| CN2009102186540A CN101706551B (en) | 2009-10-30 | 2009-10-30 | Testing circuit for forecasting failure of back bias voltage unstability of integrated circuit |
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| CN101706551B CN101706551B (en) | 2012-01-04 |
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Cited By (8)
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| CN102495352A (en) * | 2011-12-27 | 2012-06-13 | 复旦大学 | Multifunctional test circuit of integrated circuit stress degradation and test method thereof |
| CN102590735A (en) * | 2012-02-16 | 2012-07-18 | 复旦大学 | Circuit and method for testing reliability of integrated circuit |
| CN103091534A (en) * | 2011-10-31 | 2013-05-08 | 立锜科技股份有限公司 | High voltage offset detection circuit |
| CN103576065A (en) * | 2012-07-24 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Test circuit of transistor threshold voltage |
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| CN107544011A (en) * | 2016-06-24 | 2018-01-05 | 上海北京大学微电子研究院 | For predicting the chip built-in self-checking circuit system in chip life-span |
| CN110892277A (en) * | 2017-07-19 | 2020-03-17 | 西门子股份公司 | Method and system for predictive maintenance of integrated circuits |
| TWI707149B (en) * | 2018-02-23 | 2020-10-11 | 百慕達商邁威國際有限公司 | On-chip reliability monitor and method |
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| CN103091534B (en) * | 2011-10-31 | 2015-02-11 | 立锜科技股份有限公司 | High voltage offset detection circuit |
| CN103091534A (en) * | 2011-10-31 | 2013-05-08 | 立锜科技股份有限公司 | High voltage offset detection circuit |
| CN102495352A (en) * | 2011-12-27 | 2012-06-13 | 复旦大学 | Multifunctional test circuit of integrated circuit stress degradation and test method thereof |
| CN102495352B (en) * | 2011-12-27 | 2014-06-11 | 复旦大学 | Multifunctional test circuit of integrated circuit stress degradation and test method thereof |
| CN102590735A (en) * | 2012-02-16 | 2012-07-18 | 复旦大学 | Circuit and method for testing reliability of integrated circuit |
| CN102590735B (en) * | 2012-02-16 | 2014-10-29 | 复旦大学 | Circuit and method for testing reliability of integrated circuit |
| CN103576065A (en) * | 2012-07-24 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Test circuit of transistor threshold voltage |
| CN107544011A (en) * | 2016-06-24 | 2018-01-05 | 上海北京大学微电子研究院 | For predicting the chip built-in self-checking circuit system in chip life-span |
| CN106771519A (en) * | 2016-12-14 | 2017-05-31 | 上海贝岭股份有限公司 | Voltage detection circuit |
| CN106771519B (en) * | 2016-12-14 | 2019-05-14 | 上海贝岭股份有限公司 | Voltage detection circuit |
| CN110892277A (en) * | 2017-07-19 | 2020-03-17 | 西门子股份公司 | Method and system for predictive maintenance of integrated circuits |
| CN110892277B (en) * | 2017-07-19 | 2022-06-03 | 西门子股份公司 | Method and system for predictive maintenance of integrated circuits |
| US11525858B2 (en) | 2017-07-19 | 2022-12-13 | Siemens Aktiengesellschaft | Method and system for predictive maintenance of integrated circuits |
| TWI707149B (en) * | 2018-02-23 | 2020-10-11 | 百慕達商邁威國際有限公司 | On-chip reliability monitor and method |
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| CN101706551B (en) | 2012-01-04 |
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