CN101699562A - Erasing and writing method of phase change memory - Google Patents
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Abstract
The invention discloses an erasing and writing method of a phase change memory. The erasing operation is realized in a way that: applying a small-pulse-height pulse on a phase change material in the device, wherein the pulse enables the phase change material to right achieve the fusion temperature and partially form amorphous areas in the phase change material; and continuing to applying a plurality of small-pulse-height pulses, and accumulating amorphous areas in the phase change material until the device is transferred from low impedance state to high impedance state. The invention realizes the erasing and writing operations by utilizing the accumulating function; on one hand, low heat produced by the small pulse height is beneficial for stability of the material, and on the other hand, the small pulse height can ensure the application of the phase change memory in the environment requiring low programming current (voltage), thereby reducing the energy consumption of the device and greatly saving the cost for optimizing the device structure under the condition of no change of the device structure of the phase change memory.
Description
Technical field
The present invention relates to the method for operating of storer, refer in particular to the erasing-writing method of the phase transition storage that can realize low-power consumption.The invention belongs to the micro-nano art of electronics.
Background technology
The phase transition storage technology is based on Ovshinsky at late 1960s (Phys.Rev.Lett., 21,1450～1453,1968) beginning of the seventies (Appl.Phys.Lett., 18,254～257,1971) phase-change thin film of Ti Chuing can be applied to that the conception of phase change memory medium sets up, and is the memory device of a kind of low price, stable performance.Phase transition storage can be made on the silicon wafer substrate, its critical material is that the research focus of recordable phase-change thin film, heating electrode material, thermal insulation material and extraction electrode material also just launches around its device technology: the physical mechanism research of device comprises how reducing device material etc.The ultimate principle of phase transition storage is to utilize electric impulse signal to act on the device cell, make phase-change material between amorphous state and polycrystalline attitude, reversible transition take place, low-resistance when high resistant during by the resolution amorphous state and polycrystalline attitude can realize writing, wipe and read operation of information.
Phase transition storage owing to have reads at a high speed, high erasable number of times, non-volatile, advantages such as component size is little, strong motion low in energy consumption, anti-and radioresistance, is thought flash memories that most possible replacement is present by international semiconductor TIA and becomes following storer main product and become the device of commercial product at first.
The reading and writing of phase transition storage, wiping operation apply the voltage or the current pulse signal of different in width and height exactly on device cell: wipe operation (RESET), after phase-change material temperature in adding a weak point and strong pulse enable signal device cell is elevated to more than the temperature of fusion, through thereby cooling realization phase-change material polycrystalline attitude is to amorphous conversion fast, promptly one state is to the conversion of " 0 " attitude again; Write operation (SET), when apply one long and pulse enable signal phase-change material temperature medium tenacity is raised under the temperature of fusion, on the Tc after, and keep a period of time to impel nucleus growth, thus realize the conversion of amorphous state to the polycrystalline attitude, promptly " 0 " attitude is to the conversion of one state; Read operation after adding a very weak pulse signal that can not exert an influence to the state of phase-change material, is read its state by the resistance value of measuring element unit.
Mechanism's great majority of being engaged at present the phase transition storage R﹠D work in the world are major companies of semicon industry, the focus that they pay close attention to all concentrates in the commercialization that realizes phase transition storage how as early as possible, problem concentrates on and reduces corresponding operating current, device architecture design and the research of storage mechanism etc.Wherein the reduction of the operating current of device is very crucial and important, because the phase transition process of phase transformation memory device unit finally will lean on the driving of complementary oxide semiconductor tube of metal or diode to realize, for realize with high density memory chips in CMOS pipe operating current or diode operation electric current be complementary the essential electric current that reduces device.The method that reduces device power consumption at present all is the change to device itself, and method has respectively: the contact area that reduces electrode and phase-change material; Improve the resistance of phase-change material; Between electrode and phase-change material or the inner thermoresistance layer or the like that adds of phase-change material.But these methods all will be changed device itself, and cost is huge, and by the change programming mode, thereby the realization read-write operation can be saved cost, this starting point of the present invention just.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of erasing-writing method of phase transition storage, reduces the erasable arteries and veins height of storer, under the situation that does not change the phase-change memory device structure, reduces device power consumption.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of erasing-writing method of phase transition storage when wiping operation, may further comprise the steps:
Step 1 applies a pulse to the phase-change material in the device, and described pulse makes phase-change material reach melt temperature, and in the local non-crystalline areas that forms of phase-change material;
Step 2 continues to apply a plurality of pulses to the phase-change material in the device, accumulates non-crystalline areas in phase-change material, forwards high-impedance state until device to from low resistance state.
Further, the induction element of described phase transition storage is CMOS pipe or P-N diode.Wherein, induction element is the switching device of connecting with phase transition storage, by control induction element come the control operation phase transition storage current signal conducting and close.
Further, accumulating non-crystalline areas in the step 2 in phase-change material is to connect by making non-crystalline areas and electrode form, thereby makes device forward high-impedance state to from low resistance state.
Further, described pulse is current impulse or potential pulse.
Further, when described pulse was current impulse, the arteries and veins height was 0.20-0.30mA.
Further, when described pulse was potential pulse, the arteries and veins height was 0.3-0.7V.
As one of preferred version of the present invention, the pulsewidth of the described pulse of step 1 is 20-120ns.
As one of preferred version of the present invention, each pulse in the described a plurality of pulses of step 2, its pulsewidth is 20-40ns.
As one of preferred version of the present invention, be spaced apart 5-40ns between the described a plurality of pulses of step 2.
As one of preferred version of the present invention, the arteries and veins higher primary school of the described a plurality of pulses of step 2 is in the arteries and veins height that equals the described pulse of step 1.
Further, each pulse in the described a plurality of pulses of step 2, its arteries and veins height is all smaller or equal to the arteries and veins height of its previous pulse, causes the influence of crystallization again in order to guarantee non-crystalline areas that each pulse operation did not stay last pulse operation.
When usually phase transition storage was wiped operation (RESET), the phase-change material temperature that need apply in a weak point and the strong pulse enable signal device cell was elevated to more than the temperature of fusion; During write operation (SET), apply one long and pulse enable signal phase-change material temperature medium tenacity is raised under the temperature of fusion, on the Tc.This traditional erasing-writing method is owing to emphasize the device reaction velocity, so requirement operation pulsewidth is little, thereby adopts stronger monopulse usually, the operating current or the voltage of device are bigger.In order to reduce device power consumption, the present invention has reduced the arteries and veins height of pulse, adopt multiple-pulse, realize the erasable operation of storer by cumulative function, the high stability of material that helps low in calories that produces of on the one hand low arteries and veins, low on the other hand arteries and veins height can guarantee that phase transition storage is in the application that requires under low program current (voltage) environment.
In technical scheme of the present invention, the mode of accumulating non-crystalline areas by small-pulse effect can realize the RESET operation.The operating impulse that the RESET operation of this accumulation formula needs only at the beginning can make in the polycrystalline phase-change material melt region is arranged, and satisfies the very little operating current of a requirement needs that melt region is arranged in the polycrystalline phase-change material.In the prior art, monopulse operation RESET electric current down is generally 2-3mA, and the solution of the present invention can keep under the constant situation of device architecture, reduces the RESET operating current to 0.2-0.3mA.At present the reset pulsewidth of PCRAM generally is 100ns, and the SET pulsewidth generally is 1000ns, thereby the key factor that influences phase transition storage speed is SET pulsewidth (1000ns).Technical scheme of the present invention can be implemented in and finishes cumulative operation in the 1000ns, so this erasable operation can reduce erasable electric current on the basis of not sacrificing the phase transition storage operating speed.
Thereby compared to prior art, beneficial effect of the present invention is: the erasing-writing method of this phase transition storage can limit operating current (or voltage), by multipulse cumulative function, improve current density, thereby the raising thermal efficiency, under the situation that does not change the phase-change memory device structure, reduced device power consumption, saved the cost of optimised devices structure greatly.
Description of drawings
Fig. 1 is a phase-change memory device longitudinal cross-section axis of no-feathering symmetry synoptic diagram among the embodiment 1,2;
Fig. 2 is single current impulse synoptic diagram of step 1 among the embodiment 1;
Fig. 3 is a plurality of current impulse current diagram of step 2 among the embodiment 1;
Fig. 4 a, Fig. 4 b are high-impedance state regional distribution chart and the temperature profiles after the step 1 current practice of embodiment 1;
Fig. 5 a, Fig. 5 b are high-impedance state regional distribution chart and the temperature profiles after first current impulse operation in the step 2 of embodiment 1;
Fig. 6 a, Fig. 6 b are high-impedance state regional distribution chart and the temperature profiles after second current impulse operation in the step 2 of embodiment 1;
Fig. 7 a, Fig. 7 b are high-impedance state regional distribution chart and the temperature profiles after the 3rd current impulse operation in the step 2 of embodiment 1;
Fig. 8 be among the embodiment in the current practice phase-change material resistance and running time concern synoptic diagram;
Fig. 9 is the univoltage pulse synoptic diagram of step 1 among the embodiment 2;
Figure 10 is a plurality of potential pulse synoptic diagram of step 2 among the embodiment 2;
Figure 11 a, Figure 11 b are high-impedance state regional distribution chart and the temperature profile of the step 1 of embodiment 2 after voltage-operated;
Figure 12 a, Figure 12 b are high-impedance state areal distribution and the temperature profiles after first potential pulse operation in the step 2 of embodiment 2;
Figure 13 a, Figure 13 b are high-impedance state regional distribution chart and the temperature profiles after second potential pulse operation in the step 2 of embodiment 2;
Figure 14 be among the embodiment voltage-operated in phase-change material resistance and running time concern synoptic diagram.
Description of symbols among the figure:
11 bottom electrodes, 12 phase-change materials
13 top electrodes, 14 insulating material
The melt temperature isotherm of 15 central symmetry axes, 41 Fig. 4 b
The melt temperature isotherm of non-crystalline areas 51 Fig. 5 b of 42 Fig. 4 a
The melt temperature isotherm of non-crystalline areas 61 Fig. 6 b of 52 Fig. 5 a
The melt temperature isotherm of non-crystalline areas 71 Fig. 7 b of 62 Fig. 6 a
The non-crystalline areas of 72 Fig. 7 a
81,82,83,84, the position of the resistance data point of 85 phase-change materials after different pulse operations
The non-crystalline areas of melt temperature isotherm 112 Figure 11 a of 111 Figure 11 b
The non-crystalline areas of melt temperature isotherm 122 Figure 12 a of 121 Figure 12 b
The non-crystalline areas of melt temperature isotherm 132 Figure 13 a of 131 Figure 13 b
The position of the resistance data point of 141,142,143,144 phase-change materials after different pulse operations
Embodiment
Below in conjunction with the more complete description the present invention of diagram, the invention provides preferred embodiment, but should not be considered to only limit among the embodiment set forth herein.
Phase transition storage is made of a plurality of device cells usually, each device cell comprise phase-change material and with contacted top electrode of phase-change material and bottom electrode, storer by the electric impulse signal that device cell is applied different in width and height realize reading, wiping, write operation.These electric impulse signals can change their arteries and veins height and pulsewidth by programming mode, and are applied on the phase-change material by electrode.
Traditional erasing-writing method is owing to adopted stronger pulse signal, and the operating current or the voltage of device are bigger, and electric current is generally 2-3mA, voltage usually＞1V.In order to reduce device power consumption, the invention provides a kind of erasing-writing method of new phase transition storage, this method goes for any phase change memory device unit.The induction element of described phase transition storage can be that the CMOS pipe also can be the P-N diode.
When adopting this method to wipe operation, may further comprise the steps:
Step 1, according to the characteristics of this phase change memory unit structure and phase-change material the phase-change material in the device being applied low high pulse of arteries and veins heats up phase-change material, this pulse makes the maximum temperature point in the phase-change material reach melt temperature just, and in the local non-crystalline areas that forms of phase-change material.Wherein, formed non-crystalline areas is not sealed bottom electrode (or top electrode) fully, as long as there is amorphous state to form.
Step 2 continues to apply a plurality of low high pulses of arteries and veins to phase-change material, accumulates non-crystalline areas in phase-change material, forwards high-impedance state until device to from low resistance state.Wherein, the accumulation non-crystalline areas makes device forward high-impedance state to from low resistance state by making non-crystalline areas and electrode form series connection in phase-change material.
Described pulse is current impulse or potential pulse.When described pulse was current impulse, the arteries and veins height was 0.20-0.30mA; When described pulse was potential pulse, the arteries and veins height was 0.3-0.7V.According to the characteristics of different phase change memory unit structure and phase-change material, the arteries and veins height that is adopted also can be different.
As preferred version of the present invention, the pulsewidth of the described pulse of step 1 is 20-120ns; Each pulse in the described a plurality of pulses of step 2, its pulsewidth is 20-40ns.Be spaced apart 5-40ns between the described a plurality of pulses of step 2.
As preferred version of the present invention, the arteries and veins higher primary school of a plurality of pulses described in the step 2 is in the arteries and veins height that equals pulse described in the step 1.Further, each pulse in the described a plurality of pulses of step 2, its arteries and veins height is all smaller or equal to the arteries and veins height of its previous pulse, causes the influence of crystallization again in order to guarantee non-crystalline areas that each pulse operation did not stay last pulse operation.
The non-crystalline areas that first pulse operation forms is equivalent to a restraining barrier in the polycrystalline phase-change material, can limit distribution of current, improves local current densities, thereby improves the thermal efficiency.When adding second pulse, pulse height still keeps less current (voltage), forms melt region in the middle of the passage between electrode and non-crystalline areas, quenches rapidly, makes this melt region form amorphous.By twice operation, it is big that non-crystalline areas becomes, and further limited electric current, improved current density, improved the thermal efficiency.Add the 3rd pulse current (voltage) again, because bigger current density, thereby make the thermal efficiency improve greatly, same arteries and veins height can the more crystalline phase-change material of fusion.Add up with this and to seal electrode, make that polycrystalline becomes series connection with the state-transition in parallel of amorphous in the device, make device reach high-impedance state, realize erasable operation (reset) until the high-impedance state non-crystalline areas.
Embodiment 1:
Phase-change memory device longitudinal cross-section axially symmetric structure as shown in Figure 1, bottom electrode 11 materials are W, phase-change material 12 is Ge
2Sb
2Te
5, top electrode 13 materials are W, insulating material 14 on every side is SiO
2, central symmetry axes 15.The bottom electrode radius is 20nm.Phase-change material thickness is 150nm.
Step 1 applies a monopulse to device, and as shown in Figure 2, the arteries and veins height is 0.20-0.30mA, and present embodiment is preferably 0.25mA, and pulsewidth (running time) is 20-120ns, is preferably 100ns.Device promptly reaches thermal equilibrium constantly at 25-30ns.That is to say when the device galvanization, phase-change material produces heat on the one hand, device is by upper/lower electrode and the heat radiation of surrounding medium material on the one hand, less than 25-30ns the time, heat radiation needs the time in the device, produces heat and accounts for main effect, temperature raises, greater than 25-30ns the time, heat that produces in the device and the heat that distributes reach balance, and temperature maintenance is constant.
This moment, temperature kept shown in Fig. 4 a, 4b, and wherein in the scope of melt temperature isotherm 41 parcels of Fig. 4 b, phase-change material melts, and pulse stops, and temperature reduces rapidly, and melt region forms the non-crystalline areas 42 of Fig. 4 a.Amorphous fails to seal bottom electrode, fails to form the series connection of high resistant and low-resistance, so device resistance keeps low resistance state.Shown in the Square Number strong point at 81,82,83,84 places among Fig. 8, resistance maintains 4.5kohm always.
Step 2 applies a plurality of pulses to device, adopts the same high 0.25mA of arteries and veins, and pulsewidth is that 20-40ns is preferably 30ns, is spaced apart 5-20ns between a plurality of pulses, is preferably 5ns, as shown in Figure 3.
In the pulse first time (0-30ns) operation, device promptly reaches thermal equilibrium at moment 30ns place.Temperature Distribution is shown in Fig. 5 a, 5b at this moment, and wherein in the scope of melt temperature isotherm 51 parcels of Fig. 5 b, phase-change material melts, and pulse stops, and temperature reduces rapidly, and melt region forms the non-crystalline areas 52 of Fig. 5 a.Amorphous fails to seal bottom electrode, fails to form the series connection of high resistant and low-resistance, so device resistance keeps low resistance state.Shown in the circular data point at 82 places among Fig. 8, resistance is 4.5kohm.
In the pulse second time (35ns-65ns) operation, device promptly reaches thermal equilibrium at moment 65ns place.Temperature Distribution is shown in Fig. 6 a, 6b at this moment, and wherein in the scope of melt temperature isotherm 61 parcels of Fig. 6 b, phase-change material melts, and pulse stops, and temperature reduces rapidly, and melt region forms the non-crystalline areas 62 of Fig. 6 a.Non-crystalline areas increases to some extent, but still fails to seal bottom electrode, fails to form the series connection of high resistant and low-resistance, so device resistance increases to some extent, but still keeps low resistance state.Shown in the circular data point at 83 places among Fig. 8, resistance is 9kohm.
In pulse for the third time (70ns-100ns) operation, device promptly reaches thermal equilibrium in the 100ns place constantly in pulse, this moment, Temperature Distribution was shown in Fig. 7 a, 7b, wherein in the scope of melt temperature isotherm 71 parcels of Fig. 7 b, phase-change material melts, pulse stops, and temperature reduces rapidly, and melt region forms the non-crystalline areas 72 of Fig. 7 a.Non-crystalline areas is sealed bottom electrode, forms the series connection of high resistant and low-resistance, so device transfers high-impedance state to from low resistance state, realizes erasable operation (reset).As the circular data point at 85 places among Fig. 8, resistance is 2600kohm.
Embodiment 2:
Adopt identical technical scheme with embodiment 1, difference is: the pulse signal that is adopted is a potential pulse.
Step 1 applies a monopulse to device, and as shown in Figure 9, the arteries and veins height is 0.3-0.7V, and present embodiment is preferably 0.3V, and pulsewidth (running time) is 20-120ns, is preferably 100ns.Device promptly reaches thermal equilibrium constantly at 25-30ns.Temperature keeps shown in Figure 11 a, 11b, and wherein in the scope of melt temperature isotherm 111 parcels of Figure 11 b, phase-change material melts, and pulse stops, and temperature reduces rapidly, and melt region forms the non-crystalline areas 112 of Figure 11 a.Amorphous fails to seal bottom electrode, fails to form the series connection of high resistant and low-resistance, so device resistance keeps low resistance state.Shown in the Square Number strong point at 141,142,143 places among Figure 14, resistance maintains 4.3kohm always.
Step 2 applies a plurality of pulses to device, adopts the same high 0.3V of arteries and veins, and pulsewidth is that 20-40ns is preferably 40ns, is spaced apart 20-40ns between a plurality of pulses, is preferably 20ns, as shown in figure 10.
In the pulse first time (0-40ns) operation, device promptly reaches thermal equilibrium at moment 30ns place.Temperature Distribution is shown in Figure 12 a, 12b at this moment, and wherein in the scope of melt temperature isotherm 121 parcels of Figure 12 b, phase-change material melts, and pulse stops, and temperature reduces rapidly, and melt region forms the non-crystalline areas 122 of Figure 12 a.Amorphous fails to seal bottom electrode, fails to form the series connection of high resistant and low-resistance, so device resistance keeps low resistance state.Shown in 142 place's circular data points among Figure 14, resistance is 4.3kohm.
In the pulse second time (60ns-100ns) operation, device promptly reaches thermal equilibrium in the 100ns place constantly in pulse, this moment, Temperature Distribution was shown in Figure 13 a, 13b, wherein in the scope of melt temperature isotherm 131 parcels of Figure 13 b, phase-change material melts, pulse stops, and temperature reduces rapidly, and melt region forms the non-crystalline areas 132 of Figure 13 a.Non-crystalline areas is sealed bottom electrode, forms the series connection of high resistant and low-resistance, so device transfers high-impedance state to from low resistance state, realizes erasable operation (reset).As 144 place's circular data points among Figure 14, resistance is 2700kohm.
The other technologies that relate among the present invention belong to the category that those skilled in the art are familiar with, and do not repeat them here.The foregoing description is the unrestricted technical scheme of the present invention in order to explanation only.Any technical scheme that does not break away from spirit and scope of the invention all should be encompassed in the middle of the patent claim of the present invention.
Claims (11)
1. the erasing-writing method of a phase transition storage is characterized in that: when wiping operation, may further comprise the steps:
Step 1 applies a pulse to the phase-change material in the device, and described pulse makes phase-change material reach melt temperature, and in the local non-crystalline areas that forms of phase-change material;
Step 2 continues to apply a plurality of pulses to the phase-change material in the device, accumulates non-crystalline areas in phase-change material, forwards high-impedance state until device to from low resistance state.
2. according to the erasing-writing method of the described phase transition storage of claim 1, it is characterized in that: the induction element of described phase transition storage is CMOS pipe or P-N diode.
3. according to the erasing-writing method of the described phase transition storage of claim 1, it is characterized in that: in phase-change material, accumulate non-crystalline areas in the step 2 and make device forward high-impedance state to from low resistance state by making non-crystalline areas and electrode form series connection.
4. according to the erasing-writing method of the described phase transition storage of claim 1, it is characterized in that: described pulse is current impulse or potential pulse.
5. according to the erasing-writing method of the described phase transition storage of claim 4, it is characterized in that: when described pulse was current impulse, the arteries and veins height was 0.20-0.30mA.
6. according to the erasing-writing method of the described phase transition storage of claim 4, it is characterized in that: when described pulse was potential pulse, the arteries and veins height was 0.3-0.7V.
7. according to the erasing-writing method of the described phase transition storage of claim 1, it is characterized in that: the pulsewidth of the described pulse of step 1 is 20-120ns.
8. according to the erasing-writing method of the described phase transition storage of claim 1, it is characterized in that: each pulse in the described a plurality of pulses of step 2, its pulsewidth is 20-40ns.
9. according to the erasing-writing method of the described phase transition storage of claim 1, it is characterized in that: be spaced apart 5-40ns between the described a plurality of pulses of step 2.
10. according to the erasing-writing method of the described phase transition storage of claim 1, it is characterized in that: the arteries and veins higher primary school of the described a plurality of pulses of step 2 is in the arteries and veins height that equals pulse described in the step 1.
11. erasing-writing method according to the described phase transition storage of claim 1, it is characterized in that: each pulse in the described a plurality of pulses of step 2, its arteries and veins height is all smaller or equal to the arteries and veins height of its previous pulse, causes the influence of crystallization again in order to guarantee non-crystalline areas that each pulse operation did not stay last pulse operation.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456397A (en) * | 2010-10-15 | 2012-05-16 | 美光科技公司 | Read distribution management for phase change memory |
| WO2016011638A1 (en) * | 2014-07-24 | 2016-01-28 | 华为技术有限公司 | Data storage method and control device for phase-change memory |
| US9336843B2 (en) | 2012-04-27 | 2016-05-10 | Micron Technology, Inc. | Program-disturb decoupling for adjacent wordlines of a memory device |
| US9508426B2 (en) | 2012-05-17 | 2016-11-29 | Micron Technology, Inc. | Program-disturb management for phase change memory |
| US9899084B2 (en) | 2014-07-24 | 2018-02-20 | Huawei Technologies Co., Ltd. | Data storage method and phase change memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101118784A (en) * | 2007-09-06 | 2008-02-06 | 复旦大学 | Reset operation method of resistor stochastic memory |
| KR101291222B1 (en) * | 2007-11-29 | 2013-07-31 | 삼성전자주식회사 | Method of operating phase change memory device |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456397A (en) * | 2010-10-15 | 2012-05-16 | 美光科技公司 | Read distribution management for phase change memory |
| CN102456397B (en) * | 2010-10-15 | 2014-11-19 | 美光科技公司 | Read distribution management for phase change memory |
| US8913426B2 (en) | 2010-10-15 | 2014-12-16 | Micron Technology, Inc. | Read distribution management for phase change memory |
| US9196359B2 (en) | 2010-10-15 | 2015-11-24 | Micron Technology, Inc. | Read distribution management for phase change memory |
| US9336843B2 (en) | 2012-04-27 | 2016-05-10 | Micron Technology, Inc. | Program-disturb decoupling for adjacent wordlines of a memory device |
| US9508426B2 (en) | 2012-05-17 | 2016-11-29 | Micron Technology, Inc. | Program-disturb management for phase change memory |
| WO2016011638A1 (en) * | 2014-07-24 | 2016-01-28 | 华为技术有限公司 | Data storage method and control device for phase-change memory |
| CN105723461A (en) * | 2014-07-24 | 2016-06-29 | 华为技术有限公司 | Data storage method and control device for phase-change memory |
| US9899084B2 (en) | 2014-07-24 | 2018-02-20 | Huawei Technologies Co., Ltd. | Data storage method and phase change memory |
| US10083749B2 (en) | 2014-07-24 | 2018-09-25 | Huawei Technologies Co., Ltd | Data storage method and phase change memory |
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