CN101661940A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN101661940A CN101661940A CN200910169152A CN200910169152A CN101661940A CN 101661940 A CN101661940 A CN 101661940A CN 200910169152 A CN200910169152 A CN 200910169152A CN 200910169152 A CN200910169152 A CN 200910169152A CN 101661940 A CN101661940 A CN 101661940A
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Abstract
A strong dielectric capacitor provided with a lower electrode (15), a strong dielectric film (16) and an upper electrode (17) is covered with an interlayer insulating film (18); one end of the lower electrode (15) is processed into comb dent shape, and a plurality of contact holes (21) are formed on the interlayer insulating film (18) so as to be matched with the survival part thereof, i.e., clearances (recess) are arranged between the lower ends of at least two of the contact holes (21) and on the lower electrode (15); and wiring (25) connected with the lower electrode (15) through the contact holes (21) is formed on the interlayer insulating film (18).
Description
The application is that application number is 200810090099.3, the applying date is on September 5th, 2003, denomination of invention is divided an application for the patent application of " semiconductor device and manufacture method thereof ".Application number is 200810090099.3, the applying date is on September 5th, 2003, denomination of invention is the application number (international application no: PCT/JP2003/011348), the applying date the dividing an application for the patent application of " semiconductor device and manufacture method thereof " that be on September 5th, 2003, denomination of invention that is 03826593.1 for the patent application of " semiconductor device and manufacture method thereof ".
Technical field
The present invention relates to a kind of realize the improving electrode of ferro-electric materials capacitor and the semiconductor device and the manufacture method thereof of the contact between the wiring.
Background technology
In recent years, though as cut off the electricity supply also can stored information nonvolatile storage, (FeRAM) is noticeable for strong dielectric memory.FeRAM utilizes the hysteresis characteristic of strong dielectric to come stored information.At strong dielectric memory, be provided with ferro-electric materials capacitor by each memory cell.Ferro-electric materials capacitor is to be provided with strong dielectric film as capacitor dielectric between pair of electrodes.Owing to ferro-electric materials capacitor produces polarization corresponding to the interelectrode voltage that applies,, also keep spontaneous polarization, so can keep information even cancellation applies voltage.In addition, when applying the polarity upset of voltage, the polarity of spontaneous polarization is also overturn.If can detect this spontaneous polarization, just can sense information.
In addition, because the capacity ratio SiO of strong dielectric film
2The electric capacity of film is big, so the situation of ferro-electric materials capacitor being enrolled booster circuit or smoothing circuit is also arranged.In the ferro-electric materials capacitor that is incorporated into booster circuit or smoothing circuit, any one of lower electrode, strong dielectric film and upper electrode is all big than the ferro-electric materials capacitor that constitutes memory cell.Therefore, on lower electrode, be formed with a plurality of contact holes.
At this, describe at the manufacture method in the past of semiconductor device with the peripheral circuit that has possessed ferro-electric materials capacitor.Figure 18 A and Figure 18 B to Figure 20 A and Figure 20 B are the figure that represents the manufacture method of semiconductor device in the past.In addition, Figure 18 B, Figure 19 B and Figure 20 B are the profiles along the II-II line among Figure 18 A, Figure 19 A and Figure 20 A.
When making such semiconductor device (strong dielectric memory), at first, on semiconductor substrate, for example Si substrate, form after the element such as CMOS transistor, form interlayer dielectric and wiring etc., shown in Figure 18 A and Figure 18 B, form the adhesive layer (basilar memebrane) of pellumina 111 as ferro-electric materials capacitor.Then, on pellumina 111, form conducting film (lower electrode film) and the strong dielectric film that lower electrode is used successively.Form the Pt film and be used as the lower electrode film, form Pb (Zr, Ti) O
3Film (PZT film) is used as strong dielectric film.Then, by heat-treating, make the strong dielectric film crystallization.On strong dielectric film form IrO thereafter,
xFilm is used as the conducting film (upper electrode film) that upper electrode is used.And, by processing these films by the order of upper electrode film, strong dielectric film and lower electrode film, thereby in the presumptive area that forms the FeRAM cell array, when forming a plurality of ferro-electric materials capacitors (not shown), in formation comprises the presumptive area of peripheral circuit of booster circuit and smoothing circuit, shown in Figure 18 A and Figure 18 B, form lower electrode 115, PZT film 116 and upper electrode 117.
In addition, the flat shape of each lower electrode 115 is that bond length is that 50 μ m～60 μ m, the length of growing the limit are the rectangle of 200 μ m～250 μ m.In addition, the flat shape that is arranged at the lower electrode of strong dielectric memory cell array is that bond length is that the length on 4.0 μ m, long limit is the rectangle of 560 μ m.
Process after these films, form TEOS oxide-film 118, this TEOS oxide-film 118 is carried out planarization by CMP (cmp) as interlayer dielectric.Then, form contact hole (not shown) on TEOS oxide-film 118 and pellumina 111 etc., this contact hole is up to diffusion layer (semiconductor substrate) of the below that is formed on lower electrode 115 etc.Then, shown in Figure 19 A and Figure 19 B, form up to the contact hole 121 of lower electrode 115 and up to the contact hole 122 of upper electrode 117 at TEOS oxide-film 118.At this moment, form a plurality of contact holes 121 at each lower electrode 115.
Then, whole go up to form TiN film (about 150nm) as bottom barrier metal (barrier metal) film, Al film and as the TiN film of top barrier metal film, by on these films, forming figure, shown in Figure 20 A and Figure 20 B, form wiring 125 that is connected with lower electrode 115 and the wiring 126 that is connected with upper electrode 117 via contact hole 122 via all contact holes 121.
In addition, even strong dielectric memory cell array portion, also parallel and formation of connecting up etc. with peripheral circuit portion.
Then, form after the interlayer dielectric that covers wiring 125 and 126, at 350 ℃ N
2Carry out 60 minutes the heat treatment of moisture that is used to remove this interlayer dielectric in the environment.
Afterwards, further form wiring and interlayer dielectric and finish semiconductor device.
But in fact, the result that the inventor observes with the surface of the semiconductor device of this method manufacturing in the past is, near such unusual of the existence depression contact site of the lower electrode of peripheral circuit portion.Thisly do not produce in memory cell array portion unusually.The present application people is in order to determine that this is what kind of situation and carried out section and observed and composition analysis unusually.Figure 21 A to Figure 21 C is near result's the curve chart of the composition analysis of the wiring of the expression contact site.In section was observed, near the contact site of lower electrode, wiring produced variable color.In addition, shown in Figure 21 A to Figure 21 C, the peak value of Si and Pt etc. has appearred in the zone that the peak value of Al should significantly occur.This expression is accompanied by reaction, and these atom diffusion are in wiring.
In addition, in having the semiconductor device of ferro-electric materials capacitor,, after having formed upper electrode, must carry out the annealing in process in oxygen atmosphere in order to improve the characteristic of strong dielectric film.Therefore, as electrode material, be difficult to the material of oxidation or the material that oxidation also keeps the electric conductor state even use.As this material, mainly use Pt, Ir or IrO
xSuch platinum group type metal and oxide thereof.In addition, as other wiring material, in other semiconductor device, also use general employed Al.And, in ferro-electric materials capacitor, be connected with other element etc. via Al wiring.At this moment, the thickness of strong dielectric film is thicker, and the size of the vertical direction of capacitor is also bigger.Therefore, towards darker in the majority of the contact hole of electrode for capacitors.And, be formed with the Al wiring via this contact hole.
But the platinum group type metal generation eutectic reaction of known Al and Pt etc. is speciallyyed permit No. 3045928 specification and JP as JP and is speciallyyed permit No. 3165093 specification put down in writing, and need form the barrier metal film of TiN film etc. between them.That is, as shown in figure 22, on dielectric film 145, be formed with ferro-electric materials capacitor, be formed with dielectric film 146 in the mode that covers this ferro-electric materials capacitor with the lower electrode 148 that constitutes by Pt.And, on dielectric film 146, be formed with contact hole up to lower electrode 148, on dielectric film 146, be formed with via in this contact hole and the barrier metal film 151 that is connected with lower electrode 148 and connect up 152.Barrier metal film 151 and connecting up 152 is made of TiN, Al respectively.
, the crystallization of Pt and TiN is along mutual identical orientation, so when heat-treating when form the Al wiring on the TiN barrier metal film after, exist Pt to pass the TiN barrier metal film and the situation of reacting with Al.And, when this reaction takes place, not only can cause loose contact, also can produce bigger projection upward, and then also produce influence the upper strata wiring.
Usually, in the LOGIC product, form the TiN film and use stacked barrier metal film on the Ti film, still, in ferro-electric materials capacitor, the Ti film absorbs O at contact interface from the platinum group type metal oxide that is used in electrode
2, form TiO
xLayer.Consequently, contact resistance uprises.In addition, in TOHKEMY 2002-100740 communique, put down in writing the stacked barrier metal film that on the TiN film, has formed the Ti film, but in this structure, Ti and Al reaction produce electromigration.
Patent documentation 1:JP speciallys permit specification No. 3045928;
Patent documentation 2:JP speciallys permit specification No. 3165093;
Patent documentation 3:JP spy opens the 2002-100740 communique.
Disclosure of an invention
The object of the present invention is to provide the reaction between a kind of electrode that can suppress ferro-electric materials capacitor and the wiring and obtain the semiconductor device and the manufacture method thereof of excellent contact portion.
The application first and the described semiconductor device of second invention are to be object with following semiconductor device, and this semiconductor device has: ferro-electric materials capacitor, and it has lower electrode, strong dielectric film and upper electrode; Interlayer dielectric, it is formed on the above-mentioned ferro-electric materials capacitor, is formed with a plurality of contact holes with respect to above-mentioned lower electrode; Wiring, it is formed on the above-mentioned interlayer dielectric, is connected with above-mentioned lower electrode via above-mentioned contact hole.
And first invention is characterised in that between the lower end of at least two contact holes in above-mentioned a plurality of contact holes, above-mentioned lower electrode is provided with the gap.In addition, second invention is characterised in that between the upper end of at least two contact holes in above-mentioned a plurality of contact holes, above-mentioned wiring is provided with the gap.
The described semiconductor device of the application the 3rd invention is to be object with following semiconductor device, and this semiconductor device has: ferro-electric materials capacitor, and it has lower electrode, strong dielectric film and upper electrode; Interlayer dielectric, it is formed on the above-mentioned ferro-electric materials capacitor, is formed with a plurality of contact holes with respect to above-mentioned lower electrode; Wiring, it is formed on the above-mentioned interlayer dielectric, is connected with above-mentioned lower electrode via above-mentioned contact hole; Barrier metal film, it is formed between above-mentioned lower electrode and the above-mentioned wiring.And the 3rd invention is characterised in that above-mentioned barrier metal film has: a TiN film, and it directly contacts with above-mentioned lower electrode; The Ti film, it is formed on the above-mentioned TiN film; The 2nd TiN film, it is formed on the above-mentioned Ti film.
The application's the described semiconductor device of the 4th invention is identical with first and second invention, is object with following semiconductor device, and this semiconductor device has: ferro-electric materials capacitor, and it has lower electrode, strong dielectric film and upper electrode; Interlayer dielectric, it is formed on the above-mentioned ferro-electric materials capacitor, is formed with a plurality of contact holes with respect to above-mentioned lower electrode; Wiring, it is formed on the above-mentioned interlayer dielectric, is connected with above-mentioned lower electrode via above-mentioned contact hole.And the 4th invention is characterised in that above-mentioned wiring has Ir film or Pt film.
The simple declaration of accompanying drawing
Fig. 1 is the schematic diagram of the semiconductor device of expression first embodiment of the invention.
Fig. 2 A and Fig. 2 B are the figure of manufacture method of the semiconductor device of expression first embodiment of the invention, and expression is equivalent to the zone of FeRAM cell array 1.
Fig. 3 A to Fig. 3 C is the figure of manufacture method of the semiconductor device of expression first embodiment of the invention, and expression is equivalent to the zone of peripheral circuit 2.
Fig. 4 A and Fig. 4 B are and then Fig. 2 A and Fig. 2 B, the figure of the manufacture method of the semiconductor device of expression first embodiment of the invention.
Fig. 5 A and Fig. 5 B are Fig. 3 A to Fig. 3 C and then, the figure of the manufacture method of the semiconductor device of expression first embodiment of the invention.
Fig. 6 A and Fig. 6 B are and then Fig. 4 A and Fig. 4 B, the figure of the manufacture method of the semiconductor device of expression first embodiment of the invention.
Fig. 7 A and Fig. 7 B are and then Fig. 5 A and Fig. 5 B, the figure of the manufacture method of the semiconductor device of expression first embodiment of the invention.
Fig. 8 A and Fig. 8 B are the figure of manufacture method of the semiconductor device of expression second embodiment of the invention.
Fig. 9 A and Fig. 9 B are and then Fig. 8 A and Fig. 8 B, the figure of the manufacture method of the semiconductor device of expression second embodiment of the invention.
Figure 10 A and Figure 10 B are and then Fig. 9 A and Fig. 9 B, the figure of the manufacture method of the semiconductor device of expression second embodiment of the invention.
Figure 11 is the figure of manufacture method of the semiconductor device of expression third embodiment of the invention.
Figure 12 is Figure 11 and then, the figure of the manufacture method of the semiconductor device of expression third embodiment of the invention.
Figure 13 is Figure 12 and then, the figure of the manufacture method of the semiconductor device of expression third embodiment of the invention.
Figure 14 is the lower electrode of expression in the four embodiment of the invention and the profile of the connecting portion of wiring.
Figure 15 is the profile of the semiconductor device of expression four embodiment of the invention.
Figure 16 is the result's of expression second experimental example a curve chart.
Figure 17 is the profile of manufacture method of the semiconductor device of expression fifth embodiment of the invention.
Figure 18 A and Figure 18 B are the figure that represents the manufacture method of semiconductor device in the past.
Figure 19 A and Figure 19 B are and then Figure 18 A and Figure 18 B, the figure of the manufacture method of expression semiconductor device in the past.
Figure 20 A and Figure 20 B are and then Figure 19 A and Figure 19 B, the figure of the manufacture method of expression semiconductor device in the past.
Figure 21 A to Figure 21 C is near result's the curve chart of the composition analysis of the wiring of the expression contact site.
Figure 22 is the profile of the connecting portion of lower electrode in the semiconductor device of representing in the past and wiring.
The best mode that carries out an invention
Below, at embodiments of the present invention, be specifically described with reference to accompanying drawing.In addition, for convenience of explanation, in the execution mode below, at the structure of semiconductor device, suitable describes with its manufacture method.
(first execution mode)
At first, describe at first embodiment of the invention.Fig. 1 is the schematic diagram of the semiconductor device of expression first embodiment of the invention.Fig. 2 A and Fig. 2 B to Fig. 7 A and Fig. 7 B are the figure of manufacture method of the semiconductor device of expression first embodiment of the invention.In addition, Fig. 2 B, Fig. 4 B and Fig. 6 B are the profiles along the I-I line among Fig. 2 A, Fig. 4 A and Fig. 6 A, and Fig. 3 B, Fig. 5 B and Fig. 7 B are the profiles along the II-II line among Fig. 3 A, Fig. 5 A and Fig. 7 A, and Fig. 3 C is the profile along the III-III line among Fig. 3 A.
Be provided with FeRAM cell array 1 and peripheral circuit 2 in the first embodiment.Alignment arrangements has a plurality of FeRAM unit in FeRAM cell array 1.In peripheral circuit 2, be provided with writing, read and necessary circuit, for example booster circuit and smoothing circuit etc. such as deletion of information in the FeRAM cell array 1.
When making such semiconductor device (strong dielectric memory), in the first embodiment, at first, on semiconductor substrate, for example Si substrate, form after the element such as CMOS transistor, form interlayer dielectric and wiring etc., shown in Fig. 2 A, Fig. 2 B, Fig. 3 A and Fig. 3 B, form the adhesive layer (basilar memebrane) of pellumina 11 as ferro-electric materials capacitor.Then, on pellumina 11, form conducting film (lower electrode film) and the strong dielectric film that lower electrode is used successively.The Pt film that forms thickness for example and be about 150nm is used as the lower electrode film, forms thickness for example and be Pb (Zr, the Ti) O about 150nm
3Film (PZT film) is used as strong dielectric film.Then, handle, make the strong dielectric film crystallization by about 750 ℃, carrying out Fast Heating.Strong dielectric film on form for example thickness be IrO about 250nm thereafter,
xFilm is used as the conducting film (upper electrode film) that upper electrode is used.And, order by upper electrode film, strong dielectric film and lower electrode film is processed these films, thereby in the presumptive area (second area) that forms FeRAM cell array 1, shown in Fig. 2 A and Fig. 2 B, form lower electrode 12, PZT film 13 and upper electrode 14, simultaneously, in the presumptive area (first area) that forms peripheral circuit 2, shown in Fig. 3 A and Fig. 3 B, form lower electrode 15, PZT film 16 and upper electrode 17.
At this, describe at the shape of lower electrode 12, PZT film 13 and upper electrode 14 and lower electrode 15, PZT film 16 and upper electrode 17.
In the first area, form a plurality of lower electrodes 15.The length of the flat shape of each lower electrode 15 the chances are minor face is that the length on 50 μ m～60 μ m, long limit is the rectangle of 200 μ m～250 μ m, but shown in Fig. 3 A, Fig. 3 B and Fig. 3 C, the part of 10 μ m of an end longitudinally, be formed with a plurality of otch (gap) that extend along the longitudinal, and be divided into the broach shape.Cut apart and the width of residual part (broach part) for example is about 0.5 μ m.PZT film 16 is formed on each lower electrode 15 and what be formed on otch on the lower electrode 15 is about 1 μ m at interval.Upper electrode 17 also is formed on each lower electrode 15.
Also form a plurality of lower electrodes 12 at second area.The length of the flat shape of each lower electrode 12 the chances are minor face is that the length on 4.0 μ m, long limit is the rectangle (elongated sheets shape) of 560 μ m.Therefore, to compare with lower electrode 15 be very little to lower electrode 12.PZT film 13 forms the elongated sheets shape on each lower electrode 12, upper electrode 14 forms by each memory cell.The flat shape of upper electrode 14 for example is that the length of minor face is 1.15 μ m, and the length on long limit is the rectangle of 1.8 μ m.
Process after these films, the TEOS oxide-film 18 that forms thickness for example and be about 1.5 μ m is used as interlayer dielectric, and this TEOS oxide-film 18 is carried out planarization by CMP.Then, be formed with on TEOS oxide-film 18 and the pellumina 11 etc. up to be formed on lower electrode 12 and 15 below diffusion layer (semiconductor substrate) till contact hole (not shown).Then, shown in Fig. 5 A and Fig. 5 B, in the first area, form in the contact hole 21 and the contact hole till upper electrode 17 22 of lower electrode 15 at TEOS oxide-film 18, shown in Fig. 4 A and Fig. 4 B, at second area, be formed with up to contact hole till the lower electrode 12 19 and the contact hole till upper electrode 14 20 at TEOS oxide-film 18.At this moment, in the first area,, longitudinally form a plurality of contact holes 21 with the interval about 1.3 μ m in the end that forms this otch one side at each lower electrode 15.At second area, respectively form a contact hole 19 at each lower electrode 14. Contact hole 19 and 21 flat shape for example are that length on one side is the square of 1.8 μ m.
Then, go up for whole and form barrier metal film, Al film and barrier metal film, be shaped by these films being carried out figure, shown in Fig. 6 A and Fig. 6 B, wiring portion 23 that formation is connected with lower electrode 12 via contact hole 19 and the wiring portion 24 that is connected with upper electrode 14 via contact hole 20, shown in Fig. 7 A and Fig. 7 B, form wiring portion 25 that is connected with lower electrode 15 via all contact holes 21 and the wiring portion 26 that is connected with upper electrode 17 via contact hole 22 simultaneously.At this moment, wiring portion 24 is formed on each upper electrode 14.In addition,, for example form respectively that thickness is the TiN film of 150nm, the Al film that thickness is 550nm, the TiN film that thickness is 150nm, still be not limited to this as the barrier metal film, Al film (Al wiring) and the barrier metal film that constitute these wiring portions 23～26.For example, execution mode as hereinafter described is such, also can constitute barrier metal film by TiN film, Ti film, TiN film.
Afterwards, for interlayer dielectric 18 is dewatered, at 350 ℃ N
2During 60 minutes, heat-treat in the environment.And, further form upper strata wiring and interlayer dielectric etc., thereby finish semiconductor device (strong dielectric memory).
Even in the past, in the FeRAM cell array, the reaction between wiring and lower electrode does not take place, and does not produce defective yet.This can think because under the situation of overlooking, and in the zone that lower electrode and Al wiring overlap each other, contact hole has accounted for most area, the Pt of reaction and the amount of Al cause seldom.In the present embodiment, when with in the past structure relatively the time, the area of the part that departs from from the contact hole 21 of lower electrode 15 has diminished and has formed the part of otch, and the reacting dose of Pt reduces.Consequently, the reaction of the Al wiring in lower electrode 15 and the wiring portion 25 is difficult to produce, and can avoid the defectives such as rising, broken string and distortion of contact resistance.
What be connected with the lower electrode that is made of Pt is diffusion barrier film, is the TiN film in the past.Even therefore the centre is provided with the TiN film, the abnormal response (eutectic reaction) of Pt and Al also takes place, this is because the inadequate cause of diffusion barrier of TiN film.In addition when considering when memory cell eutectic reaction does not take place, also to consider of the influence of the layout of the quantity of layout, contact hole of lower electrode and wiring to eutectic reaction.Therefore, for the Pt that is suppressed at peripheral circuit portion and the eutectic reaction of Al,, list diffusion barrier that improves the TiN film and the method for making the layout that is difficult to react as solution.
Improve the block of TiN film, though as long as improve the membranous of TiN film or thickness is thickened just passable, these countermeasures are considered the reliability this point to the influence of ferro-electric materials capacitor and wiring, can not the former state use.With respect to this,,, carry out easily so be difficult to take place changes of properties because the adjustment of layout does not need to change process conditions.
(second execution mode)
Then, describe at second execution mode.In second execution mode,, adopt the manufacture method identical, but the structure of peripheral circuit 2 and manufacture method are different with first execution mode with first execution mode about FeRAM cell array 1.Fig. 8 A and Fig. 8 B to Figure 10 A and Figure 10 B are the figure of manufacture method of the semiconductor device of expression second embodiment of the invention.In addition, Fig. 8 B, Fig. 9 B and Figure 10 B are the profiles along the II-II line among Fig. 8 A, Fig. 9 A and Figure 10 A.
In second execution mode, at first identical with first execution mode, on semiconductor substrate, for example Si substrate, formed after the element such as CMOS transistor, form interlayer dielectric and wiring etc., shown in Fig. 8 A and Fig. 8 B, form pellumina 11.Then, on pellumina 11, form lower electrode film and strong dielectric film successively.The Pt film that forms thickness for example and be about 150nm is used as the lower electrode film, and the PZT film that forms thickness for example and be about 150nm is used as strong dielectric film.Then, handle, make the strong dielectric film crystallization by about 750 ℃, carrying out Fast Heating.Strong dielectric film on forming for example IrO about 250nm thereafter,
xFilm is used as the upper electrode film.And, order by upper electrode film, strong dielectric film and lower electrode film is processed these films, thereby in the presumptive area (second area) that forms FeRAM cell array 1, when forming lower electrode 12, PZT film 13 and upper electrode 14 (with reference to Fig. 2 A and Fig. 2 B), in the presumptive area (first area) that forms peripheral circuit 2, shown in Fig. 8 A and Fig. 8 B, form lower electrode 15, PZT film 16 and upper electrode 17.But in second execution mode, the length of the flat shape of each lower electrode 15 the chances are minor face is that the length on 50 μ m～60 μ m, long limit is the rectangle of 200 μ m～250 μ m, does not form otch.
Process after these films, form thickness for example and be TEOS oxide-film 18 about 1.5 μ m, this TEOS oxide-film 18 is carried out planarization by CMP as interlayer dielectric.Then, form the contact hole (not shown) that arrives diffusion layer (semiconductor substrate) etc. at TEOS oxide-film 18 and pellumina 11 etc., this diffusion layer is formed on the below of lower electrode 12 and 15.Then, shown in Fig. 9 A and Fig. 9 B, in the first area, on TEOS oxide-film 18, form in contact hole 31 that arrives lower electrode 15 and the contact hole 22 that arrives upper electrode 17, at second area, on TEOS oxide-film 18, form contact hole 19 that arrives lower electrode 12 and the contact hole 20 (shown in Fig. 4 A and Fig. 4 B) that arrives upper electrode 14.At this moment, in the first area,, longitudinally form a plurality of contact holes 31 with the interval about 1.3 μ m at an end longitudinally at each lower electrode 15.
Then on whole, form barrier metal film, Al film and barrier metal film, be shaped by these films being carried out figure, in the time of the wiring portion 23 that formation is connected with lower electrode 12 via contact hole 19 and the wiring portion that is connected with upper electrode 14 via contact hole 20 24 (with reference to Fig. 6 A and Fig. 6 B), shown in Figure 10 A and Figure 10 B, form wiring portion 35 that is connected with lower electrode 15 via all contact holes 31 and the wiring portion 26 that is connected with upper electrode 17 via contact hole 22.At this moment, in wiring portion 35, be formed on and be a plurality of extension 35a that the broach shape extends on the vertical vertical direction with lower electrode 15, each extension 35a is connected with lower electrode 15 via the contact hole 31 of 1 row.In addition,, for example form respectively that thickness is the TiN film of 150nm, the Al film that thickness is 550nm, the TiN film that thickness is 150nm, still be not limited to this as the barrier metal film, Al film (Al wiring) and the barrier metal film that constitute these wiring portions.For example, execution mode as hereinafter described is such, can constitute barrier metal film by TiN film, Ti film, TiN film.
Afterwards, for interlayer dielectric 18 is dewatered, at 350 ℃ N
2During 60 minutes, heat-treat in the environment.And, further form upper strata wiring and interlayer dielectric etc., thereby finish semiconductor device (strong dielectric memory).
In this second execution mode, when with in the past structure relatively the time, the diminished part in gap of broach of the area of the part that departs from from the contact hole 31 of wiring portion 35, the reacting dose of Al reduces.Consequently, identical with first execution mode, the Al wiring in lower electrode 15 and the wiring portion 35 is difficult to react, and can avoid the defectives such as rising, broken string and distortion of contact resistance.
(the 3rd execution mode)
Below, describe at third embodiment of the invention.The 3rd execution mode is the execution mode that combination first execution mode and second execution mode form.Figure 11 to Figure 13 is the manufacture method of the semiconductor device of third embodiment of the invention.
In the 3rd execution mode, at first identical with first execution mode, on semiconductor substrate, for example Si substrate, formed after the element such as CMOS transistor, form interlayer dielectric and wiring etc., shown in Fig. 8 A and Fig. 8 B, form pellumina 11.Then, on pellumina 11, form lower electrode film and strong dielectric film successively.The Pt film that forms thickness for example and be about 150nm is used as the lower electrode film, and the PZT film that forms thickness for example and be about 150nm is used as strong dielectric film.Then, handle, make the strong dielectric film crystallization by about 750 ℃, carrying out Fast Heating.Strong dielectric film on form for example thickness be IrO about 250nm thereafter,
xFilm is used as the upper electrode film.And, order by upper electrode film, strong dielectric film and lower electrode film is processed these films, thereby in the presumptive area (second area) that forms FeRAM cell array 1, when forming lower electrode 12, PZT film 13 and upper electrode 14 (with reference to Fig. 2 A and Fig. 2 B), in the presumptive area (first area) that forms peripheral circuit 2, as shown in figure 11, form lower electrode 15, PZT film 16 and upper electrode 17.At this moment, identical with first execution mode, form otch at each lower electrode 15.
Process after these films, form thickness for example and be TEOS oxide-film 18 about 1.5 μ m, this TEOS oxide-film 18 is carried out planarization by CMP as interlayer dielectric.Then, form to arrive the contact hole (not shown) of diffusion layer (semiconductor substrate) etc. on TEOS oxide-film 18 and pellumina 11 etc., this diffusion layer is formed on the below of lower electrode 12 and 15.Then, as shown in figure 11, in the first area, on TEOS oxide-film 18, form contact hole 31 that arrives lower electrode 15 and the contact hole 22 that arrives upper electrode 17, at second area, on TEOS oxide-film 18, form contact hole 19 that arrives lower electrode 12 and the contact hole 20 (shown in Fig. 4 A and Fig. 4 B) that arrives upper electrode 14 simultaneously.At this moment, in the first area,, longitudinally form a plurality of contact holes 31 with the interval about 1.3 μ m in the end that forms this otch one side at each lower electrode 15.
Then, on whole, form barrier metal film, Al film and barrier metal film, be shaped by these films being carried out figure, wiring portion 23 that formation is connected with lower electrode 12 via contact hole 19 and the wiring portion 24 (with reference to Fig. 6 A and Fig. 6 B) that is connected with upper electrode 14 via contact hole 20, simultaneously, as shown in figure 12, form wiring portion 35 that is connected with lower electrode 15 via all contact holes 31 and the wiring portion 26 that is connected with upper electrode 17 via contact hole 22.At this moment, identical with second execution mode, in wiring portion 35, be formed on and be a plurality of extension 35a that the broach shape extends on the vertical vertical direction with lower electrode 15, each extension 35a is connected with lower electrode 15 via the contact hole 31 of 1 row.In addition,, for example form respectively that thickness is the TiN film of 150nm, the Al film that thickness is 550nm, the TiN film that thickness is 150nm, still be not limited to this as the barrier metal film, Al film (Al wiring) and the barrier metal film that constitute these wiring portions.For example, execution mode as hereinafter described is such, can constitute barrier metal film by TiN film, Ti film and TiN film.
Afterwards, for interlayer dielectric 18 is dewatered, at 350 ℃ N
2During 60 minutes, heat-treat in the environment.And, further form upper strata wiring and interlayer dielectric etc., thereby finish semiconductor device (strong dielectric memory).
In this 3rd execution mode, than first and second execution mode, the reacting dose of Pt and Al reduces, and more can avoid defective.
(first experimental example)
At this, the experiment of carrying out at the present application people in fact about first to the 3rd execution mode describes.
In this experiment, make the semiconductor device of first to the 3rd execution mode and semiconductor device in the past, observe the boundary vicinity of wiring portion and lower electrode.Consequently, with respect in semiconductor device in the past, producing the depression that is accompanied by reaction, in the semiconductor device of first to the 3rd execution mode, all there is not such depression.But, in the 3rd execution mode, though there is not variable color, in first and second execution mode, a little variable colors take place a little.
In addition, in this experiment,, adopted layout such shown in the table 1 at peripheral circuit at each semiconductor device.In addition, the numeric representation in the table 1 in lower electrode and Al wiring overlapping areas, has been made as the area of the part in the contact hole relative value of the area of the outer part of 1 o'clock contact hole under the situation of overlooking.In addition, about the FeRAM cell array, in any one semiconductor device, the relative value that the area of the part in the contact hole is made as the area of the outer part of 1 o'clock contact hole is made as 0.97.
According to table 1, under the situation of overlooking, in lower electrode and Al wiring overlapping areas, the area of the part that contact hole is outer with respect to the relative value of the area of the part in the contact hole smaller or equal to 2.0, be more satisfactory particularly smaller or equal to 1.9, smaller or equal to 1.8 just better, ideal smaller or equal to 1.3.
(the 4th execution mode)
Then, describe at the 4th execution mode of the present invention.In the 4th execution mode, use the film that constitutes by the TiN film that forms successively, Ti film and TiN film as barrier metal film.Figure 14 is the lower electrode of expression in the four embodiment of the invention and the profile of the connecting portion of wiring, and Figure 15 is the profile of the semiconductor device of expression four embodiment of the invention.
In the 4th execution mode, on the surface of the semiconductor substrate 40 of Si substrate etc., be formed with element separated region 41, in element active area, be formed with diffusion layer 42 by these element separated region 41 zonings.Be formed with silicide layer 43 on the surface of diffusion layer 42.And,, be formed with the dielectric film 44 and 45 of Si oxide-film etc. in the mode of cladding element separated region 41 and element active area.On dielectric film 45, be formed with the ferro-electric materials capacitor that constitutes by lower electrode 48, strong dielectric film 49 and upper electrode 50.And then, to cover the mode of this ferro-electric materials capacitor, be formed with the interlayer dielectric 46 of Si oxide-film etc.
Be formed with the contact hole that arrives silicide layer 43 at interlayer dielectric 46,45 and 44, W plug-in unit 47 is embedded in wherein.In addition, on dielectric film 46, be formed with contact hole that arrives upper electrode 50 and the contact hole that arrives lower electrode 48.And, on dielectric film 46, be formed with the wiring portion that constitutes by barrier metal film 51 and Al film (Al wiring) 52.The part of this wiring portion is connected with W plug-in unit 47, and another part is connected with lower electrode 48 via contact hole, and another part is connected with upper electrode 50 via contact hole.
For example, lower electrode 48 and upper electrode 50 are respectively by Pt, IrO
xConstitute.In addition, as shown in figure 14, barrier metal film 51 is that TiN film 51a, thickness about 75nm is that Ti film 51b about 5nm and thickness are that TiN film 51c about 75nm constitutes by thickness for example.
At this,, describe later at the operation that forms ferro-electric materials capacitor about the manufacture method of the semiconductor device of the 4th execution mode.
When forming ferro-electric materials capacitor, formed after the dielectric film 45, carry out the planarization of dielectric film 45, form lower electrode film (Pt film) and strong dielectric film (for example PZT film) in the above successively.Then, in oxygen atmosphere, carry out annealing in process, thereby make the strong dielectric film crystallization.Then, on strong dielectric film, form upper electrode film (IrO
xFilm).
Afterwards, process these films by the order of upper electrode film, strong dielectric film and lower electrode film.In this processing, at first, by the sputter etching of having used Etching mask the upper electrode film is carried out figure and be shaped, form upper electrode 50 thus.Then, in oxygen atmosphere, anneal.Then, process strong dielectric film, thereby form strong dielectric film 49 by the sputter etching of having used other Etching mask.And, also process the lower electrode film, thereby form lower electrode 48 in the sputter etching of the Etching mask by having used other.
Then, on whole, form dielectric film 46, for example carry out the planarization of dielectric film 46 by CMP.Then, by having used the dry-etching of Etching mask, form the contact hole that arrives silicide layer 43.Afterwards, form TiN film (not shown) and W film,, form W plug-in unit 47 by they are carried out CMP as barrier metal film in the mode of imbedding this contact hole.Then, by having used the dry-etching of Etching mask, form contact hole that arrives upper electrode 50 and the contact hole that arrives lower electrode 48.
Then, form TiN film (75nm), Ti film (5nm) and the TiN film (75nm) that constitutes barrier metal film 51 successively, in nitrogen environment, anneal.The condition of this annealing is for example 350 ℃, 30 minutes.Then, form the Al film that constitutes wiring 52.And,, form barrier metal film 51 that constitutes by TiN film (a TiN film) 51a, Ti film 51b and TiN film (the 2nd TiN film) 51c and the wiring 52 that constitutes by the Al film by Al film and TiN film, Ti film and TiN film are carried out the figure shaping.
Afterwards, form interlayer dielectric and wiring etc. again, finish semiconductor device.
In the 4th such execution mode, because the existence of Ti film 51b, thereby prevent that the Pt in the lower electrode 48 is diffused into wiring.In addition, because between Ti film 51b and lower electrode 48, form TiN film 51a, so also prevented TiO
xGeneration.And, because between Ti film 51b and wiring (Al wiring) 52, be formed with TiN film 51c, so also can prevent the reaction of Ti and Al and the electromigration that produces thereupon.
About the thickness of barrier metal film 51, the thickness of TiN film 51a and 51c is for being more satisfactory more than or equal to 50nm.This is because when the thickness of TiN film 51a or 51c deficiency 50nm, Ti film 51b and lower electrode 48 or 52 causes that react easily that connect up.In addition, the thickness of Ti film 51b is more satisfactory more than or equal to 5nm.This is because when the not enough 5nm of the thickness of TiN film 51b, the lower electrode 48 and 52 causes that react easily that connect up.
In addition, when forming the TiN film 51a that constitutes barrier metal film, at first, the formation of carrying out being easy to generate the formation under the condition of accumulation in the bottom of contact hole and being easy to generate these two operations of formation under the condition of accumulation at the side wall portion of contact hole is more satisfactory.In the past, only carried out being easy to generate formation under the condition of accumulation in the bottom of contact hole., say strictly that before the formation of barrier metal film, to be that purpose is carried out the situation of RF pre-treatment more to remove natural oxide film etc., consequently, the situation of adhering to Pt at the side wall portion of contact hole arranged.Therefore, only be easy to generate when forming the TiN film under the condition of accumulation, just might react attached to the Pt of side wall portion and the Ti film that constitutes barrier metal film in the bottom of contact hole.Relative therewith, be easy to generate by side wall portion under the condition of accumulation and also form the TiN film at contact hole, just can avoid this defective.In addition, from the angle that covers, in a word, the formation of carrying out being easy to generate in the bottom of contact hole the TiN film under the condition of accumulation earlier is more satisfactory.
In addition, in contact hole, form the TiN film, form IrO thereon
xFilm (iridium oxide membrane), it is also passable to form barrier metal film by these two films.In such structure, also can pass through IrO
xFilm suppresses Al and spreads to the lower electrode side.In addition, IrO
xThe thickness of film more than or equal to 50nm or for the degree of depth of contact hole 1/20 or be more satisfactory more than it.And then, in order better to suppress IrO
xFilm and reaction as the Al of wiring material also can be at IrO
xForm the TiN film on the film.
In addition, in order to improve TiN film and IrO
xThe adhesiveness of film can form the Ti film between them.At this moment, for the Ti film of the side wall portion that is suppressed at contact hole better and the reaction of Pt, when forming the TiN film that is connected with lower electrode, as mentioned above, being easy to generate under the condition of accumulation after the some of TiN film is formed on the bottom of contact hole, is more satisfactory being easy to generate under the condition of accumulation the other parts that side wall portion at contact hole forms the TiN film.
(second experimental example)
At this, the experiment of relevant the 4th execution mode that carries out at the present application people in fact describes.
In this experiment, make the semiconductor device of the 4th execution mode and semiconductor device in the past, carry out accelerated test and measure contact resistance.In addition, in semiconductor device in the past, the thickness of the barrier metal film 151 that will be made of TiN is made as 150nm.This result is illustrated in Figure 16.
As shown in figure 16, under 400 ℃ and 420 ℃, though any one semiconductor device does not have the rising of bigger contact resistance yet,, when being 420 ℃, in the 4th execution mode, contact resistance rises hardly, but in semiconductor device in the past, contact resistance significantly rises.In addition, after the accelerated test, produce on the surface of in the past semiconductor device and to expand.Can think that these phenomenons are because pass through 440 ℃ heating, have produced the cause of the eutectic reaction of Pt and Al in semiconductor device in the past.
(the 5th execution mode)
Then, describe at the 5th execution mode of the present invention.In the 5th execution mode, use Ir or Pt to replace Al as wiring material.Figure 17 is the profile of manufacture method of the semiconductor device of expression fifth embodiment of the invention.
In the present embodiment, after the surface of Si substrate (semiconductor substrate) 60 has formed element separated region 61, in element active area, form the element of transistor with high concentration impurity diffusion layer 62, low concentration impurity diffusion layer 63, silicide layer 64, gate insulating film 65, gate electrode 66, silicide layer 67 and sidewall 68 etc. by these element separated region 60 zonings.In addition, for example near the contact site of gate electrode 67, between gate electrode 67 and diffusion layer 62, form dielectric film 69.
Afterwards, on whole, form after the dielectric film 70 and 71 of Si oxide-film etc., carry out the planarization of dielectric film 71, form lower electrode film (Pt film) and strong dielectric film (for example PZT film) in the above successively.Then, by in oxygen atmosphere, carrying out annealing in process, make the strong dielectric film crystallization.Then, on strong dielectric film, form upper electrode film (IrO
xFilm).
Afterwards, process these films by the order of upper electrode film, strong dielectric film and lower electrode film.In this processing, at first, by the sputter etching of having used Etching mask the upper electrode film is carried out figure and be shaped, thereby form upper electrode 75.Then, in oxygen atmosphere, anneal.Then, process strong dielectric film, thereby form strong dielectric film 74 by the sputter etching of having used other Etching mask.Afterwards, on whole, form pellumina, used the sputter etching of other Etching mask to come processed alumina film and lower electrode film by utilization again, thereby form alumina protective layer 91 and lower electrode 73.
Then, on whole, form dielectric film 72, for example carry out the planarization of dielectric film 72 by CMP.Then, by having used the dry-etching of Etching mask, thereby form the contact hole that arrives silicide layer 64 grades.Afterwards, form TiN film (not shown) and W film,, form W plug-in unit 77 by this being carried out CMP as barrier metal film in the mode of imbedding this contact hole.Then, by having used the dry-etching of Etching mask, thereby form contact hole that arrives upper electrode 75 and the contact hole that arrives lower electrode 73.
Then, formed after the TiN film of formation barrier metal film the metal film of the Pt film of formation formation wiring or Ir film etc.Further, on metal film, form the TiN film as hardmask.Then, only the TiN film on the metal film is carried out figure by the dry-etching that has used Etching mask and be shaped, thereby form hardmask 79.Afterwards, remove Etching mask by ashing treatment after, by having used the dry-etching of hardmask 79, to metal film with and under the TiN film carry out figure and be shaped, form wiring 78 and barrier metal film (not shown).In addition, in this dry-etching, use for example to be heated to 300 ℃ or its above dry-etching device, etched condition is made as: temperature for example: 300 ℃ or more than it, gas flow rate: HBr/O
2=10sccm/40sccm, pressure: 0.6Pa.In this dry-etching, the halogen gas (Cl in the etching gas
2, HBr etc.) ratio be made as 0.4 or be more satisfactory below it.
Then, the dielectric film 80 and 81 of formation Si oxide-film etc. forms the contact hole that arrives hardmask 79 thereon.Then, in this contact hole, form after the W plug-in unit 82, on dielectric film 81, form barrier metal film and connect up 83.In addition, hardmask 79 is not removed after being used to form wiring 78 dry-etching yet, and as wiring 83 and the barrier metal film use between 78 of connecting up.Because hardmask 79 is formed on flat, thus its block height, even eutectic reaction can not take place in wiring 83 Al wiring yet between wiring.
Then, the dielectric film 84 and 85 of formation Si oxide-film etc. forms the contact hole that arrives wiring 83 thereon.Then, in this contact hole, form after the W plug-in unit 86, on dielectric film 85, form wiring 87.And, form dielectric film 88,89 and polyimide film 90 as epiphragma, form pad (pad) peristome that arrives wiring 87 thereon.
In the 5th such execution mode, constitute by Ir film or Pt film because be connected the wiring 78 of lower electrode 73, upper electrode 75, so between wiring 78 and lower electrode 73 and upper electrode 75, eutectic reaction can not take place.
But, in the man-hour that adds of carrying out noble metal film, in usual way, need broaden removing width and keeping width, the shape after the processing becomes conical in shape.Consequently, the wiring resistance ratio becomes higher by the value of wiring width expectation.Relative therewith, as mentioned above, when at 300 ℃ or more than it, Cl
2And/or HBr and O
2The gaseous mixture environment in when carrying out etching, can obtain low-resistance wiring 78.In addition, when carrying out such high temperature etching, photoresist mask in the past can not be used, but as mentioned above,, high temperature etching can be tackled by using the TiN film as hardmask.In addition, though even the TiN film is also etched hardly at the environment that is used for the etching noble metal film (halogen+oxygen), former state is remaining,, use as barrier metal film by former state, can prevent the eutectic reaction between the wiring of the wiring that forms and noble metal thereon.
In addition,, also can make up and obtain various effects from all or part of of the structure of each execution mode of first execution mode to the, five execution modes by a plurality of combinations.
Industrial utilizability
Such as above-mentioned detailed explanation, according to the present invention, can suppress ferro-electric materials capacitor electrode and with This connection be routed in unusual reaction in the contact section. Therefore, can suppress the rising of resistance, and then Distortion in also suppressing to make.
Table 1
| In the contact hole | Outside the contact hole | |
| The |
1 | 1.9 |
| The |
1 | 1.8 |
| The |
1 | 1.3 |
| In the past (reference example) | 1 | 2.5 |
Claims (6)
1. semiconductor device has:
Ferro-electric materials capacitor, it has lower electrode, strong dielectric film and upper electrode;
Interlayer dielectric, it is formed on the above-mentioned ferro-electric materials capacitor, is formed with a plurality of contact holes with respect to above-mentioned lower electrode;
Wiring, it is formed on the above-mentioned interlayer dielectric, is connected with above-mentioned lower electrode via above-mentioned contact hole,
Above-mentioned semiconductor device is characterised in that,
Above-mentioned wiring has Ir film or Pt film.
2. semiconductor device as claimed in claim 1 is characterized in that, has the TiN film that is formed in the above-mentioned wiring.
3. the manufacture method of a semiconductor device comprises:
Form the operation of ferro-electric materials capacitor, this ferro-electric materials capacitor has lower electrode, strong dielectric film and upper electrode;
Form the operation of interlayer dielectric on above-mentioned ferro-electric materials capacitor, this interlayer dielectric has a plurality of contact holes with respect to above-mentioned lower electrode;
Form the operation of wiring on above-mentioned interlayer dielectric, this wiring is connected with above-mentioned lower electrode via above-mentioned contact hole,
The manufacture method of above-mentioned semiconductor device is characterised in that,
The operation that forms above-mentioned wiring comprises the operation that forms Ir film or Pt film.
4. the manufacture method of semiconductor device as claimed in claim 3 is characterized in that, the operation that forms above-mentioned wiring comprises:
Form the operation of raw material film, this raw material film is made of Ir or Pt;
By the dry-etching more than 300 ℃ the above-mentioned raw materials film is carried out the operation that figure is shaped.
5. the manufacture method of semiconductor device as claimed in claim 4 is characterized in that, when carrying out above-mentioned dry-etching, uses and contains halogen gas and O
2Gas as etching gas, and make the ratio of the above-mentioned halogen gas in the above-mentioned etching gas smaller or equal to 0.4, wherein, this halogen gas is Cl
2Perhaps HBr.
6. the manufacture method of semiconductor device as claimed in claim 3 is characterized in that, the operation that forms above-mentioned wiring comprises:
Form the operation of raw material film, this raw material film is made of Ir or Pt;
On the above-mentioned raw materials film, form the operation of TiN film;
Use Etching mask that above-mentioned TiN film is carried out figure and be shaped, thus the operation of formation hardmask;
Remove the operation of above-mentioned Etching mask;
Use above-mentioned hardmask that the above-mentioned raw materials film is carried out the operation that figure is shaped.
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