JP2001250922A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cancel the continuity failure between capacity upper wiring and a plug or wiring existing in the lower layer, and to improve a manufacturing yield in a semiconductor memory using a ferroelectric capacitor. SOLUTION: In the semiconductor memory, the lower layer of capacity upper wiring 12 that is formed at the upper side of a ferroelectric capacitor Cf has a structure that is composed of conductive oxide, and at the same time is also used as the upper electrode of the ferroelectric capacitor. The capacity upper wiring 12 is connected to a plug 4 that is placed in the lower layer or other wiring via a conductor 15 that is formed by the same process as a lower electrode 8 of the ferroelectric capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a ferroelectric or high dielectric (hereinafter, referred to as a ferroelectric) for holding stored information formed on a semiconductor substrate. The present invention relates to a configuration of a semiconductor memory including a capacitor element and a memory cell transistor having a dielectric film of (high) dielectric) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, technical development of a semiconductor memory in which a ferroelectric film having spontaneous polarization characteristics or a high dielectric film which is a paraelectric but has a high dielectric constant is used as a capacitor insulating film has been actively performed. ing. FIG. 8 is an equivalent circuit diagram of a unit memory cell constituting a semiconductor memory using a ferroelectric (high) dielectric capacitor. The memory cell MC includes a field-effect transistor Tr and a ferroelectric (high) dielectric capacitor Cf connected to one of the source and the drain of the transistor. The other of the source and the drain of the transistor Tr is a bit. The line BL, the gate electrode of the transistor Tr is connected to the word line WL, and the other electrode of the ferroelectric (high) dielectric capacitor Cf is connected to the plate line PL. A large-scale memory can be configured by arranging the memory cells MC shown in FIG. 8 in a matrix.

FIG. 9 is a sectional view of a conventional unit memory cell. However, FIG. 9 also shows a portion where the plate line constituted by the on-capacitance wiring 12 is connected to a peripheral circuit outside the cell array region. In the conventional example shown in FIG.
Source / drain n ⁺ in the surface region of the silicon substrate 1
A diffusion layer 2 is formed, and a gate electrode 3 is formed on a p-type silicon substrate with a gate insulating film interposed therebetween, thereby forming a field-effect transistor as a cell transistor.

On the field effect transistor, a ferroelectric (high) dielectric capacitive element composed of a lower electrode 8, a ferroelectric (high) dielectric film 9, and a wiring 12 on a capacitor is formed with an interlayer insulating film 7 interposed therebetween. The lower electrode 8 is connected to the other source / drain diffusion layer 2 of the field effect transistor by the first plug 4. In this example, the word line WL also serves as the gate electrode 3 of the field effect transistor.

The ferroelectric (high) dielectric film 9 is made of PZT (Pb _x Zr).
Ti _1-x O ₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ), BS
It is formed using T (Ba _x Sr _{1 -x} TiO ₃ ) or the like. On the ferroelectric (high) dielectric capacitance element, a capacitance cover film 11 is formed, on which a capacitance line 12 is formed as a plate line. The on-capacitance wiring 12 is in contact with the ferroelectric (high) dielectric film 9 in a contact hole formed in the capacitance
This portion also serves as the upper electrode of the ferroelectric (high) dielectric capacitor. This structure is disclosed in Japanese Patent Application Laid-Open No. 8-335673.

The ferroelectric (high) dielectric film is usually formed in an oxidizing atmosphere, and after the ferroelectric (high) dielectric film is formed, annealing in an oxygen atmosphere is required to stabilize the ferroelectric (high) dielectric film. Since the lower electrode 8 is often used, an oxidation-resistant noble metal (for example, Pt, Ir) or a conductive oxide (for example, IrO ₂ , RuO ₂ ) is used.

However, when the lower electrode of the ferroelectric (high) dielectric capacitor is brought into contact with the plug as in the conventional example, it is not preferable that the portion to be brought into contact with the plug is made of a conductive oxide. . The reason for this is that the conductive oxide oxidizes the material constituting the plug, for example, W, and causes poor conduction between the plug and the lower electrode. Therefore, when a conductive oxide is used for the lower electrode, it is preferable to lay a noble metal (for example, Pt, Ir) under the conductive oxide.

The upper wiring 12 (which constitutes a plate line in FIG. 9) serves as an upper electrode of a ferroelectric (high) dielectric capacitance element at a portion in contact with the ferroelectric (high) dielectric film 9, so that its lowermost layer is formed. Is preferably a conductive oxide (for example, IrO ₂ , RuO ₂ ). The reason is described in JP-A-7-2452.
As disclosed in JP-A-37-37, when a conductive oxide such as IrO ₂ is used as an upper electrode in contact with a ferroelectric film, a remarkable effect of remarkably reducing fatigue deterioration of the ferroelectric film due to data rewriting is recognized. It is. For the high dielectric film, the lower layer of the wiring above the capacitor is conductive because the interface between the upper electrode and the high dielectric film has the function of reducing the leakage current due to oxygen defects in the high dielectric film. It is preferably an oxide.

A wiring layer 14 mainly composed of aluminum is formed on the upper wiring 12, and a wiring for connecting the bit line and the upper wiring 12 to the peripheral circuit is formed by the wiring layer 14. You. As described in Japanese Patent Application Laid-Open No. 2-172282, a plasma CV
A silicon nitride film (SiN _x ) or a silicon oxynitride film (SiO _x N _y ) is formed as the protection film 15 by the D method. This is because the silicon nitride film (SiN _x ) or the silicon oxynitride film (SiO _x N _y ) has moisture resistance that prevents the metal material from being corroded by moisture contained in the air.

[0010]

The above-capacitance wiring 12 must be connected to a plug or other wiring or a semiconductor substrate located below it. However, when the lowermost layer of the on-capacitance wiring 12 is made of a conductive oxide,
Contacting the lower layer with a plug in a lower layer causes conduction failure between the conductive oxide and the plug, resulting in a problem of lowering the production yield of the semiconductor memory. The reason is that the heat treatment applied after the contact with the plug material, for example, W or polysilicon, in contact with the conductive oxide slightly oxidizes the vicinity of the contact interface and forms a thin insulating film. A similar problem occurs when the capacitance upper wiring 12 is connected to another metal wiring or a semiconductor substrate below.

On the other hand, in the conventional example shown in FIG. 9, another wiring layer is newly introduced on the wiring on the capacitor, and the wiring on the capacitor and the plug are connected through the wiring layer to cause a problem of poor conduction. Are avoiding. However, this method has a problem that the manufacturing cost of the semiconductor memory increases due to the increase in the number of manufacturing steps. Further, the ferroelectric (high) dielectric film is easily deteriorated by the LSI manufacturing process, and if the number of steps after forming the ferroelectric (high) dielectric capacitive element is increased, the reliability as a semiconductor memory is impaired.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate poor conduction between a wiring on a capacitor and a plug or another wiring without increasing the manufacturing cost of the semiconductor memory and without impairing the reliability of the semiconductor memory. An object of the present invention is to provide a semiconductor device and a method thereof capable of improving a manufacturing yield.

[0013]

A semiconductor device according to the present invention comprises a lower electrode and a dielectric film formed above a metal wiring or plug on a semiconductor substrate on which the metal wiring or plug is formed; An insulating film formed on a dielectric film, and a wiring layer in contact with the dielectric film in a contact hole formed in the insulating film and communicating with the dielectric film and having a conductive oxide as a lowermost layer. And a wiring on the capacitor, wherein the wiring on the capacitance is connected to the metal wiring or the plug via a conductor.

The conductor is formed in the same step as the lower electrode, and the conductor is a platinum group element (Ru, Rh, Pd, Os, I
(r, Pt) or a conductor obtained by stacking a conductive oxide on a material mainly containing a platinum group element.

Further, the dielectric film, the lower electrode,
The invention is characterized in that a capacitance element of a semiconductor memory holding information is constituted by the above-mentioned wiring on the capacitance, and the dielectric film is a ferroelectric (high) dielectric.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a metal wiring or a plug on a semiconductor substrate, a step of simultaneously forming a lower electrode and a conductor thereon, and a step of forming a dielectric on the lower electrode Forming a film and an insulating film in this order; forming a contact hole in the insulating film that communicates with the dielectric film and the conductor; and contacting the conductive film with the dielectric film and the conductor in the contact hole. A step of forming an over-capacitance wiring composed of a wiring having a conductive oxide as a lowermost layer.

The operation of the present invention will be described. The wiring above the capacitor of the semiconductor memory is connected to the plug via a conductor formed in the same step as the lower electrode of the ferroelectric (high) dielectric capacitor. If it is connected to the plug via this conductor, no conduction failure occurs. This is because the lower electrode material, for example, Pt, which is in contact with the conductive oxide forming the lowermost layer of the wiring above the capacitor, is a noble metal and is not oxidized to become an insulator.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a sectional view of an embodiment of the semiconductor memory of the present invention. This semiconductor memory includes a semiconductor substrate 1, a memory cell transistor provided on the semiconductor substrate, a ferroelectric (high) dielectric capacitor, and a capacitor such as SiO ₂ provided on the ferroelectric (high) dielectric capacitor. It has a cover film 11 and a wiring 12 on the capacitor. Strong (high)
The dielectric capacitance element includes a lower electrode 8 and a ferroelectric film 9, and a wiring 12 on the capacitance is in contact with the ferroelectric (high) dielectric film 9 in a contact hole formed in the capacitance cover film. (High) Also serves as the upper electrode of the dielectric capacitor.

The upper wiring 12 is connected to the first conductor 15 via a conductor 15.
Connected to plug 4. In the present embodiment, the bit line 1
6 is formed in the same step as the wiring 12 on the capacitor. In this case, the bit line is connected to the memory cell transistor via the conductor 15 and the first plug 4. However, the bit line may be formed in another step.

The upper wiring 12 also serves as an upper electrode of a ferroelectric (high) dielectric capacitance element. In order to obtain good capacitance characteristics, the lower wiring of the upper wiring 12 is made of a conductive material such as IrO ₂ or RuO ₂ . It is composed of an oxide.

Next, a method of manufacturing the semiconductor memory according to the present embodiment will be described with reference to the process sectional views shown in FIGS. The transistor Tr and the first plug 4 are formed by a normal silicon semiconductor integrated circuit manufacturing process. First
As the plug, W, polysilicon or the like is used. After the first plug 4 is formed, the CMP (Chemecal Mechanical
Polishing) (FIG. 2).

Thereafter, a ferroelectric capacitor is formed by the following method. First, a lower electrode 8 is formed on an interlayer insulating film 11, and a ferroelectric (high) dielectric film 9 is formed thereon. As a material used for the lower electrode 8, a noble metal such as Pt, Ir, and Ru, or IrO on a noble metal such as Pt, Ir, and Ru are used.
_{And a} stack of conductive oxides such as RuO ₂ , which is usually formed by a sputtering method.

The lower electrode 8 is hardly oxidized under the noble metal in order to prevent the plug from being oxidized during the formation of a ferroelectric (high) dielectric film formed in an oxidizing atmosphere. It is preferable to spread TiN. Also, T
Under iN, as an adhesion layer on the interlayer insulating film 7, Ti
It is preferable to lay. As the strong (high) dielectric film 9,
PZT (PbLaZr _x T _{1 -x} O ₃ ) or SBT (S
rBi ₂ Ta ₂ O ₉ ), BST (Ba _x Sr _1-x TiO ₃ )
And the like are preferable since they have ferroelectricity and a high dielectric constant at room temperature, and are formed by a sputtering method, a sol-gel method, a CVD method, or the like.

Next, the ferroelectric film 9 and the lower electrode 8 are
Patterning is performed simultaneously by the IE method (FIG. 3). Lower electrode 8
At the same time, the conductor 15 is formed. Subsequently, the conductor 15
The upper ferroelectric (high) dielectric film 9 is removed by a wet etching method or the like (FIG. 4). Next, after depositing an insulating film such as a silicon oxide film as the capacitor cover film 11, a contact hole communicating with the ferroelectric film 9 and the conductor 15 is formed (FIG. 5).

Next, a conductive oxide or a material obtained by laminating another metal material on a conductive oxide is formed as the upper wiring 12 by a sputtering method or the like, and then patterned (FIG. 6). The bit lines 16 are simultaneously formed at this time. Alternatively, the bit line may be formed in another step. IrO ₂ , RuO _2, or the like is used as the conductive oxide constituting the lowermost layer of the upper wiring 12. Further, a protective film 13 is formed on the on-capacitance wiring. As the protective film 13, a silicon nitride film (SiN _x ) or a silicon oxynitride film (SiON _x ) film is formed by a plasma CVD method.

[0026]

Embodiments of the present invention will be described below. First,
A first embodiment of the present invention will be described with reference to the sectional view of FIG. This semiconductor memory includes a semiconductor substrate 1 and a memory cell transistor Tr provided on the semiconductor substrate.
The capacitor includes a ferroelectric capacitor Cf, a capacitor cover film 11 provided on the ferroelectric capacitor, and a wiring 12 on the capacitor.

The ferroelectric capacitor includes a lower electrode 8 and a ferroelectric film 9, and the upper wiring 12 contacts the ferroelectric film 9 in a contact hole formed in the capacitor cover film 11, and a ferroelectric film is formed at this portion. Also serves as the upper electrode of the dielectric capacitance element. The on-capacitance wiring 12 is a conductor 1 outside the memory cell array region.
5 is connected to the first plug 4. The bit line 16 is formed in the same step as the wiring 12 on the capacitor. The on-capacitance wiring 12 also serves as the upper electrode of the ferroelectric capacitive element, and in order to obtain good capacitance characteristics, the on-capacitance wiring 12 is formed by using IrO _{2 as the} lowermost layer and stacking Ir thereon.

The manufacturing method of this embodiment will be described. The semiconductor substrate 1 is manufactured by a normal silicon semiconductor integrated circuit manufacturing process.
The field effect transistor Tr and the first plug 4 are formed thereon (see FIG. 2). The first plug 4 is made of W.
Ti, TiN, and Pt are sequentially formed as a lower electrode 8 on the planarized interlayer insulating film 7 from the lower layer by a sputtering method. Subsequently, a PZT film having a thickness of 200 nm at a substrate temperature of 400 ° C. is formed as a ferroelectric film 9 by a CVD method.
(PbZr _0.45 Ti _0.55 O ₃ ) is formed.

After forming the PZT film, annealing is performed at 400 ° C. for 10 minutes in an oxygen atmosphere to improve the ferroelectric polarization characteristics. PZT film formation and subsequent annealing are performed in an oxidizing atmosphere, but the substrate temperature is as low as 400 ° C. or less.
In these steps, the first plug 4 or Ti and TiN formed thereon as a lower electrode are oxidized to form a lower electrode.
No conduction failure occurs between the first plugs 4.

Subsequently, the ferroelectric film 9 and the lower electrode 8 are simultaneously patterned by RIE (see FIG. 3). Subsequently, PZT on the conductor 15 is removed by wet etching with a mixed solution of hydrofluoric acid and nitric acid using a photoresist as a mask (see FIG. 4).

Next, an O ₃ -T
By the EOS CVD method, a SiO
_Two films are formed, and a contact hole reaching the surface of the ferroelectric film 9 and the conductor 15 is formed by RIE (see FIG. 5). After the formation of the contact hole, annealing is performed at 400 ° C. for 10 minutes in an oxygen atmosphere in order to remove damage applied to the ferroelectric film when the contact hole is formed. Subsequently, IrO ₂ and Ir are sequentially deposited as the upper wiring 12 by a sputtering method and patterned by an RIE method (see FIG. 6). The bit line 16 is also formed at this time.

After patterning the over-capacitance wiring 12, in a nitrogen atmosphere at 400 ° C. for 10
Anneal for a minute. Further, on the upper wiring 12,
As the protective film 13, a silicon oxynitride film (SiO _x N _y ) having a thickness of 1 μm is formed at a substrate temperature of 300 ° C. by a plasma CVD method using SiH ₄ , NH ₃ , and N ₂ O as source gases.

FIG. 7 shows a second embodiment of the present invention. In the second embodiment, the first embodiment is such that the bit line 17 is mainly made of aluminum and is formed by a wiring different from the wiring 12 on the capacitor before the ferroelectric capacitor element manufacturing process. And different. This semiconductor memory includes a semiconductor substrate 1 and
The memory cell transistor Tr provided on this semiconductor substrate, the first metal wiring 5, and the ferroelectric capacitive element Cf
And a capacitor cover film 11 provided on the ferroelectric capacitor
And a wiring 12 on the capacitor.

The ferroelectric capacitive element Cf includes a lower electrode 8 and a ferroelectric film 9, and the plate line 12 is
The ferroelectric film 9 is in contact with the ferroelectric film 9 in the contact hole formed at 1 and also serves as the upper electrode of the ferroelectric capacitor. The upper wiring 12 is connected to the second plug 6 via a conductor 15 outside the memory cell array region.

The upper wiring 12 also serves as the upper electrode of the ferroelectric capacitor Cf.
The lower wiring layer 12 is made of IrO _2, and Ir, TiN, and Al are stacked thereon in order to reduce resistance.

The manufacturing method of this embodiment will be described. The field effect transistor, the first plug 4, and the first metal wiring 5 are formed on the semiconductor substrate 1 by a normal silicon semiconductor integrated circuit manufacturing process. A second plug 6 is formed on the first metal wiring 5 to reach the surface of the interlayer insulating film 7 planarized by the CMP method. First metal wiring 5
Is formed by stacking Ti, TiN, Al, and TiN in order from the lower layer. Both the first plug 4 and the second plug 6 are made of W.

On the planarized interlayer insulating film 7, Ti, TiN, Ir and IrO ₂ are sequentially formed as a lower electrode 8 from the lower layer by a sputtering method, and the subsequent processes are the same as those of the first embodiment. is there.

[0038]

The effect of the present invention is to improve the yield of semiconductor memories. The reason for this is that, conventionally, when the lowermost layer of the over-capacitance wiring is made of a conductive oxide, there has been a problem that continuity failure often occurs between the over-capacitance wiring and the plug or other wiring. By connecting to a plug or another wiring via a conductor formed in the same step, such a conduction failure can be avoided without increasing the number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor memory of the present invention.

FIG. 2 is a cross-sectional view showing a part of the method for manufacturing a semiconductor memory according to the present invention.

FIG. 3 is a sectional view showing a part of the method for manufacturing a semiconductor memory according to the present invention;

FIG. 4 is a sectional view showing a part of the method for manufacturing a semiconductor memory according to the present invention;

FIG. 5 is a sectional view showing a part of the method for manufacturing a semiconductor memory according to the present invention;

FIG. 6 is a sectional view showing a part of the method for manufacturing a semiconductor memory according to the present invention;

FIG. 7 is a sectional view showing the structure of the semiconductor memory of the present invention.

FIG. 8 is an equivalent circuit diagram of a conventional semiconductor memory cell.

FIG. 9 is a sectional view showing the structure of a conventional semiconductor memory.

[Explanation of symbols]

Tr Cell transistor BL, 16, 17 Bit line PL Plate line WL Word line MC Memory cell Cf Strong (high) dielectric capacitance 1 p-type Si substrate 2 n ⁺ diffusion layer 3 Gate electrode 4, 6 Plug 5 Metal wiring 7 Interlayer insulation Film 8 Lower electrode 9 Strong (high) dielectric film 11 Capacitor cover film 12 Capacitance wiring (plate line) 13 Protective film 14 Wiring layer 15 Conductor

Claims (9)

[Claims] A lower electrode and a dielectric film formed above the metal wiring or the plug on the semiconductor substrate on which the metal wiring or the plug is formed; and an insulating film formed on the dielectric film. Contacting the dielectric film in a contact hole formed in the insulating film and communicating with the dielectric film,
And a wiring above the capacitor formed of a wiring layer having a conductive oxide as the lowermost layer, wherein the wiring above the capacitor is connected to the metal wiring or the plug via a conductor. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein said conductor is formed in the same step as said lower electrode. 3. The method according to claim 1, wherein the conductor is a platinum group element (Ru, R
h, Pd, Os, Ir, Pt), or a conductor obtained by laminating a conductive oxide on a material mainly containing a platinum group element. Or the semiconductor device according to 2. 4. The semiconductor memory device according to claim 1, wherein said dielectric film, said lower electrode, and said wiring on said capacitor form a capacitive element of a semiconductor memory for holding information. Semiconductor device. 5. The semiconductor device according to claim 1, wherein said dielectric film is a ferroelectric (high) dielectric. 6. A step of forming a metal wiring or a plug on a semiconductor substrate, a step of simultaneously forming a lower electrode and a conductor thereon, and forming a dielectric film and an insulating film on the lower electrode in this order. Forming a contact hole communicating with the dielectric film and the conductor in the insulating film; and contacting the dielectric film and the conductor in the contact hole and using a conductive oxide as a lowermost layer. A method of manufacturing a semiconductor device, comprising a step of forming a wiring on a capacitor constituted by wiring. 7. The conductor is made of a platinum group element (Ru, R
7. A conductor mainly composed of (h, Pd, Os, Ir, Pt) or a conductor obtained by laminating a conductive oxide on a material mainly composed of a platinum group element. The manufacturing method of the semiconductor device described in the above. 8. The semiconductor device according to claim 6, wherein said dielectric film, said lower electrode, and said wiring on said capacitor constitute a capacitive element of a semiconductor memory for retaining information. Device manufacturing method. 9. The method for manufacturing a semiconductor device according to claim 6, wherein said dielectric film is a ferroelectric (high) dielectric.