CN101661922B - Copper interconnection line with silicon through hole having high depth-to-width ratio and preparation method thereof - Google Patents
Copper interconnection line with silicon through hole having high depth-to-width ratio and preparation method thereof Download PDFInfo
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- CN101661922B CN101661922B CN200910041532.9A CN200910041532A CN101661922B CN 101661922 B CN101661922 B CN 101661922B CN 200910041532 A CN200910041532 A CN 200910041532A CN 101661922 B CN101661922 B CN 101661922B
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Abstract
The invention relates to a copper interconnection line with a silicon through hole having a high depth-to-width ratio, which is a copper interconnection line, the diameter of which is larger and larger from a starting end to a finishing end of the electrodeposited copper. The method for preparing the copper interconnection line by adopting the electrodeposition is characterized in that the electrodeposited copper grows from a thinner end to a thicker end; an anode adopts a high-purity electrolytic copper plate, the area of which is larger than or equal to two times of that of a cathode; the conducting current density is kept constant; in the transitional electrodeposited process, the intensities of the forward current and the reverse current are equal; and the conducting time of the forward current is 5 times of that of the reverse current. The invention uses the silicon through hole which is gradually thinned as a channel for growing the electrodeposited copper, and the silicon through hole can automatically adjust the distribution of local effective current densities in the electrodeposited process and is beneficial to enabling air bubbles generated by the cathode in the electrodeposited process to escape from the silicon through hole, thereby realizing the preparation of the copper interconnection line with the silicon through hole having the high depth-to-width ratio and no hole defects.
Description
Technical field
The present invention relates to a kind of vertical copper connecting line of silicon through hole of integrated circuit high-aspect-ratio, the invention still further relates to employing and turn to electro-deposition techniques to prepare the method for this vertical copper connecting line.
Background technology
Interconnecting silicon through holes technology is except improving the transmission characteristic of interconnection density and high speed signal, can also reduce power loss by reducing the length of whole lead-in wire, simultaneously contact hole is also for the Joule heat that tube core sends provides heat dissipation channel, thereby provides more excellent solution for the three-dimensional of MEMS encapsulation and IC is integrated.But interconnecting silicon through holes technology still faces the interior zero defect metallization of making, through hole of small through hole and the technical challenges such as formation of interconnection line and silicon substrate electric insulation.This project is conceived to the preparation of electro-coppering interconnection line in through hole.Plating has been the main technique of copper interconnecting line.The main purpose of electroplating be in silicon through hole, be full of densification, without hole, seamless and other defect, the copper that is evenly distributed.Although existing copper plating process can obtain satisfactory interconnection line in depth-to-width ratio is less than 10 through hole, but the through hole for high-aspect-ratio (> 10), electro-coppering interconnection line makes electric conductivity variation owing to containing cavity and other defect, even opens circuit.
Recently, the application study about pulse plating in integrated circuit copper interconnecting line more and more come into one's own [1,2].The people such as Dixit [2] have proposed a kind of new electroplating technology electro-coppering interconnection line in the through hole of high-aspect-ratio.In experiment, the silicon wafer that the method that first adopts STS DRIE is 200-400 μ m at thickness etches the through hole of diameter 10-30 μ m, and on the inwall of through hole, grow 1.8 silicon dioxide layers of μ m and the silicon nitride layer of 200nm stop copper to the diffusion of silicon.The gold seeds that 300nm is thick be deposited upon one contact disk on, and target silicon wafer with photoresist temporary bonding get up.Employing is by the plating mode of the end to top, and in order to make the deposition rate of copper in electroplating process keep constant, they have proposed " electrodeposition technology that depth-to-width ratio relies on ", are exactly high-aspect-ratio in brief, low positive current density, high negative-phase sequence curent density.But, because the upper and lower diameter of through hole is identical, in this method use procedure, need constantly to adjust size of current, adapt to the variation [2] of acid copper depth-to-width ratio, technique is relatively cumbersome, and is unfavorable for the effusion of the bubble that produces in electrodeposition process.
In addition, adopt at present electrodeposition technology to prepare the flawless copper interconnecting line of depth-to-width ratio about 15 also more difficult.List of references: [1] Al-Sarawi SF, Abbott D, Franzon PD.A review of 3-D packagingtechnology.Ieee Transactions on Components Packaging and ManufacturingTechnology Part B-Advanced Packaging 1998; 21:2.
[2]Dixit?P，Miao?JM.Aspect-ratio-dependent?copper?electrodepositiontechnique?for?very?high?aspect-ratio?through-hole?plating.Journal?of?theElectrochemical?Society?2006；153：G552.
Summary of the invention
First object of the present invention, just be to provide a kind of copper interconnection line with silicon through hole having high depth-to-width ratio of integrated circuit, make when this copper connecting line of preparation, local plating current density is adjusted on ground that can be real-time automatically, the effusion of the bubble that is conducive to produce in electrodeposition process, thus realize the preparation that depth-to-width ratio is greater than 15 copper interconnection line with silicon through hole.
For achieving the above object, copper interconnection line with silicon through hole having high depth-to-width ratio of the present invention is: thick one end, copper interconnecting line one end is thin, and pressing close to conductive silicon chip end is taper end.
Described silicon through hole is from thin to thick from acid copper starting end to clearing end diameter.
Second object of the present invention, is just to provide the preparation technology of above-mentioned copper interconnection line with silicon through hole having high depth-to-width ratio.
The preparation technology of described copper interconnection line with silicon through hole having high depth-to-width ratio mainly comprises the following steps:
1, adopt photoetching technique to prepare via mask at silicon chip surface;
2, use inductively coupled plasma (ICP) deep reaction ion etching (DRIE) technology on silicon chip, to obtain tapered silicon through hole, make device silicon chip;
3, then on the inwall of silicon through hole, grow silicon dioxide layer and silicon nitride layer;
4, preparation conductive silicon chip, at another sheet silicon chip surface sputtering sedimentation Cr and Au film in succession, makes conductive silicon chip;
5, being connected of conductive silicon chip and device silicon chip, first adopt corrosion-resistant glue to be connected at edge device silicon chip and conductive silicon chip, a thinner end in contact conductive silicon chip in silicon through hole, and pick out wire from conductive silicon chip;
6, acid copper interconnection line: acid copper is from thinner end to growing compared with butt end, and negative electrode is connected with conductive silicon chip, and anode adopts high-purity electrolysis copper coin, and its area is more than or equal to the twice of negative electrode; In whole electrodeposition process, it is constant that conducting current density keeps; In turning to electrodeposition process, adopted better simply square wave curent change trend, and forward current is equal with negative current intensity, forward current ON time is 5-7 times of negative current.
In above-mentioned preparation technology's the 2nd step, comprise following operation:
(a), in front side of silicon wafer etching, be formed on the blind hole that the thin diameter in the thick inner end of opening gradually changes;
(b) at silicon chip back side, carry out large area etching, till the silicon blind hole UNICOM with front-side etch;
(c) remove mask;
(d) device silicon chip is carried out to surface treatment.
Described DRIE technology reactive ion etching parameter is: etching gas SF
6flow velocity be 150-170sccm, passivation gas C
4f
8for 90-110sccm; ICP radio-frequency power is 750-850W, bottom electrode radio-frequency power 10-12W; Etch period: 7 initial etching cycle periods are 20 minutes (7*20=140 minute), rear 15 etching cycle periods are 10 minutes.
In above-mentioned preparation technology's the 6th step, the concrete electro-deposition parameter of described pulse electrodeposition copper is as follows:
CuSO
430-60 grams per liter, H
2sO
4200-240 grams per liter, Cl
-45-55ppm, additive EP-1100C35-45 milliliter/liter, brightener EP-1000R 5-7 milliliter/liter, temperature is room temperature, and mechanical agitation in deposition process is positive and negatively more than or equal to 5 to electric current ratio turn-on time, and current density is set as 11-15mA/cm
2electrodeposition time is 24 hours.
Beneficial effect: because the diameter in hole is at hole length direction skewness, through hole taper end is d corresponding to diameter, the diameter of through hole butt end is corresponding to d ', as seen from Figure 2, d ' > d.In electrodeposition process, the corresponding current density of thinner end is larger, thereby deposition velocity is very fast, and this design can make acid copper promptly contact with conductive gold film, increases the electric conductivity of whole electro-deposition system.Along with the growth of acid copper, it is large that the diameter of through hole becomes, and effective current density now reduces gradually.Lower current density makes copper deposition be not easy to produce defect.Tapered through hole, except can automatically regulating electric current, also has another one advantage, is conducive to the derivation of the gas that produces in deposition process, thereby has also reduced the generation of acid copper defect.In addition, of the present invention, turn in electrodeposition process, adopted better simply curent change trend, and forward current is equal with negative current, but forward current ON time is 5-7 times of negative current.The employing of negative current mainly can make the more outstanding part of copper surface ratio of deposition fall as anodic solution, totally makes acid copper reach the effect of crystallization refinement densification.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, patent of the present invention is further illustrated.
Fig. 1 is the technological process that electro-deposition techniques is prepared the vertical copper interconnecting line of high-aspect-ratio: (a) Mask Fabrication; (b) front side of silicon wafer etching; (c) silicon chip back side perforate; (d) remove mask; (e) device silicon chip surface treatment (deposition 1.8 silicon dioxide layers of μ m and the silicon nitride of 200nm); (f) conductive silicon chip preparation; (g) device silicon chip adopts insulating cement to be connected with conductive silicon chip;
Fig. 2 is the device schematic diagram of acid copper interconnection line;
Fig. 3 is that depth-to-width ratio is about 18 silicon through hole SEM photo;
Fig. 4 adopts the copper interconnection line with silicon through hole that depth-to-width ratio prepared by the present invention is 18.
Wherein, 1-photoresist, 2-silicon dioxide layer, 3-silicon chip, 4-silicon dioxide layer and silicon nitride layer, 5-Au and Cr coating, 6-epoxide-resin glue, 7-copper.
embodiment
Referring to Fig. 1 to Fig. 4, copper interconnection line with silicon through hole having high depth-to-width ratio of the present invention is: thick one end, copper interconnecting line one end is thin, and pressing close to conductive silicon chip end is taper end.
The preparation technology embodiment mono-of above-mentioned copper interconnection line with silicon through hole having high depth-to-width ratio mainly comprises the following steps:
1, adopt photoetching technique to prepare via mask at silicon chip surface;
2, use inductively coupled plasma (ICP) deep reaction ion etching (DRIE) technology on silicon chip, to obtain tapered silicon through hole, make device silicon chip, containing following operation;
(a), in front side of silicon wafer etching, form the blind hole that meets depth-to-width ratio requirement that the thin diameter in the thick inner end of opening gradually changes;
(b) at silicon chip back side, carry out large area etching, till the silicon blind hole UNICOM with front-side etch;
(c) remove mask;
(d) device silicon chip is carried out to surface treatment;
Described DRIE technology reactive ion etching parameter is: etching gas SF
6flow velocity be 160sccm, passivation gas C
4f
8for 100sccm; ICP radio-frequency power is 800W, bottom electrode radio-frequency power 11W; Etch period: 7 initial etching cycle periods are 20 minutes (7*20=140 minute), rear 15 etching cycle periods are 10 minutes.
3, then on the inwall of silicon through hole, grow silicon dioxide layer and silicon nitride layer;
4, preparation conductive silicon chip, at another sheet silicon chip surface thick Cr of sputtering sedimentation 20nm and the thick Au film of 300nm in succession mutually, makes conductive silicon chip;
5, being connected of conductive silicon chip and device silicon chip, first adopt corrosion-resistant glue to be connected at edge device silicon chip and conductive silicon chip, a thinner end in contact conductive silicon chip in silicon through hole, and pick out wire from conductive silicon chip;
6, acid copper interconnection line: acid copper is from thinner end to growing compared with butt end, the conductive silicon chip connecting and device silicon chip are placed in the plating solution of electro-coppering, conductive silicon chip is as negative electrode, and anode adopts high-purity electrolysis copper coin, and its area is more than or equal to the twice of negative electrode; In whole electrodeposition process, it is constant that conducting current density keeps; In turning to electrodeposition process, adopt reversion electro-deposition techniques, adopted better simply square wave curent change trend, and forward current and negative current intensity equate, forward current ON time is 5-7 times of negative current, and the direction of growth of electro-coppering is that accessory rights requires the thinner end of the silicon through hole described in 1 to growing compared with butt end.
In above-mentioned preparation technology's the 6th step, the concrete electro-deposition parameter of described pulse electrodeposition copper is as follows:
CuSO
430-60 grams per liter, H
2sO
4200-240 grams per liter, Cl
-45-55ppm, additive EP-1100C35-45 milliliter/liter, brightener EP-1000R 5-7 milliliter/liter, temperature is room temperature, and mechanical agitation in deposition process is positive and negatively more than or equal to 5 to electric current ratio turn-on time, and current density is set as 11-15mA/cm
2electrodeposition time is 24 hours.
The concrete electro-deposition parameter of described pulse electrodeposition copper is as follows:
CuSO
440 grams per liters, H
2sO
4210 grams per liters, Cl
-50ppm, 40 milliliters/liter of additive EP-1100C, 5 milliliters/liter of brightener EP-1000R, temperature is room temperature, and mechanical agitation in deposition process is positive and negatively more than or equal to 5 to electric current ratio turn-on time, and current density is set as 12mA/cm
2electrodeposition time is 24 hours.
Claims (3)
1. a preparation technology who prepares copper interconnection line with silicon through hole having high depth-to-width ratio, mainly comprises the following steps:
1) adopt photoetching technique to prepare via mask at silicon chip surface;
2) use inductively coupled plasma (ICP) deep reaction ion etching (DRIE) technology on silicon chip, to obtain tapered silicon through hole, make device silicon chip;
3) then on the inwall of silicon through hole, grow silicon dioxide layer and silicon nitride layer;
4) prepare conductive silicon chip, at another sheet silicon chip surface sputtering sedimentation Cr and Au film in succession, make conductive silicon chip;
5) being connected of conductive silicon chip and device silicon chip, first adopt corrosion-resistant glue to be connected at edge device silicon chip and conductive silicon chip, a thinner end in contact conductive silicon chip in silicon through hole, and pick out wire from conductive silicon chip;
6) acid copper interconnection line: acid copper is from thinner end to growing compared with butt end, and negative electrode is connected with conductive silicon chip, and anode adopts high-purity electrolysis copper coin, and its area is more than or equal to the twice of negative electrode; In whole electrodeposition process, it is constant that conducting current density keeps; In turning to electrodeposition process, adopt the variable-current of square wave, and forward current is equal with negative current intensity, forward current ON time is 5-7 times of negative current.
2. the preparation technology of copper interconnection line with silicon through hole having high depth-to-width ratio according to claim 1, is characterized in that, in preparation technology's the 2nd step, comprising following operation:
(a), in front side of silicon wafer etching, form the blind hole that meets depth-to-width ratio requirement that the thin diameter in the thick inner end of opening gradually changes;
(b) at silicon chip back side, carry out large area etching, till the silicon blind hole UNICOM with front-side etch;
(c) remove mask;
(d) device silicon chip is carried out to surface treatment.
3. the preparation technology of copper interconnection line with silicon through hole having high depth-to-width ratio according to claim 2, is characterized in that: described deep reaction ion etching technology reactive ion etching parameter is: etching gas SF
6flow velocity be 150-170sccm, passivation gas C
4f
8for 90-110sccm; ICP radio-frequency power is 750-850W, bottom electrode radio-frequency power 10-12W; Etch period: 7 initial etching cycle periods are 20 minutes (7*20=140 minute), rear 15 etching cycle periods are 10 minutes.
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| KR101506910B1 (en) * | 2012-09-27 | 2015-03-30 | 티디케이가부시기가이샤 | Method for anisotropic plating and thin- film coil |
| CN103715131B (en) * | 2012-09-29 | 2016-02-03 | 中国航天科技集团公司第九研究院第七七一研究所 | Large depth-to-width ratio TSV through hole step etching and sidewall method of modifying |
| CN103879951B (en) * | 2012-12-19 | 2016-01-06 | 中国科学院上海微系统与信息技术研究所 | The preparation method of silicon through hole |
| US9365947B2 (en) * | 2013-10-04 | 2016-06-14 | Invensas Corporation | Method for preparing low cost substrates |
| CN105097652B (en) * | 2014-05-07 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN116288374B (en) * | 2022-12-30 | 2023-10-13 | 东莞赛诺高德蚀刻科技有限公司 | Metal surface secondary processing method based on etching and electrodeposition |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592964A (en) * | 2001-11-26 | 2005-03-09 | 先进微装置公司 | Method of implantation after copper seed deposition |
| CN1797737A (en) * | 2004-12-22 | 2006-07-05 | 上海华虹Nec电子有限公司 | Interspace technical method for implementing copper connecting lines in semiconductor device |
| CN101378047A (en) * | 2007-08-30 | 2009-03-04 | 联发科技股份有限公司 | Interconnection structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592964A (en) * | 2001-11-26 | 2005-03-09 | 先进微装置公司 | Method of implantation after copper seed deposition |
| CN1797737A (en) * | 2004-12-22 | 2006-07-05 | 上海华虹Nec电子有限公司 | Interspace technical method for implementing copper connecting lines in semiconductor device |
| CN101378047A (en) * | 2007-08-30 | 2009-03-04 | 联发科技股份有限公司 | Interconnection structure |
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