CN102148192B - Method for growing blocking layer and seed layer on surface of silicon through hole - Google Patents
Method for growing blocking layer and seed layer on surface of silicon through hole Download PDFInfo
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- CN102148192B CN102148192B CN 201010613156 CN201010613156A CN102148192B CN 102148192 B CN102148192 B CN 102148192B CN 201010613156 CN201010613156 CN 201010613156 CN 201010613156 A CN201010613156 A CN 201010613156A CN 102148192 B CN102148192 B CN 102148192B
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Abstract
The invention discloses a method for growing a blocking layer and a seed layer on a surface of a silicon through hole in the technical field of semiconductors. A silicon through hole structure which is provided with the blocking layer and the seed layer is obtained by sequentially carrying out titanium (Ti) deposition and wet oxidation on a substrate which is provided with the silicon through hole. In the method, the good stability, conductive performance and properties of difficult chemical change and relatively stronger bonding force with copper (Cu) of a titanium dioxide (TiO2) are utilized; the thickness of the prepared blocking layer is 200-1,000 nanometres; the seed layer which is obtained by oxidation has good conductive performance, relatively higher electric conductivity, uniform thickness and good step coverage; and the surface of the TiO2 observed by a scanning electron microscope (SEM) has a cylindrical structure, thereby facilitating bonding of the Cu and the seed layer.
Description
Technical field
What the present invention relates to is a kind of method of technical field of semiconductors, specifically a kind of method in silicon through-hole surfaces growth barrier layer and Seed Layer.
Background technology
Microelectronic industry is along with the deduction of Moore's Law, towards more small scale and the live width limit are approached.Being accompanied by characteristic size constantly descends, objectively bring the innovation on many integrated technologies, wherein led the trend of 3D encapsulation technology development based on the stacked package mode of through hole silicon (TSV) perpendicular interconnection with its short distance interconnection and superintegrated key technology advantage.
The TSV technology of using in the three-dimensional stacked encapsulation is the integrated of a series of technology, comprising: the silicon via etch, and the growth of insulating barrier through hole, barrier layer and Seed Layer growth, the silicon via metal is filled technology such as (mainly being Cu).Wherein, need between insulating barrier and metal Cu, introduce one deck diffusion impervious layer, prevent Cu in the silicon diffusion and form the complex centre, affect the semiconducting behavior of silicon, cause device performance degeneration.The barrier layer requires that good thermal stability is arranged, and with Seed Layer and insulating barrier stronger adhesion is arranged.At present, the research on barrier layer mainly concentrates on refractory metal Ru, Ta, Ti and nitride TaN thereof, TiN, WN with and ternary compound TaSiN, on the materials such as WNC.In existing main flow process system, adhesion/barrier in the through hole is that main dry process is finished by PVD, CVD, Seed Layer deposits then electro-coppering as Seed Layer by follow-up sputter or first PVD, and so not only complex process but also cost are expensive, are unfavorable for reducing cost.In addition, with conventional PVD method deposition Seed Layer, step coverage is poor, and bottom seed layer thickness only has 10～15% of opening part, cause bottom and opening part resistance difference, thereby deposition rate is had any different when causing electroplating.When electroplating filling, base copper ion depletion rate is faster than diffusion rate, so base copper ion concentration opening part copper ion concentration little (namely having concentration gradient), and it is slow to cause the bottom to electroplate the speed ratio opening part, forms easily cavity and crack.Therefore, only use PVD deposited barrier layer and Seed Layer, the uniformity of its step coverage and film is difficult to guarantee.If barrier layer and Seed Layer can be united two into one, perhaps in conjunction with wet processing, then can shorten the time, simplify technique, save cost.
Find through the retrieval to prior art, a kind of barrier/seed layers manufacture method has been proposed among the patent US20070062818, this technology mainly is by improving solution composition, adjust the plating condition, directly on copper diffusion barrier layer, form the good and continuous Seed Layer of figure spreadability, its thickness 10nm～20nm with electro-plating method.Used barrier layer is TaN (400nm)/Ta (10nm) bilayer film, and TaN obtains by reaction magnetocontrol sputtering, and Ta is the film of magnetron sputtering.But complex process, and require high, plating condition to be difficult to control to solution composition.
(day for announcing: the method for modifying that has proposed the silicon through hole 2009-12-15): the silicon through-hole surfaces is used CVD deposit passivation layer SiN or SiON to US Patent No. 7633165 successively, thickness 200nm～1500nm, sputtered with Ti, reactive sputtering TiN then, at last sputter Cu again.Wherein Ti can be with PVD or ion metal plasma (IMP) deposition techniques, thickness 50nm～120nm of TiN and Ti.The method can not be avoided the poor problem of Seed Layer step coverage, can produce cavity and crack in that copper is inner after electroplate filling, and the adhesion of copper and TiN is not fine, and the uniformity of Seed Layer is difficult to guarantee.
Summary of the invention
The present invention is directed to the prior art above shortcomings, provide a kind of novel on silicon through-hole surfaces growth barrier layer the method with Seed Layer: usefulness dry method depositing Ti film then oxidation Ti as TSV in Seed Layer.TiO
2Have good thermal stability and conductivity, and with Cu stronger adhesion is arranged.In addition, Ti has good barrier properties, and Seed Layer is obtained by wet oxidation Ti, has guaranteed the step coverage of Seed Layer, has well solved the problem that forms the cavity of filling of electroplating.
The present invention is achieved by the following technical solutions, the through-silicon via structure of the present invention by the substrate with silicon through hole being carried out successively obtain having barrier layer and Seed Layer behind Ti deposition and the wet oxidation.
Described substrate with silicon through hole specifically adopts acetone to clean under the ultrasound environments of 25kHz-68kHz through ultrasonic cleaning and oven dry, removes surface organic matter and pollutes, and carries out twice washed with de-ionized water to remove residual acetone again, then dries.
The temperature of described oven dry is 60 ℃-80 ℃, and drying time is: 10min-20min.
Described Ti deposition refers to: adopt the dry film depositional mode, be lower than 2 * 10 at background vacuum pressure
-4Pa, sputtering pressure are lower than under the inert gas sputtering atmosphere of 1.0Pa, take pure Ti target as sputtering target material, the rotation substrate are set, and deposit thickness is between 200nm-1000nm.
Described dry film depositional mode refers to: magnetron sputtering, ion beam sputtering or pulsed laser deposition.
Described wet oxidation refers to: substrate is placed hydrogen peroxide and NaOH mixed solution, place 30-50 ℃ water-bath to react.
Described mixed solution prepares in the following manner: be the H of 30wt% with concentration
2O
2It is in the NaOH aqueous solution of 10g/L-30g/L that solution adds concentration.
Described clean oven dry refers to: substrate was put into 45 ℃ of deionized waters 10 minutes, use deionized water in the ultrasonic middle cleaning of 25kHz-68kHz again, at last at 80 ℃-100 ℃ lower oven dry 10min-20min.
The present invention utilizes the dry method depositing Ti and carries out the subsequent oxidation processing TVS barrier layer and Seed Layer technique are united two into one, and compared with prior art advantage comprises: greatly simplified depositing operation and the cost of barrier layer and Seed Layer, only needed a dry method sputter; Barrier layer and the Seed Layer adhesion of preparation are good, have compared better interface binding power and stability with multistep sputter or plating seed layer; Barrier layer and the seed layer thickness of preparation are even, and step coverage is good; The barrier layer that is applied to TSV and the Seed Layer technology of preparation, cost is low, and technological process is simple, low-power consumption, pollution-free, and very strong market application foreground is arranged.
Description of drawings
Fig. 1 is the silicon through hole generalized section with insulating barrier that deep reaction ion etching goes out;
Fig. 2 is the silicon through hole generalized section that deposits barrier layer and Seed Layer;
Among the figure: 1 silicon through hole substrate, 2 insulating barriers, 3 barrier layers and Seed Layer.
Embodiment
The below elaborates to embodiments of the invention, and present embodiment is implemented under take technical solution of the present invention as prerequisite, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
Be used for the preparation of the ultrathin film of TSV barrier layer and Seed Layer, specifically may further comprise the steps:
(1) the silicon through hole substrate that is used for TSV with ultrasonic cleaning carries out magnetron sputtering deposition Ti, and sedimentary condition is: the background vacuum is 2 * 10
-4Pa, sputtering target material are the Ti of purity 99.99%.
(2) sputtering atmosphere is high-purity Ar, and air pressure is 1Pa, and substrate rotates to improve uniformity, and the speed of rotation is that the 12rpm sputtering time is 100min, deposition rate 2nm/min.
Wet oxidation is carried out in the substrate placement with silicon through hole that (3) will deposit Ti, and NaOH concentration is 20g/L, and volume is 100ml, adds H
2O
2Volume be 2ml, 30 ℃ of temperature, the time is 30min, cleaning, drying, temperature is 80 ℃, the time is 20min.
The barrier layer thickness of above-mentioned preparation is 200nm, and gained Seed Layer electric conductivity is good after the oxidation, has higher conductivity, can reach the requirement of electro-coppering, even thickness, and step coverage is good.Titania surface is column structure under SEM, is conducive to the combination of Cu and Seed Layer.In addition, behind 450 ℃ of high-temperature thermal annealings, the Ti barrier layer still can keep preferably barrier properties, does not detect the existence of copper at Ti and silicon oxide interface place.
Ion beam depositing and wet oxidation are used for the ultrathin film of TSV barrier layer and Seed Layer, specifically may further comprise the steps:
(1) the silicon through hole substrate that is used for TSV with ultrasonic cleaning carries out ion beam sputter depositing Ti, and sedimentary condition is: the background vacuum is 5 * 10
-4Pa, sputtering target material are the Ti of purity 99.99%.
(2) sputtering atmosphere is high-purity Ar, and operating air pressure is 1.9 * 10
-2Pa, substrate rotates to improve uniformity, and the speed of rotation is that the 12rpm sputtering time is 120min, deposition rate 5nm/min.
Wet oxidation is carried out in the substrate placement with silicon through hole that (3) will deposit Ti, and NaOH concentration is 10g/L, and volume is 100ml, adds H
2O
2Volume be 2ml, 30 ℃ of temperature, the time is 30min, cleaning, drying, temperature is 80 ℃, the time is 20min.
The barrier layer thickness of above-mentioned preparation is 600nm, and gained Seed Layer electric conductivity is good after the oxidation, has higher conductivity, can reach the requirement of electro-coppering, even thickness, and step coverage is good.Titania surface is column structure under SEM, is conducive to the combination of Cu and Seed Layer.In addition, behind 450 ℃ of high-temperature thermal annealings, the Ti barrier layer still can keep preferably barrier properties, does not detect the existence of copper at Ti and silicon oxide interface place.
Embodiment 3
Pulsed laser deposition and wet oxidation are used for the ultrathin film of TSV barrier layer and Seed Layer, specifically may further comprise the steps:
(1) the silicon through hole substrate that is used for TSV with ultrasonic cleaning carries out ion beam sputter depositing Ti, and sedimentary condition is: the background vacuum is 1 * 10
-4Pa, sputtering target material are the Ti of purity 99.99%.
(2) the used lasing light emitter of sputter is (KrF ex-cimer laser, wavelength 250nm, pulse frequency 5Hz), air pressure is 0.01Pa, and substrate rotates to improve uniformity, and the speed of rotation is 12rpm, sputtering time is 20min, deposition rate 10nm/min.
Wet oxidation is carried out in the substrate placement with silicon through hole that (3) will deposit Ti, and NaOH concentration is 10g/L, and volume is 100ml, adds H
2O
2Volume be 2ml, 30 ℃ of temperature, the time is 30min, cleaning, drying, temperature is 80 ℃, the time is 20min.
The barrier layer thickness of above-mentioned preparation is 200nm, and gained Seed Layer electric conductivity is good after the oxidation, has higher conductivity, can reach the requirement of electro-coppering, even thickness, and step coverage is good.Titania surface is column structure under SEM, is conducive to the combination of Cu and Seed Layer.In addition, behind 450 ℃ of high-temperature thermal annealings, the Ti barrier layer still can keep preferably barrier properties, does not detect the existence of copper at Ti and silicon oxide interface place.
In above-mentioned three embodiment, described silicon chip all is the silicon chip that etches through hole through DRIE, and the technical parameter of silicon chip, the etching parameters of DRIE are along with the technical indicator of TSV changes and changes.
Claims (3)
1. the method in silicon through-hole surfaces growth barrier layer and Seed Layer is characterized in that, by the through-silicon via structure that the substrate with silicon through hole is carried out successively obtain having barrier layer and Seed Layer behind Ti deposition and the wet oxidation; Described wet oxidation refers to: the substrate with silicon through hole that will deposit Ti is positioned in the mixed solution of hydrogen peroxide and NaOH and carries out wet oxidation, the concentration of described NaOH solution is 10g/L or 20g/L, volume is 100ml, the volume that adds hydrogen peroxide is 2ml, described mixed solution carries out heating water bath under 30 ℃, the time is 30min, with the substrate cleaning, drying behind the heating water bath, bake out temperature is 80 ℃, and drying time is 20min.
2. the method in silicon through-hole surfaces growth barrier layer and Seed Layer according to claim 1 is characterized in that, described Ti deposition refers to: adopt the dry film depositional mode, be lower than 2 * 10 at background vacuum pressure
-4Pa under the inert gas sputtering atmosphere of sputtering pressure less than 1.0Pa, take pure Ti target as sputtering target material, arranges the rotation substrate, and deposit thickness is between 200nm-1000nm.
3. the method in silicon through-hole surfaces growth barrier layer and Seed Layer according to claim 2 is characterized in that described dry film depositional mode refers to: magnetron sputtering, ion beam sputtering or pulsed laser deposition.
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| CN102270603B (en) * | 2011-08-11 | 2013-12-04 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| WO2014012381A1 (en) * | 2012-07-17 | 2014-01-23 | 上海交通大学 | Copper-connection microcolumn mechanical property in-situ compression sample and preparation method thereof |
| US8778801B2 (en) * | 2012-09-21 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming seed layer structure |
| CN103887232B (en) * | 2014-04-04 | 2016-08-24 | 华进半导体封装先导技术研发中心有限公司 | The method improving the metal filled uniformity of TSV |
| KR20220042652A (en) * | 2020-09-28 | 2022-04-05 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method of semiconductor device |
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| CN101483149A (en) * | 2009-02-13 | 2009-07-15 | 华中科技大学 | Production method for through wafer interconnection construction |
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| 封国强 等.一种低成本的硅垂直互连技术.《半导体技术》.2006,第31卷(第10期),766-781. * |
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