CN101661895A - Z-direction lamination encapsulating method - Google Patents
Z-direction lamination encapsulating method Download PDFInfo
- Publication number
- CN101661895A CN101661895A CN200910184131A CN200910184131A CN101661895A CN 101661895 A CN101661895 A CN 101661895A CN 200910184131 A CN200910184131 A CN 200910184131A CN 200910184131 A CN200910184131 A CN 200910184131A CN 101661895 A CN101661895 A CN 101661895A
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- Prior art keywords
- bonding
- chip
- solder joint
- ball
- welding point
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
The invention provides a superimposed forward direction bonding method, which provides lower camber height and less neck damages compared with the traditional forward direction bonding method. Compared with reverse ball bonding, the method reduces damage of bonding region on sensitive chips, and increases yield. The method is characterized in that the maximum camber height of the device is not more than the thickness of the chip for keeping the optimum gap between ring-shaped layers; a Bump ball mode is used in connecting the chips, namely, firstly a golden ball is made on a second welding point; and then a gold thread is connected to the second welding point from a first welding point by normal bonding mode; and the position accuracy of each golden ball is 3 um.
Description
(1) technical field
The present invention relates to the chip-stack technical field, be specially the Z direction lamination encapsulating method.
(2) background technology
Common three-dimension packaging is carried out lamination to two or more chips exactly in single encapsulation.The initial form of laminated type chip encapsulation technology is the lamination of two, three and four lead-in wire bondings, and among the lead-in wire bonding lamination that is used for five, six of low volume production and more a plurality of laminations also researching and developing.Configuration under the laminated type chip typical situation is pyramid or lamination with same size of cantilever-designed.The laminated type chip encapsulation technology is driving a lot of fields Development of Packaging Technology, comprises ultralow radian gold thread bonding techniques, disk thinning technique, thin substrate and low viscosity molding technology.Stacked package is the steric linkage technology of Z direction in the technology of Wire Bond most critical, comprise the gold thread bonding techniques between ultralow radian gold thread bonding techniques and chip and the chip, one, the complexity that increases of ultralow radian gold thread bonding techniques limitation in height and stack technology configuration proposed special challenge to the gold thread bonding techniques in laminated chips is used.The requirement of low radian gold thread bonding techniques has promoted the continuous growth that reverse bonding techniques uses.The forward bonding technical process of standard, see Fig. 3, at first chopper being placed on the chip, is first solder joint with the chip bonding district, and pin is the order bonding of second solder joint, 8 are respectively chip for gold thread, 10 for bonding region, 11,12 for solder joint, 9, bonding technology then places chopper in the chip bonding district earlier in the other direction, make a call to after the gold goal earlier, and be first solder joint with pin again, the chip bonding district is the order bonding of second solder joint, and second solder joint is got on the gold goal.
In present several application, the bonding technology of many employings standard, because the bonding technology speed of standard is faster than reciprocal, and can genuine thinner spacing.But the bonding technology of standard is subjected to the constraint of camber aspect.And excessive counter drawing can be caused the neck crackle above the gold goal, and these crackles have caused integrity problem.
(3) summary of the invention
It is legal to the invention provides a kind of superposed type positive key, its except provide damage than the low camber of traditional forward bonding and less neck, compare with reverse ball bonding, reduced the bonding region damage on the sensitive chip, also improved output.
Its technical scheme is such: it is characterized in that: the camber of device maximum should not be higher than the thickness of the chip that keeps the best slit between the annulate lamella; When carrying out being connected of chip and chip chamber, use Bump ball pattern, promptly earlier make a call to a gold goal, and then gold thread is connected to second solder joint from first solder joint with the pattern of normal bonding at second solder joint.
It is further characterized in that: the positional precision 3um of each gold goal.
In the said method of the present invention, the camber of device maximum, the thickness that should not be higher than the chip that keeps the best slit between the annulate lamella, on second solder joint because gold goal arranged, therefore being provided with in the parameter of making a call to second solder joint can be more much smaller than normal bonding pattern, when this has just guaranteed to make a call to second solder joint effectively the chip under the aluminium lamination itself is not had too much influence.Because in the low distortion of first solder joint, superposed type forward method also provides the more ability of thin space of ratio inverse ball bonding, in using, this can obtain being lower than the camber of 75um.
(4) description of drawings
Fig. 1 is a pyramid laminated type Chip Packaging form structure schematic diagram;
Fig. 2 is the laminated type Chip Packaging form structure schematic diagram with same size of cantilever-designed;
Fig. 3 is the schematic diagram of the forward bonding technology of existing standard;
Fig. 4 is the schematic diagram of forward bonding of the present invention.
(5) embodiment
See Fig. 1, Fig. 2, Fig. 4, in the processing technology of the present invention, the camber 7 of device maximum should not be higher than the thickness of the chip 2,4 that keeps the best slit between the annulate lamella; When carrying out being connected of chip 12 and 11 of chips, use Bump ball pattern, promptly earlier make a call to a gold goal 10, and then gold thread is connected to second solder joint 10 from first solder joint 8 with the pattern of normal bonding at second solder joint; The positional precision 3um of each gold goal 8,10,9 is gold thread, and 1 is the bonding wire of top chip, and 3 is outside plastic packaging, and 5 is that substrate, 6 is plug-in unit.
Claims (2)
1, Z direction lamination encapsulating method is characterized in that: the camber of device maximum should not be higher than the thickness of the chip that keeps the best slit between the annulate lamella; When carrying out being connected of chip and chip chamber, use Bump ball pattern, promptly earlier make a call to a gold goal, and then gold thread is connected to second solder joint from first solder joint with the pattern of normal bonding at second solder joint.
2, according to the described Z direction lamination encapsulating method of claim 1, it is characterized in that: the positional precision 3um of each gold goal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910184131A CN101661895A (en) | 2009-08-25 | 2009-08-25 | Z-direction lamination encapsulating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910184131A CN101661895A (en) | 2009-08-25 | 2009-08-25 | Z-direction lamination encapsulating method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101661895A true CN101661895A (en) | 2010-03-03 |
Family
ID=41789821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910184131A Pending CN101661895A (en) | 2009-08-25 | 2009-08-25 | Z-direction lamination encapsulating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101661895A (en) |
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2009
- 2009-08-25 CN CN200910184131A patent/CN101661895A/en active Pending
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| PB01 | Publication | ||
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Application publication date: 20100303 |