CN101659034B - Method for performing chemical-mechanical polishing (cmp) - Google Patents
Method for performing chemical-mechanical polishing (cmp) Download PDFInfo
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- CN101659034B CN101659034B CN2009101659833A CN200910165983A CN101659034B CN 101659034 B CN101659034 B CN 101659034B CN 2009101659833 A CN2009101659833 A CN 2009101659833A CN 200910165983 A CN200910165983 A CN 200910165983A CN 101659034 B CN101659034 B CN 101659034B
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Images
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Crystallography & Structural Chemistry (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing. The invention method is simple and has economic benefit, does not reduce the gate height due to over-polishing and decreases the risk of damaging the lower layer mask in the chemical-mechanical polishing art.
Description
Technical field
The present invention relates to the manufacturing of semiconductor device, particularly employed chemical mechanical milling tech in semiconductor is made.
Background technology
Semiconductor integrated circuit (IC) industry has experienced the growth of too fast speed.It is new that the technological progress of IC material and design makes that the production of IC ceaselessly pushes away from generation to generation, and each from generation to generation all more preceding has littler component size and more complicated circuit from generation to generation.The technology of this microization can increase prouctiveness usually and lower relevant cost is provided.Such microization also produces higher relatively power consumption (power dissipation) value, and it can use the device of low power consumption, and for example CMOS complementary metal-oxide-semiconductor (CMOS) device adapts to.The CMOS device is formed by gate oxide and polysilicon gate electrode.Therefore, along with component size is constantly dwindled, expected to use high dielectric constant grid dielectric medium and metal gate electrode to replace gate oxide and polysilicon gate electrode, to promote the usefulness of element.A method that has been used is to be called last (gate last) technology of grid or grid displacement (gate replacement) technology.In gate last process, form void earlier and put the polycrystalline grid, and can carry out general CMOS manufacturing process then, up to deposition interlayer dielectric (interlayer dielectric; ILD).Generally can on interlayer dielectric layer, carry out cmp, put the polycrystalline grid to expose void.Removable then void is put the polycrystalline grid, and replaces with the metal gates that is fit to.Yet, found that general chemical mechanical milling tech has the problem of control gate height, and may cause defective the tunic of below.This can cause not good device usefulness and lower wafer yield (wafer yield).
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides a kind of method of carrying out cmp, comprise: processing semiconductor substrate, on this substrate, to form a nominal grid structure, on this nominal grid structure, form a hard mask, and on this hard mask, form an interlayer dielectric layer; Carry out one first chemical mechanical milling tech with one first slurry, to modify the contoured surface of this its non-flat forms of interlayer dielectric layer; Carry out one second chemical mechanical milling tech with one second slurry, to remove this hard mask; And carry out one the 3rd chemical mechanical milling tech with one the 3rd slurry, to remove a boundary layer, this boundary layer is formed in this semiconductor technology between this nominal grid and this hard mask.
The present invention also provides a kind of method of carrying out cmp on the semiconductor substrate, this semiconductor substrate has a nominal grid formed thereon, be formed at the hard mask of one on this nominal grid and be formed at a contact etch stop layer and an interlayer dielectric layer on this hard mask, this method comprises: carry out one first chemical mechanical milling tech with one first slurry, with this interlayer dielectric layer of planarization; Carry out one second chemical mechanical milling tech with one second slurry, to remove this contact etch stop layer and this hard mask; And carry out one the 3rd chemical mechanical milling tech with one the 3rd slurry, to remove a boundary layer, this boundary layer is formed in semiconductor technology between this nominal grid and this hard mask.
The present invention also provides a kind of method of carrying out multi-platform (multi-platen) cmp, comprise: processing semiconductor substrate, with in form a nominal grid on this substrate, in forming a hard mask on this nominal grid and formation one contact etch stop layer and an interlayer dielectric layer on this substrate that comprises this hard mask; Carry out one first chemical mechanical milling tech with this interlayer dielectric layer of planarization, this first chemical mechanical milling tech uses one first platform and one first slurry; Carry out one second chemical mechanical milling tech to remove this etching stopping layer and this hard mask, this second chemical mechanical milling tech uses one second platform and one second slurry, and this second slurry has the selection ratio greater than about 20; And carry out one the 3rd chemical mechanical milling tech to remove a boundary layer, this boundary layer is formed in this semiconductor technology between this nominal grid and this hard mask, the 3rd chemical mechanical milling tech uses one the 3rd platform and one the 3rd slurry, and the 3rd slurry has the selection ratio greater than about 3.
Method of the present invention provides the method for carrying out chemical mechanical milling tech in gate last process, its simple and tool economic benefit.Therefore can in gate last process, control gate height accurately, and can not cross the height that grinds and reduce grid.Also reduced the risk of tunic below in chemical mechanical milling tech, damaging.Therefore, the usefulness of device can become more measurable and stable.In addition, production cost can be reduced, and the wafer production capacity can be improved.
Description of drawings
Fig. 1 is the vertical view of the rotary grinding system of cmp of an embodiment.
Fig. 2 is for showing the method flow diagram of each conception of species according to the present invention.
Fig. 3 A to Fig. 3 E is the process section according to the semiconductor device in the method for an embodiment.
Description of reference numerals in the above-mentioned accompanying drawing is as follows:
The rotary grinding system of 100～cmp; 102～stand; 104～stand; 106～stand; 108～stand; 110～mechanical arm; 300～semiconductor device; 302～zone (or transistor); 304～zone (or transistor); 306～semiconductor substrate; 308～isolation structure; 312～gate dielectric; 314～gate dielectric; 322～stop or protective layer; 324～stop or protective layer; 332～void is put the polycrystalline grid structure; 334～void is put the polycrystalline grid structure; 342～hard mask; 344～hard mask; 360～contact etch stop layer; 370～interlayer dielectric layer; 375～chemical mechanical milling tech; 385～chemical mechanical milling tech; 390～boundary layer; 395～chemical mechanical milling tech; S1～slurry; S2～slurry; S3～slurry; P1～platform; P2～platform; P3～platform.
The specific embodiment
About manufacturing and the occupation mode of each embodiment is as detailed in the following.Yet, it should be noted that, various applicable inventive concept provided by the present invention is to implement according to this according to the various variations of literary composition in concrete, and only is to be used for showing specifically using and making method of the present invention at this specific embodiment of discussing, and not in order to limit the scope of the invention.Below by various accompanying drawings and illustrate the manufacture process of preferred embodiment of the present invention.In various various embodiment of the present invention and accompanying drawing, the identical identical or similar elements of mark representative.In addition, when the layer of material layer is when being positioned on another material layer or the substrate, it can be to be located immediately at its surface to go up or be inserted with in addition other intermediary layers.
Fig. 1 is the vertical view of the rotary grinding system of the cmp of an embodiment (CMP rotary polishersystem) 100.System 100 can comprise four station systems (four-station system), wherein a station 102 is in order to be written into (loading) and to carry (unloading), and other three stations 104,106,108 comprise that platform (for example, platform P1, platform P2, platform P3), with the separate operation chemical mechanical milling tech, it will be in hereinafter explanation.System 100 can more comprise mechanical arm (robot arm) 110, and it can be in order to transmit substrate to another station from a station, and for instance, aforesaid substrate is a semiconductor wafer.Understand system 100 and can comprise other elements, for example block casket (cassette) and input/output module, yet understand for the easier quilt of the inventive concept that makes this explanation, with its simplification.In addition, without departing from the spirit and scope of the present invention, also can use station, the platform with other structures, the chemical machinery polishing system that reaches machinery.
Fig. 2 is for showing the flow chart of the method 200 of each conception of species according to the present invention, and it carries out chemical mechanical milling tech on semiconductor device in last (gate last) technology of grid.Fig. 3 A to Fig. 3 E is the semiconductor technology profile according to the method 200 of Fig. 2.Can use (Fig. 1's) system 100 to carry out method 200.In gate last process, the void that can form device is earlier put the polycrystalline grid, and then can carry out the CMOS manufacturing process to form various structures (for example, grid structure, light dope source electrode/drain electrode (lightlydoped source/drain; LDD) zone, side wall spacer (sidewall spacer), heavy doping source electrode/drain region, metal silication element etc.), up on device, depositing interlayer dielectric (interlayerdielectric; ILD).
Method 200 originates in step 210, can process semiconductor substrate, put the polycrystalline grid structure on substrate, to form void, put in void and form hard mask on the polycrystalline grid structure, and on the substrate that comprises hard mask, form contact etch stop layer (contact etch stop layer; CESL) and interlayer dielectric.
In Fig. 3 A, semiconductor device 300 can comprise zone 302 and 304, and in wherein forming various microelectronic devices, it is the part of integrated circuit.Understand semiconductor device 300 and can comprise that storage arrangement (includes but not limited to static RAM (static random access memory; SRAM)), logic device (includes but not limited to mos field effect transistor (metal-oxide semiconductor field-effect transistor; And/or other devices MOSFET)).In one embodiment, zone 302 can comprise N type slot field-effect transistor (N-channel field effecttransistor; NFET), and the zone 304 can comprise P type slot field-effect transistor (P-channel fieldeffect transistor; PFET). Transistor 302 and 304 can form by the CMOS manufacturing process, therefore at this some technology of brief explanation and element.
Transistor 302,304 can comprise gate dielectric 312,314 separately.Gate dielectric 312,314 can comprise high-k dielectric materials, for example hafnium oxide (hafnium oxide; HfO
2).Perhaps, gate dielectric 312,314 optional other high-k dielectric materials that comprise, for example hafnium silicon oxide (hafnium silicon oxide; HfSiO), hafnium silicon oxynitride (hafnium silicon oxynitride; HfSiON), hafnium oxide tantalum (hafnium tantalum oxide; HfTaO), hafnium oxide titanium (hafniumtitanium oxide; HfTiO), hafnium oxide zirconium (hafnium zirconium oxide; HfZrO), reach above-mentioned combination.Gate dielectric 312,314 also can be formed on the boundary layer (interfacial layer), and above-mentioned boundary layer can for example be an oxide layer.Moreover transistor 302,304 can more comprise cover layer (cappinglayer), with the work function of modulation (gate electrode) metal level, with suitable nFET 302 and the pFET 304 of showing as respectively.For instance, cover layer can comprise lanthana (lanthanum oxide; LaO
x), aluminium oxide (aluminum oxide; AlO
x), magnesia (magnesium oxide; MgO
x) or other suitable materials.
Transistor 302,304 can more comprise separately and stops or protective layer 322,324 that it is formed at respectively on the gate dielectric 312,314.Barrier layer 322,324 can comprise TiN, TaN or other suitable materials.Transistor 302,304 can comprise more separately that void puts polycrystalline grid structure 332,334, and it is formed at respectively on the barrier layer 322,324.Hard mask 342,344 can be formed at respectively on the polycrystalline structure 332,334.Hard mask 342,344 can comprise SiN, SiON, SiC, SiOC/PEOX, TEOS or other suitable materials.Understand transistor 302,304 and can comprise various elements, for example side wall spacer; Regions and source, it comprises light dope source electrode/drain region and heavy doping source electrode/drain region; The metal silication element; And other known elements.
In substrate 306, form after various microelectronic devices and the element, can on transistor 302,304, form stressor layers (stressed layer), for example contact etch stop layer (contact etch stop layer; CESL) 360.Contact etch stop layer 360 can be formed by silicon nitride, silicon oxynitride, carborundum, silicon oxide carbide or other suitable materials.Can form dielectric layer on contact etch stop layer 360, for example interlayer dielectric layer 370, and the formation method can be chemical vapour deposition (CVD), high density plasma CVD, rotation coating, sputter or other suitable methods.Interlayer dielectric layer 370 can be between device 302,304 with substrate 306 on other zones in upwards the filling of compliance.Interlayer dielectric layer 370 can comprise PSG, BPSG, SiO
2, TEOS or other suitable materials.As discussed previously, in gate last process, the void of transistor 302,304 is put polycrystalline grid structure 332,334 and can be removed by the selectivity etch back process, makes it possible to form the proper metal grid, puts the polycrystalline grid structure to replace void.Therefore, can pass through chemical mechanical milling tech planarization interlayer dielectric layer 370, up to arriving empty top of putting polycrystalline grid structure 332,334, it will be in hereinafter describing in detail.
Method 200 proceeds to step 220, can use first slurry and first platform (platform P1/ slurry S1 as shown in fig. 1), and semiconductor substrate is carried out first chemical mechanical milling tech.In Fig. 3 B, can on interlayer dielectric layer 370, carry out first chemical mechanical milling tech 375, removing the part interlayer dielectric layer, and the planarization interlayer dielectric layer.Also promptly, after depositing operation, initial interlayer dielectric layer 370 can have the surface (surface) or the contoured surface (topography) of non-flat forms.Therefore can carry out first chemical mechanical milling tech 375, to reach smooth-going (smooth) and smooth (planar) surface for following illustrated next chemical mechanical milling tech.
In general, slurry comprises little, abrasion (abrasive) particle of specific dimensions and shape, and it is suspended in the aqueous solution.Abrasive particle substantially can be the same with the tunic that will grind hard.Can be according to the material that will grind, with adding in the solution of acid or alkali optional.Grinding rate can be subjected to the influence of various slurry parameters, for example concentration of solid particle and slurry coating of particles, size and distribution in the chemical composition of slurry solution, the slurry.Can use of the transmission of automatic grinding slurry feed system to guarantee that slurry is suitable.
Because first chemical mechanical milling tech 375 that carries out on interlayer dielectric layer 370 reaches smooth and smooth-going surface, therefore first slurry does not need to have any selection than (selectivity).First slurry can comprise abrasive particle, for example (fumed) silica (silica of gas phaseization; SiO
2), it is in the aqueous solution.The aqueous solution can comprise alkali metal (alkaline) solution or other suitable solution.Therefore, the pH value scope of first slurry can be between about 9 to about 12.The silica granules size range can be between about 2nm to about 50nm.Moreover first slurry can comprise silica, and its proportion is between about 10% to about 25%.Perhaps, the optional aluminium oxide (alumina that comprises of first slurry; Al
2O
3).
First chemical mechanical milling tech 375 can comprise following technological parameter.The speed of rotation of first platform (rotational speed), its scope can be between about 80rpm (per minute rotation number) to about 120rpm.Available grinding pressure between the semiconductor device 300 and first platform, its scope between about 1.5psi (PSI) to about 5psi.First slurry can about 250ml/min (per minute milliliter) speed be disseminated on first platform.First chemical mechanical milling tech 375 can comprise the arranged grinding technics time (timed polishing process), and its scope was between about 60 to about 90 seconds.Perhaps, first chemical mechanical milling tech 375 can use known end-point detecting system (endpoint detection system), to stop first chemical mechanical milling tech.Found 375 pairs of interlayer dielectric layers 370 of first chemical mechanical milling tech remove speed be about 2200 dusts/minute.Understand and specific remove speed and can change according to the composition of first slurry and the parameter of first chemical mechanical milling tech.
Method 200 proceeds to step 230, can use second slurry and second platform (platform P2/ slurry S2 as shown in fig. 1), and semiconductor substrate is carried out second chemical mechanical milling tech.In certain embodiments, can be in the station (station) between platform P1 and the platform P2, in the washed with de-ionized water of semiconductor device 300 enterprising line options or similar wet-cleaned.In Fig. 3 C, can on semiconductor device 300, carry out second chemical mechanical milling tech 385, stop layer 360 to remove contact hole etching, and remove the hard mask 342,344 of transistor 302,304 respectively.
Because second chemical mechanical milling tech 385 that carried out removes hard mask 342,344, and stops then, therefore second slurry can comprise that one selects ratio, and (oxide: silicon nitride (oxide: SiN)) is greater than about 20 for oxide and silicon nitride for they.Second slurry can comprise abrasive particle, for example cerium oxide (ceriumoxide; CeO
2), it is in the aqueous solution.The pH value scope of second slurry can be between about 4 to about 10.The particle size range of cerium oxide can be between about 2nm to about 50nm.Moreover second slurry can comprise cerium oxide, and its proportion is between about 0.1% to about 8%.
Second chemical mechanical milling tech 385 can comprise following technological parameter.The speed of rotation of second platform, its scope can be between about 60rpm (per minute rotation number) to about 120rpm.Available grinding pressure between the semiconductor device 300 and second platform, its scope between about 1.5psi (PSI) to about 5psi.Second slurry can about 250ml/min (per minute milliliter) speed be disseminated on second platform.Second chemical mechanical milling tech 385 can comprise the arranged grinding technics time, and its scope was between about 200 to about 400 seconds.Yet, the milling time cycle that also can use other.Perhaps, second chemical mechanical milling tech 385 can use known end-point detecting system, to stop second chemical mechanical milling tech.Found 385 pairs of oxides of second chemical mechanical milling tech remove speed be about 3600 dusts/minute, and to silicon nitride (SiN) remove speed be about 130 dusts/minute.Understand and specific remove speed and can change according to the composition of second slurry and the parameter of second chemical mechanical milling tech.
Method 200 proceeds to step 240, can use the 3rd slurry and the 3rd platform (platform P3/ slurry S3 as shown in fig. 1), and semiconductor substrate is carried out the 3rd chemical mechanical milling tech.In certain embodiments, can be in the station between platform P2 and the platform P3, in the washed with de-ionized water of semiconductor device 300 enterprising line options or similar wet-cleaned.Found boundary layer 390 in the CMOS manufacturing process, be formed at void and put between polycrystalline grid 332,334 and the hard mask 342,344.In other words, seemingly (oxide-like) boundary layer of oxide is in the technology of semiconductor device 300, is formed between (void is put the polycrystalline grid) polysilicon layer and (hard mask) silicon nitride layer.Therefore, carrying out second chemical mechanical milling tech 385 with after removing hard mask 342,344, boundary layer 390 can expose, and puts polycrystalline grid structure 332,334 and cover void.In Fig. 3 D, can on semiconductor device 300, carry out the 3rd chemical mechanical milling tech 395 to remove boundary layer 390.
Because the 3rd chemical mechanical milling tech 395 that is carried out is the boundary layers 390 that remove like oxide, therefore the 3rd slurry can comprise that one selects ratio, and it is for polycrystalline thing (poly) and oxide (poly: be greater than about 3 oxide).The 3rd slurry can comprise abrasive particle, for example (fumed) silica (silica of gas phaseization; SiO
2), it is in the aqueous solution.The aqueous solution can comprise alkali metal soln (alkaline solution) or other suitable alkaline solutions (basic solution).Therefore, the pH value scope of the 3rd slurry can be between about 9 to about 12.The silica granules size range can be between about 2nm to about 50nm.Moreover the 3rd slurry can comprise silica, and its proportion is between about 0.5% to about 12%.
The 3rd chemical mechanical milling tech 395 can comprise following technological parameter.The speed of rotation of the 3rd platform, its scope can be between about 40rpm (per minute rotation number) to about 90rpm.Available grinding pressure between semiconductor device 300 and the 3rd platform, its scope between about 0.3psi (PSI) to about 3psi.The 3rd slurry can about 250ml/min (per minute milliliter) speed be disseminated on the 3rd platform.The 3rd chemical mechanical milling tech 395 can comprise the arranged grinding technics time, and its scope was between about 5 seconds to about 15 seconds.Yet, the milling time cycle that also can use other.Perhaps, the 3rd chemical mechanical milling tech 395 can use known end-point detecting system, to stop the 3rd chemical mechanical milling tech.Found 395 pairs of polycrystalline things of the 3rd chemical mechanical milling tech remove speed be about 1600 dusts/minute, and to oxide remove speed be about 490 dusts/minute.Understand and specific remove speed and can change according to the composition of the 3rd slurry and the parameter of the 3rd chemical mechanical milling tech.
After carrying out the 3rd chemical mechanical milling tech 395, can go out in 100 years in the process of semiconductor device 300 from (Fig. 1's) chemical machinery polishing system, the wafer of choosing wantonly cleans and platform cleans.Moreover the top surface that void is put polycrystalline grid structure 332,334 exposes and is ready to and is removed.In addition, can accurately control the gate height of transistor 302,304, do not ground (over-polishing) and reduce gate height and can not cross.
Method 200 proceeds to step 250, and removable void is put polycrystalline grid structure 332,334, and replaces with metal gates.For instance, void is put the polycrystalline grid structure and can be removed by etch process, forms groove whereby, and can one or more metal level filling groove (grid).Polysilicon optionally removes by being exposed in the solution (for example ammonium hydroxide) that contains hydroxyl ion, deionized water and/or other solution that is fit to.Afterwards, can carry out extra technology, for example on metal level, carry out cmp to finish the manufacturing of semiconductor device; Form contact hole (contact)/interlayer hole (via); Form the multiple layer inner connection structure, it comprises metal level and interlayer dielectric; Form protective layer etc.
In Fig. 3 E, finished spendable method 200 in invention, wherein have only a types of devices (for example nFET or pFET) to hold the void of (side) to put the polycrystalline grid and expose.For instance, can carry out method 200, close and stay the nFET device end only to open the pFET device end.In other words, the void that can expose in the pFET device end is put polycrystalline grid 334, and stays part contact etch stop layer 360 and hard mask 342 in the nFET device end.Afterwards, can carry out chemical mechanical milling tech to open the nFET device end.In other examples, can carry out method 200 only to open the nFET device end, close and stay the pFET device end.Therefore, the void that can expose in the nFET device end is put the polycrystalline grid, and stays part contact etch stop layer and hard mask in the pFET device end.Afterwards, can carry out chemical mechanical milling tech to open the pFET device end.
In addition, can consider various additives are added in the slurry described herein.In certain embodiments, additive can comprise organic additive, for example organic acid, ethylenediamine tetra-acetic acid (ethyene diaminetetraacetic acid; EDTA), interfacial agent (surfactant), and chelating agent.In other embodiments, additive can comprise inorganic additive, and for example acid (acid)/alkali metal (alkali) buffer and ion are strengthened (ionic strength) agent.In other embodiments, select to add in the slurry described herein than control (selectivity control) agent.Selection can comprise interfacial agent (F-rich surfactant), and the interfacial agent (OH-rich surfactant) of rich hydroxyl ion of the interfacial agent (C-richsurfactant) of rich carbon, rich fluorine than controlling agent.In addition, in another embodiment again, abrasive particle can comprise various kinds, for example (fumed) of gas phaseization, colloid (colloidal), and (for example mixed polymerization abrasion thing (hybridpolymer abrasive)) that mix.
In a word, method described herein can be used in the grid replacing process of the gate stack with high contoured surface (high-topography) (it comprises nominal grid technology).Contact etch stop layer and interlayer dielectric layer can be deposited on the device (nFET and pFET, or NMOS and PMOS, or CMOS), and the recess between the filling device.The first, can on interlayer dielectric layer, use contoured surface slurry (topographyslurry), to reach the surface of smooth and low fluctuating.The second, can use high flat degree slurry (highplanarity slurry), to remove contact etch stop layer and the hard mask on the nominal grid.The 3rd, can use optionally slurry (selective slurry), modifying the nominal grid surface, and remove in semiconductor fabrication formed boundary layer between nominal grid and hard mask.Therefore, method described herein provide gate last process a kind of control and uniformly nominal grid remove technology.
Therefore, a kind of method of carrying out cmp comprises processing semiconductor substrate, on this substrate, to form a nominal grid structure, on this nominal grid structure, form a hard mask, and on this hard mask, form an interlayer dielectric layer, carry out one first chemical mechanical milling tech with one first slurry, to modify the contoured surface of this its non-flat forms of interlayer dielectric layer, carry out one second chemical mechanical milling tech with one second slurry, to remove this hard mask, and carry out one the 3rd chemical mechanical milling tech with one the 3rd slurry, to remove a boundary layer, this boundary layer is formed in this semiconductor technology between this nominal grid and this hard mask.In certain embodiments, this first slurry comprises silica (silica; SiO
2), its proportion is between about 10% to about 25%, and pH value scope is between about 9 to about 12.In other embodiments, this first chemical mechanical milling tech comprise the slurry of about 250ml/min scatter speed, scope between about 80rpm to the speed of rotation of about 120rpm, scope between about 1.5psi extremely the grinding pressure of about 5psi and scope between about 60 seconds one of them in about 90 seconds time cycle extremely.In some other embodiment, this first slurry does not have the ratio of selection.
In another embodiment again, this second slurry comprises cerium oxide (cerium oxide; CeO
2), its proportion is between about 0.1% to about 8%, and pH value scope is between about 4 to about 10.In certain embodiments, this second chemical mechanical milling tech comprise the slurry of about 250ml/min scatter speed, scope between about 60rpm to the speed of rotation of about 120rpm, scope between about 1.5psi extremely the grinding pressure of about 5psi and scope between about 200 seconds one of them in about 400 seconds time cycle extremely.In other embodiments, this second slurry has the selection ratio greater than about 20.In certain other embodiments, the 3rd slurry comprises silica (silica; SiO
2), its proportion is between about 0.5% to about 12%, and pH value scope is between about 9 to about 12.In other embodiments, the 3rd chemical mechanical milling tech comprise the slurry of about 250ml/min scatter speed, scope between about 40rpm to the speed of rotation of about 90rpm, scope between about 0.3psi extremely the grinding pressure of about 3psi and scope between about 5 seconds one of them in about 15 seconds time cycle extremely.In other embodiment again, the 3rd slurry has the selection ratio greater than about 3.
A kind of method of carrying out cmp on the semiconductor substrate also is provided, and this semiconductor substrate has a nominal grid formed thereon, be formed at the hard mask of one on this nominal grid and be formed at a contact etch stop layer and an interlayer dielectric layer on this hard mask.This method comprises with one first slurry carries out one first chemical mechanical milling tech, with this interlayer dielectric layer of planarization, carry out one second chemical mechanical milling tech with one second slurry, to remove this contact etch stop layer and this hard mask, and carry out one the 3rd chemical mechanical milling tech with one the 3rd slurry, to remove a boundary layer, this boundary layer is formed in semiconductor technology between this nominal grid and this hard mask.In certain embodiments, this first slurry comprises silica (silica; SiO
2), its proportion is between about 10% to about 25%, and pH value scope is between about 9 to about 12.In other embodiments, this second slurry comprises cerium oxide (cerium oxide; CeO
2), its proportion is between about 0.1% to about 8%, and pH value scope is between about 4 to about 10.In certain other embodiments, the 3rd slurry comprises silica (silica; SiO
2), its proportion is between about 0.5% to about 12%, and pH value scope is between about 9 to about 12.In other embodiment again, this first, second, and the 3rd slurry comprise in the interfacial agent of the interfacial agent of organic acid, EDTA, interfacial agent, chelating agent, acid/alkali metal buffer, ion hardening agent, the interfacial agent of rich carbon, rich fluorine and rich hydroxyl ion one of them separately.In certain embodiments, this method more is included in carries out removing this nominal grid after the 3rd chemical mechanical milling tech, and replaces with a metal gates.
In addition, a kind of method of carrying out multi-platform (multi-platen) cmp is provided, it comprises processing semiconductor substrate, on this substrate, to form a nominal grid, on this nominal grid, form a hard mask, and on this substrate that comprises this hard mask, form a contact etch stop layer and an interlayer dielectric layer, carry out one first chemical mechanical milling tech with this interlayer dielectric layer of planarization, this first chemical mechanical milling tech uses one first platform and one first slurry, carry out one second chemical mechanical milling tech to remove this etching stopping layer and this hard mask, this second chemical mechanical milling tech uses one second platform and one second slurry, this second slurry has the selection ratio greater than about 20, and carry out one the 3rd chemical mechanical milling tech to remove a boundary layer, this boundary layer is formed in this semiconductor technology between this nominal grid and this hard mask, the 3rd chemical mechanical milling tech uses one the 3rd platform and one the 3rd slurry, and the 3rd slurry has the selection ratio greater than about 3.In certain embodiments, this second slurry has the ratio of selection for oxide and nitride.In other embodiments, the 3rd slurry has the ratio of selection for polysilicon and oxide.In other embodiment again, this first slurry comprises silica (silica; SiO2), its proportion is between about 10% to about 25%, and pH value scope is between about 9 to about 12, and this second slurry comprises cerium oxide (cerium oxide; CeO
2), its proportion is between about 0.1% to about 8%, and the pH value is between about 4 to about 10; And the 3rd slurry comprise silica (silica; SiO
2), its proportion is between about 0.5% to about 12%, and the pH value is between about 9 to about 12.
The present invention various embodiment described herein have different benefits.For instance, method of the present invention provides the method for carrying out chemical mechanical milling tech in gate last process, its simple and tool economic benefit.Therefore can in gate last process, control gate height accurately, and can not cross the height that grinds and reduce grid.Also reduced the risk of tunic below in chemical mechanical milling tech, damaging.Therefore, the usefulness of device can become more measurable and stable.In addition, production cost can be reduced, and the wafer production capacity can be improved.Understand said different embodiment and have different benefits, and all embodiment might not need special benefit.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the scope that claim defined.For instance, though method described herein is to use in " grid is last " technology, and described method also can be used in the hybrid technique, and above-mentioned hybrid technique comprises grid technology and gate last process at first.In other words, the metal gates of some devices (for example NMOS or PMOS device) can form in the technology at first at grid, and some other device (for example PMOS or NMOS device) can form in gate last process.
Claims (15)
1. method of carrying out cmp comprises:
Processing semiconductor substrate to form a nominal grid structure on this substrate, forms a hard mask on this nominal grid structure, and forms an interlayer dielectric layer on this hard mask;
Carry out one first chemical mechanical milling tech with one first slurry, to modify the contoured surface of this its non-flat forms of interlayer dielectric layer;
Carry out one second chemical mechanical milling tech with one second slurry, to remove this hard mask; And
Carry out one the 3rd chemical mechanical milling tech with one the 3rd slurry, to remove a boundary layer, this boundary layer is formed in this semiconductor technology between this nominal grid and this hard mask.
2. method of carrying out cmp as claimed in claim 1, wherein this first slurry comprises silica, its proportion is between 10% to 25%, and pH value scope is between 9 to 12.
3. method of carrying out cmp as claimed in claim 2, wherein this first chemical mechanical milling tech comprises that the slurry of 250ml/min scatters speed, scope between the speed of rotation of 80rpm to 120rpm, scope grinding pressure and scope one of them in 60 seconds to 90 seconds time cycle between 1.5psi to 5psi.
4. method of carrying out cmp as claimed in claim 2, wherein this first slurry does not have the ratio of selection.
5. method of carrying out cmp as claimed in claim 1, wherein this second slurry comprises cerium oxide, its proportion is between 0.1% to 8%, and pH value scope is between 4 to 10.
6. method of carrying out cmp as claimed in claim 4, wherein this second chemical mechanical milling tech comprises that the slurry of 250ml/min scatters speed, scope between the speed of rotation of 60rpm to 120rpm, scope grinding pressure and scope one of them in 200 seconds to 400 seconds time cycle between 1.5psi to 5psi.
7. method of carrying out cmp as claimed in claim 4, wherein this second slurry has the selection ratio greater than 20.
8. method of carrying out cmp as claimed in claim 1, wherein the 3rd slurry comprises silica, its proportion is between 0.5% to 12%, and pH value scope is between 9 to 12.
9. method of carrying out cmp as claimed in claim 6, wherein the 3rd chemical mechanical milling tech comprises that the slurry of 250ml/min scatters speed, scope between the speed of rotation of 40rpm to 90rpm, scope grinding pressure and scope one of them in 5 seconds to 15 seconds time cycle between 0.3psi to 3psi.
10. method of carrying out cmp as claimed in claim 6, wherein the 3rd slurry has the selection ratio greater than 3.
11. method of on the semiconductor substrate, carrying out cmp, this semiconductor substrate has a nominal grid formed thereon, be formed at the hard mask of one on this nominal grid and be formed at a contact etch stop layer and an interlayer dielectric layer on this hard mask, and this method comprises:
Carry out one first chemical mechanical milling tech with one first slurry, with this interlayer dielectric layer of planarization;
Carry out one second chemical mechanical milling tech with one second slurry, to remove this contact etch stop layer and this hard mask; And
Carry out one the 3rd chemical mechanical milling tech with one the 3rd slurry, to remove a boundary layer, this boundary layer is formed in semiconductor technology between this nominal grid and this hard mask.
12. method of carrying out cmp on semiconductor substrate as claimed in claim 11 more is included in and carries out removing this nominal grid after the 3rd chemical mechanical milling tech, and replaces with a metal gates.
13. a method of carrying out multi-platform cmp comprises:
Processing semiconductor substrate, with in form a nominal grid on this substrate, in forming a hard mask on this nominal grid and formation one contact etch stop layer and an interlayer dielectric layer on this substrate that comprises this hard mask;
Carry out one first chemical mechanical milling tech with this interlayer dielectric layer of planarization, this first chemical mechanical milling tech uses one first platform and one first slurry;
Carry out one second chemical mechanical milling tech to remove this etching stopping layer and this hard mask, this second chemical mechanical milling tech uses one second platform and one second slurry, and this second slurry has the selection ratio greater than 20; And
Carry out one the 3rd chemical mechanical milling tech to remove a boundary layer, this boundary layer is formed in this semiconductor technology between this nominal grid and this hard mask, the 3rd chemical mechanical milling tech uses one the 3rd platform and one the 3rd slurry, and the 3rd slurry has the selection ratio greater than 3.
14. method of carrying out multi-platform cmp as claimed in claim 13, wherein this second slurry has the ratio of selection for oxide and nitride.
15. method of carrying out multi-platform cmp as claimed in claim 13, wherein the 3rd slurry has the ratio of selection for polysilicon and oxide.
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|---|---|---|---|
| US9042408P | 2008-08-20 | 2008-08-20 | |
| US61/090,424 | 2008-08-20 | ||
| US12/499,439 US8153526B2 (en) | 2008-08-20 | 2009-07-08 | High planarizing method for use in a gate last process |
| US12/499,439 | 2009-07-08 |
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| CN101659034A CN101659034A (en) | 2010-03-03 |
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| US (1) | US8153526B2 (en) |
| CN (1) | CN101659034B (en) |
| TW (1) | TWI470686B (en) |
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| US20120264302A1 (en) * | 2011-04-13 | 2012-10-18 | Chun-Wei Hsu | Chemical mechanical polishing process |
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| US8647986B2 (en) * | 2011-08-30 | 2014-02-11 | United Microelectronics Corp. | Semiconductor process |
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| US9202699B2 (en) | 2011-09-30 | 2015-12-01 | Intel Corporation | Capping dielectric structure for transistor gates |
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| CN103918083A (en) | 2011-10-01 | 2014-07-09 | 英特尔公司 | Source/drain contacts for non-planar transistors |
| CN103035504B (en) * | 2011-10-09 | 2016-07-06 | 中芯国际集成电路制造(北京)有限公司 | Cmp method and chemical-mechanical polisher |
| US8975179B2 (en) * | 2011-10-18 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Planarization process for semiconductor device fabrication |
| CN103137452B (en) * | 2011-11-25 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Control the method for replacement gate structure height |
| DE112011105925B4 (en) | 2011-12-06 | 2023-02-09 | Tahoe Research, Ltd. | Microelectronic transistor and method of making the same |
| US9589803B2 (en) | 2012-08-10 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate electrode of field effect transistor |
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| US9337103B2 (en) * | 2012-12-07 | 2016-05-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for removing hard mask oxide and making gate structure of semiconductor devices |
| US8853084B2 (en) | 2013-01-31 | 2014-10-07 | International Business Machines Corporation | Self-adjusting gate hard mask |
| US9960050B2 (en) | 2013-08-05 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company Limited | Hard mask removal method |
| CN104701151A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Gate electrode forming method |
| US20150214114A1 (en) * | 2014-01-28 | 2015-07-30 | United Microelectronics Corp. | Manufacturing method of semiconductor structure |
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| US9917017B2 (en) * | 2015-12-29 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Replacement gate process for semiconductor devices |
| KR102434914B1 (en) | 2016-01-15 | 2022-08-23 | 삼성전자주식회사 | Method for forming patterns of semiconductor device and method for fabricating semiconductor device using the same |
| US10062845B1 (en) * | 2016-05-13 | 2018-08-28 | Crossbar, Inc. | Flatness of memory cell surfaces |
| US10522754B2 (en) | 2016-06-15 | 2019-12-31 | Crossbar, Inc. | Liner layer for dielectric block layer |
| US10749110B1 (en) | 2016-07-15 | 2020-08-18 | Crossbar, Inc. | Memory stack liner comprising dielectric block layer material |
| US9923080B1 (en) | 2017-02-02 | 2018-03-20 | International Business Machines Corporation | Gate height control and ILD protection |
| CN108878363B (en) * | 2017-05-12 | 2021-07-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US10964549B2 (en) * | 2018-11-30 | 2021-03-30 | Taiwan Semiconductor Manufacturing Company Limited | Wafer polishing with separated chemical reaction and mechanical polishing |
| CN111816562B (en) * | 2019-04-10 | 2024-05-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110473834A (en) * | 2019-08-29 | 2019-11-19 | 上海华力集成电路制造有限公司 | The manufacturing method of grid |
| CN110690114A (en) * | 2019-10-11 | 2020-01-14 | 武汉新芯集成电路制造有限公司 | CMP polishing method |
| US11984324B2 (en) * | 2020-06-30 | 2024-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
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| US20070215950A1 (en) * | 2006-03-20 | 2007-09-20 | Tomonori Aoyama | Semiconductor device and manufacturing method thereof |
| US20080083948A1 (en) * | 2006-10-05 | 2008-04-10 | Hsien-Hsin Lin | SiGe selective growth without a hard mask |
Also Published As
| Publication number | Publication date |
|---|---|
| US8153526B2 (en) | 2012-04-10 |
| CN101659034A (en) | 2010-03-03 |
| TWI470686B (en) | 2015-01-21 |
| US20100048007A1 (en) | 2010-02-25 |
| TW201009925A (en) | 2010-03-01 |
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