CN101645439A - 发光二极管 - Google Patents

发光二极管 Download PDF

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CN101645439A
CN101645439A CN200810303373A CN200810303373A CN101645439A CN 101645439 A CN101645439 A CN 101645439A CN 200810303373 A CN200810303373 A CN 200810303373A CN 200810303373 A CN200810303373 A CN 200810303373A CN 101645439 A CN101645439 A CN 101645439A
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electrode
light
luminescence chip
emitting diode
packaging body
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朱源发
江文章
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Foxsemicon Integrated Technology Shanghai Inc
Foxsemicon Integrated Technology Inc
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Foxsemicon Integrated Technology Shanghai Inc
Foxsemicon Integrated Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

本发明涉及一种发光二极管，其包括一个第一电极，一个与该第一电极并列设置且极性相反的第二电极，至少一个第一发光芯片，至少一个第二发光芯片以及一个封装体。该至少一个第一发光芯片与该第一电极及该第二电极电性连接以用于射出具有第一波长的第一光束。该至少一个第二发光芯片与该第一电极及该第二电极电性连接以用于射出具有第二波长的第二光束，该第二波长的范围为570～670纳米。该封装体设置在该第一电极及第二电极上且将该至少一个第一发光芯片与该至少一个第二发光芯片包覆在其中。该封装体内掺杂有荧光物质，该荧光物质经由该第一光束激发以产生白光，该第二光束用以调节该白光的色温。

Description

发光二极管
技术领域
本发明涉及一种发光二极管。
背景技术
现如今，发光二极管(Light Emitting Diode，LED)已经被广泛应用到很多领域，如何能得到性能更优越的发光二极管已经变成人们研发的方向，在此，一种新型发光二极管可参见Daniel A.Steigerwald等人在文献IEEE Journal on Selected Topics in QuantumElectronics，Vol.8，No.2，March/April 2002中的Illumination With Solid StateLighting Technology一文。因为发光二极管具有发光效率高、演色性佳等特点，所以其开始被人们运用在路灯上以利于日常生活所需。
然而，现有的发光二极管光源射出的白光的色温值偏高，其通常介于4500~6500K，这样会让人们感觉寒冷且光线刺眼、同时光源的演色性也仅能达到80％，这样的色温值及演色性还不能达到人们的要求。现有的发光二极管通常是通过在发光二极管晶粒中加入荧光物质以发出白光，而荧光物质的比例在发光二极管制造完成后即已固定，因此不能在后续的使用过程中对发光二极管的色温进行调节，从而不利于人们的使用要求。
有鉴于此，提供一种色温可调的发光二极管实为必要。
发明内容
以下将以实施例说明一种色温可调的发光二极管。
一种发光二极管，其包括：一个第一电极，一个与该第一电极并列设置且极性相反的第二电极，至少一个第一发光芯片，至少一个第二发光芯片以及一个封装体。该至少一个第一发光芯片与该第一电极及该第二电极电性连接以用于射出具有第一波长的第一光束。该至少一个第二发光芯片与该第一电极及该第二电极电性连接以用于射出具有第二波长的第二光束，该第二波长的范围为570~670纳米。该封装体设置在该第一电极及第二电极上且将该至少一个第一发光芯片与该至少一个第二发光芯片包覆在其中。该封装体内掺杂有荧光物质，该荧光物质经由该第一光束激发以产生白光，该第二光束用以调节该白光的色温。
相对于现有技术，所述发光二极管可射出白光及波长范围为570~670纳米的光，使所述发光二极管通过调节波长范围为570~670纳米的光的亮度以实现调节所述白光的色温，从而适当的提高人们的舒适度。
附图说明
图1是本发明第一实施例发光二极管的截面示意图。
图2是本发明第二实施例发光二极管的截面示意图。
图3是本发明第三实施例发光二极管的截面示意图。
具体实施方式
下面结合附图对本发明作进一步的详细说明。
请参见图1，本发明第一实施例提供的发光二极管10，其包括：一个第一电极11，一个第二电极12，一个第一发光芯片13，一个第二发光芯片14及一个封装体15。
第一电极11与第二电极12构成一导线架(Lead Frame)，二者并列设置且极性相反。在本实施例中，第一电极11为正极，第二电极12为负极。
第一发光芯片13与第二发光芯片14串联，第一发光芯片13与第二发光芯片14由第一电极11与第二电极12向其提供电能。
第一发光芯片13用于发出具有第一波长的激发光。第一发光芯片13包括位于其同一侧的第一接触电极131及第二接触电极132，第一发光芯片13设置在第一电极11上且其接触电极131、132相对远离第一电极11。第一发光芯片13的第一接触电极131与第一电极11打线连接。
第二发光芯片14用于射出具有第二波长的第二光束，第二波长的范围为570~670纳米。第二发光芯片14包括第一接触电极141及第二接触电极142，二者相对设置。第二发光芯片14的第一接触电极141与第一发光芯片13的第一接触电极131极性相同。第二发光芯片14设置在第二电极12上，第二发光芯片14的第一接触电极141与第一发光芯片13的第二接触电极132打线连接，第二发光芯片14的第二接触电极142直接与第二电极12电性连接。
第一发光芯片13所用材料为III-V族化合物，例如：氮化铝镓铟(AlInGaN)等，第二发光芯片14所用材料为III-V族化合物，例如：磷化铝镓铟(AlInGaP)。
可以理解的是，发光二极管10所包括的第一发光芯片13及第二发光芯片14的数量不限于一个，其也可为多个。
封装体15包括内封装体151及包覆内封装体151的外封装体152。内封装体151设置在第一电极11上以密封第一发光芯片13，而外封装体152设置在第一电极11与第二电极12的上方以密封第二发光芯片14及内封装体151。内封装体151内掺杂有荧光物质，第一发光芯片13发出的激发光可激发荧光物质产生白光，产生的白光可经由外封装体152出射至封装体15的外部。荧光物质可为钇铝石榴石(YAG)荧光粉，铽铝石榴石(TAG)荧光粉，硅酸盐荧光粉，或氮化物荧光粉等。
当第一电极11与第二电极12连接至一驱动控制单元(图未示)时，第一发光芯片13与第二发光芯片14串接在一电气回路中，驱动控制单元可控制流过第一发光芯片13与第二发光芯片14的电流以调节第一发光芯片13与第二发光芯片14所发出光的亮度。第一发光芯片13所发出的激发光可激发荧光物质产生白光，第二光束直接经由外封装体152出射至封装体15的外部。在此，驱动控制单元可通过控制流过上述电气回路的电流来调节第二光束的亮度，从而可以对发光二极管10所发出的白光的色温进行调节。
请参见图2，本发明第二实施例提供的发光二极管20，其与上述第一实施例提供的发光二极管10基本相同，不同之处在于：发光二极管20还包括一个二极管芯片27，二极管芯片27与第一发光芯片13及第二发光芯片14反向并联，即当第一电极11为正极而第二电极12为负极时，二极管芯片27的负极271与第一电极11电性连接，二极管芯片27的正极272与第二电极12电性连接，二极管芯片27可有效的防止反向电压过大而损坏第一发光芯片13。在此，当第一电极11与第二电极12连接至一驱动控制单元(图未示)时，第一发光芯片13与第二发光芯片14串联在一电气回路中，驱动控制单元可通过控制流过上述电气回路的电流来调节具有第二波长的第二光束的亮度，从而可以对发光二极管20所发出的白光的色温进行调节。
请参见图3，本发明第三实施例提供的发光二极管30，其包括：一个第一电极31，一个第二电极32，一个第一发光芯片33，一个第二发光芯片34，及一个封装体15。
第二电极32包括一个第一部分321及一个第二部分322，二者电性相同并分别设置在第一电极31的两侧。在本实施例中，第一电极31为负极，第二电极32的第一部分321及第二部分322均为正极。
第一发光芯片33由第一电极31和第二电极32的第一部分321向其提供电能，以使第一发光芯片33发出具有第一波长的激发光。第一发光芯片33包括位于其同一侧的第一接触电极331及第二接触电极332，第一发光芯片33设置在第一电极31上且其接触电极331、332相对远离第一电极31。第一发光芯片33的第一接触电极331与第一电极31打线连接，第一发光芯片33的第二接触电极332与第二电极32的第一部分321打线连接。
第二发光芯片34由第一电极31及第二电极32的第二部分322向其提供电能，以使第二发光芯片34发出具有第二波长的第二光束，第二波长的范围为570~670纳米。第二发光芯片34设置在第一电极31上且与第一发光芯片33相邻。第二发光芯片34包括第一接触电极341及第二接触电极342，二者相对设置。第二发光芯片34的第一接触电极341与第一发光芯片33的第二接触电极332极性相同。第二发光芯片34的第一接触电极341与第二电极32的第二部分322打线连接，第二发光芯片34的第二接触电极342直接与第一电极31电性连接。
第一发光芯片33发出的激发光可激发封装体15的内封装体151内掺杂的荧光物质产生白光，产生的白光可经由外封装体152出射至封装体15的外部。在此，第二发光芯片34由封装体15的外封装体152覆盖，所以第二发光芯片14射出的第二光束可直接经外封装体152出射至封装体15的外部。
当第一电极31与第二电极32的第一部分321连接至一第一驱动控制单元(图未示)，且第一电极31与第二电极32的第二部分322连接至一第二驱动控制单元(图未示)时，第一发光芯片33处在由第一驱动控制单元来控制的第一电气回路中，第二发光芯片34处在由第二驱动控制单元来控制的第二电气回路中，第一驱动控制单元与第二驱动控制单元可分别控制流过第一发光芯片33与第二发光芯片34的电流以分别调节第一发光芯片33与第二发光芯片34所发出光的亮度。第一发光芯片33所发出的激发光可激发荧光物质产生白光，第二发光芯片34所发出的第二光束直接经由外封装体152出射至封装体15的外部。在此，第二驱动控制单元可通过控制流过上述第二电气回路的电流来调节第二光束的亮度，从而可以对发光二极管30所发出的白光的色温进行调节。
另外，本领域技术人员还可于本发明精神内做其它变化，只要其不偏离本发明的技术效果，这些依据本发明精神所做的变化，都应包含在本发明所要求保护的范围之内。

Claims (7)

1.一种发光二极管，其包括一个第一电极及一个与该第一电极并列设置且极性相反的第二电极，其特征在于：
该发光二极管还包括至少一个第一发光芯片，至少一个第二发光芯片以及一个封装体，该至少一个第一发光芯片与该第一电极及该第二电极电性连接以用于射出具有第一波长的第一光束，该至少一个第二发光芯片与该第一电极及该第二电极电性连接以用于射出具有第二波长的第二光束，该第二波长的范围为570~670纳米，该封装体设置在该第一电极及第二电极上且将该至少一个第一发光芯片与该至少一个第二发光芯片包覆在其中，该封装体内掺杂有荧光物质，该荧光物质经由该第一光束激发以产生白光，该第二光束用以调节该白光的色温。
2.如权利要求1所述的发光二极管，其特征在于，该至少一第一发光芯片与该至少一第二发光芯片串联。
3.如权利要求1所述的发光二极管，其特征在于，该发光二极管还包括一个二极管芯片，该二极管芯片与该至少一第一发光芯片反向并联。
4.如权利要求1所述的发光二极管，其特征在于，该至少一第一发光芯片与该至少一第二发光芯片设置在该第一电极上且相邻设置，该第二电极包括一个第一部分与一个第二部分，该至少一第一发光芯片与该第一部分及该第一电极电性连接，该至少一第二发光芯片与该第二部分及第一电极电性连接。
5.如权利要求1所述的发光二极管，其特征在于，该至少一第一发光芯片所用材料为氮化铝镓铟，该至少一第二发光芯片所用材料为磷化铝镓铟。
6.如权利要求1所述的发光二极管，其特征在于，该封装体包括一个内封装体及一个包覆该内封装体的外封装体，该内封装体用于密封该至少一个第一发光芯片，该外封装体用于密封该至少一个第二发光芯片及该内封装体，该内封装体内掺杂有该荧光物质。
7.如权利要求1所述的发光二极管，其特征在于，该荧光物质为钇铝石榴石荧光粉，铽铝石榴石荧光粉，硅酸盐荧光粉或氮化物荧光粉。
CN200810303373A 2008-08-04 2008-08-04 发光二极管 Pending CN101645439A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107768359A (zh) * 2016-08-16 2018-03-06 亿光电子工业股份有限公司 发光装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107768359A (zh) * 2016-08-16 2018-03-06 亿光电子工业股份有限公司 发光装置

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