CN101641680A - 存储器系统 - Google Patents

存储器系统 Download PDF

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Publication number
CN101641680A
CN101641680A CN200880006501A CN200880006501A CN101641680A CN 101641680 A CN101641680 A CN 101641680A CN 200880006501 A CN200880006501 A CN 200880006501A CN 200880006501 A CN200880006501 A CN 200880006501A CN 101641680 A CN101641680 A CN 101641680A
Authority
CN
China
Prior art keywords
data
block
memory block
memory
input buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN200880006501A
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English (en)
Chinese (zh)
Inventor
矢野纯二
松崎秀则
初田幸辅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN101641680A publication Critical patent/CN101641680A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
CN200880006501A 2008-03-01 2008-09-22 存储器系统 Pending CN101641680A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008051477A JP4745356B2 (ja) 2008-03-01 2008-03-01 メモリシステム
JP051477/2008 2008-03-01

Publications (1)

Publication Number Publication Date
CN101641680A true CN101641680A (zh) 2010-02-03

Family

ID=41055698

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200880006501A Pending CN101641680A (zh) 2008-03-01 2008-09-22 存储器系统

Country Status (7)

Country Link
US (1) US20100281204A1 (enExample)
EP (1) EP2250566A4 (enExample)
JP (1) JP4745356B2 (enExample)
KR (1) KR101101655B1 (enExample)
CN (1) CN101641680A (enExample)
TW (1) TW200941218A (enExample)
WO (1) WO2009110125A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103902483A (zh) * 2012-12-26 2014-07-02 擎泰科技股份有限公司 非易失性存储器的数据安排方法及存储器控制系统
CN107301133A (zh) * 2017-07-20 2017-10-27 郑州云海信息技术有限公司 一种构建丢失的FTL table的方法及装置

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* Cited by examiner, † Cited by third party
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KR101077339B1 (ko) * 2007-12-28 2011-10-26 가부시끼가이샤 도시바 반도체 기억 장치
JP4461170B2 (ja) 2007-12-28 2010-05-12 株式会社東芝 メモリシステム
JP4691122B2 (ja) * 2008-03-01 2011-06-01 株式会社東芝 メモリシステム
JP4439569B2 (ja) * 2008-04-24 2010-03-24 株式会社東芝 メモリシステム
TWI370273B (en) 2008-10-17 2012-08-11 Coretronic Corp Light guide plate
JP5221332B2 (ja) * 2008-12-27 2013-06-26 株式会社東芝 メモリシステム
JP5317690B2 (ja) * 2008-12-27 2013-10-16 株式会社東芝 メモリシステム
WO2010093056A1 (en) 2009-02-12 2010-08-19 Kabushiki Kaisha Toshiba Memory system and method of controlling memory system
US8374480B2 (en) * 2009-11-24 2013-02-12 Aten International Co., Ltd. Method and apparatus for video image data recording and playback
JP5060574B2 (ja) * 2010-03-16 2012-10-31 株式会社東芝 メモリシステム
JP5221593B2 (ja) * 2010-04-27 2013-06-26 株式会社東芝 メモリシステム
JP2012008651A (ja) 2010-06-22 2012-01-12 Toshiba Corp 半導体記憶装置、その制御方法および情報処理装置
TWI480731B (zh) * 2010-06-30 2015-04-11 Insyde Software Corp 轉接裝置及經由該轉接裝置之除錯方法
JP2012128644A (ja) 2010-12-15 2012-07-05 Toshiba Corp メモリシステム
JP2012141946A (ja) * 2010-12-16 2012-07-26 Toshiba Corp 半導体記憶装置
JP5535128B2 (ja) 2010-12-16 2014-07-02 株式会社東芝 メモリシステム
TWI479315B (zh) * 2012-07-03 2015-04-01 Phison Electronics Corp 記憶體儲存裝置、其記憶體控制器與資料寫入方法
US20140032820A1 (en) * 2012-07-25 2014-01-30 Akinori Harasawa Data storage apparatus, memory control method and electronic device with data storage apparatus
CN105103234A (zh) * 2012-11-20 2015-11-25 查尔斯·I·派德尔 固态驱动器体系结构
TWI537734B (zh) * 2013-06-18 2016-06-11 群聯電子股份有限公司 資料保護方法、記憶體控制器與記憶體儲存裝置
US9880778B2 (en) * 2015-11-09 2018-01-30 Google Inc. Memory devices and methods
JP2018041204A (ja) * 2016-09-06 2018-03-15 東芝メモリ株式会社 メモリ装置及び情報処理システム
FR3074317B1 (fr) * 2017-11-27 2019-11-22 Idemia Identity & Security France Procede d'acces a une zone memoire non volatile de type flash d'un element securise, tel qu'une carte a puce
US10970216B2 (en) 2017-12-27 2021-04-06 Intel Corporation Adaptive granularity write tracking
US10949346B2 (en) * 2018-11-08 2021-03-16 International Business Machines Corporation Data flush of a persistent memory cache or buffer
TWI742961B (zh) * 2020-12-10 2021-10-11 旺宏電子股份有限公司 快閃記憶體系統及其快閃記憶體裝置
JP7516300B2 (ja) * 2021-03-17 2024-07-16 キオクシア株式会社 メモリシステム
US20240134801A1 (en) * 2022-10-19 2024-04-25 Samsung Electronics Co., Ltd. Methods and system for efficient access to solid state drive

Family Cites Families (15)

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Publication number Priority date Publication date Assignee Title
JP3688835B2 (ja) * 1996-12-26 2005-08-31 株式会社東芝 データ記憶システム及び同システムに適用するデータ転送方法
US6000006A (en) * 1997-08-25 1999-12-07 Bit Microsystems, Inc. Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage
KR100389867B1 (ko) * 2001-06-04 2003-07-04 삼성전자주식회사 플래시 메모리 관리방법
US7173863B2 (en) * 2004-03-08 2007-02-06 Sandisk Corporation Flash controller cache architecture
US20050144379A1 (en) * 2003-12-31 2005-06-30 Eschmann Michael K. Ordering disk cache requests
KR100526190B1 (ko) * 2004-02-06 2005-11-03 삼성전자주식회사 플래시 메모리의 재사상 방법
JP4768237B2 (ja) * 2004-06-25 2011-09-07 株式会社東芝 携帯可能電子装置及び携帯可能電子装置の制御方法
US20070094445A1 (en) * 2005-10-20 2007-04-26 Trika Sanjeev N Method to enable fast disk caching and efficient operations on solid state disks
JP2008033788A (ja) * 2006-07-31 2008-02-14 Matsushita Electric Ind Co Ltd 不揮発性記憶装置、データ記憶システム、およびデータ記憶方法
US7814276B2 (en) * 2007-11-20 2010-10-12 Solid State System Co., Ltd. Data cache architecture and cache algorithm used therein
KR101077339B1 (ko) * 2007-12-28 2011-10-26 가부시끼가이샤 도시바 반도체 기억 장치
JP4653817B2 (ja) * 2008-03-01 2011-03-16 株式会社東芝 メモリシステム
JP4498426B2 (ja) * 2008-03-01 2010-07-07 株式会社東芝 メモリシステム
JP4592774B2 (ja) * 2008-03-01 2010-12-08 株式会社東芝 メモリシステム
JP4643667B2 (ja) * 2008-03-01 2011-03-02 株式会社東芝 メモリシステム

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103902483A (zh) * 2012-12-26 2014-07-02 擎泰科技股份有限公司 非易失性存储器的数据安排方法及存储器控制系统
CN107301133A (zh) * 2017-07-20 2017-10-27 郑州云海信息技术有限公司 一种构建丢失的FTL table的方法及装置
CN107301133B (zh) * 2017-07-20 2021-01-12 苏州浪潮智能科技有限公司 一种构建丢失的FTL table的方法及装置

Also Published As

Publication number Publication date
EP2250566A4 (en) 2011-09-28
TW200941218A (en) 2009-10-01
JP4745356B2 (ja) 2011-08-10
WO2009110125A1 (en) 2009-09-11
KR20090117930A (ko) 2009-11-16
JP2009211231A (ja) 2009-09-17
EP2250566A1 (en) 2010-11-17
KR101101655B1 (ko) 2011-12-30
US20100281204A1 (en) 2010-11-04

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