CN101640197A - Semiconductor structure and method for manufacturing same - Google Patents
Semiconductor structure and method for manufacturing same Download PDFInfo
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- CN101640197A CN101640197A CN200810129973A CN200810129973A CN101640197A CN 101640197 A CN101640197 A CN 101640197A CN 200810129973 A CN200810129973 A CN 200810129973A CN 200810129973 A CN200810129973 A CN 200810129973A CN 101640197 A CN101640197 A CN 101640197A
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Abstract
The invention relates to a semiconductor structure and a method for manufacturing the same. The method for manufacturing a semiconductor forms an oxide layer, and at the same time, partial oxide layerareas separate space or provide height difference so as to enable a conduction bus (Bus) to be formed on the partial oxide layer areas. Therefore, the conduction bus can be defined without needing additional photomasks and can form conduction materials on the oxide layer areas in the subsequent process of manufacturing. Therefore, the manufacturing of the semiconductor can reduce the number of required photomasks so as to reduce cost.
Description
Technical field
The invention relates to a kind of semiconductor structure and method thereof, the defence ring is particularly arranged about a kind of double diffusion MOS power transistors (DMOS) structure and method thereof.
Background technology
Integrated circuit is when function from strength to strength now, and its structure also becomes increasingly complex, and causes photomask (photomask is a light shield, and this paper all the is called photomask) number of integrated circuit also to increase thereupon, and cost also constantly rises.
See also Figure 1A to Fig. 1 I at this, illustrate for example with the manufacturing (processing procedure is a manufacture process, and this paper all is called manufacturing) of N type double diffusion MOS power transistors.With reference to Figure 1A, on silicon substrate 5, grow up in regular turn N-epitaxial layer 10 and field oxide 12, and utilize first photomask to form first photoresist layer 14, to define the zone of defence ring (Guard Ring).Next, see also Figure 1B, after the field oxide 12 that etching is not covered by first photoresist layer 14, eccysis first photoresist layer 14.The field oxide 12 of defence ring also defines the active region (ActiveRegion) of MOS power transistors simultaneously.Next, in order more to clearly demonstrate the manufacturing of each transistor unit in the N type double diffusion MOS power transistors, so Fig. 1 C to Fig. 1 H only shows the defence ring of a side.See also Fig. 1 C, (grid is a gate to form grid on active region in regular turn, this paper all is called grid) oxide layer 20, gate electrode 22, and utilize second photomask to define gate regions forming second photoresist layer 24, remove not the zone that covered by second photoresist layer 24 to expose the N-epitaxial layer 10 of part with after etching.Inject the part that the P-semiconductor substance exposes in N-epitaxial layer 10 with ion implantation, and elevated temperature heat drives in (Drive-in) and forms P wellblock 26.Then, see also Fig. 1 D, eccysis second photoresist layer 24 uses the 3rd photomask to form the 3rd photoresist layer 32, defining source electrode, and injects N+ semiconductor substance and elevated temperature heat with ion implantation and drives in and form N+ source area 30.See also Fig. 1 E, remove the 3rd photoresist layer 32 after, form the 4th photoresist layer 42 to use the 4th photomask, fasten plug (P-Plug) injection region 40 and inject the P+ semiconductor substance with ion implantation and fasten plug injection region 40 to define P in P.
Then, please refer to F figure, form silicon dioxide layer 50 and boron-phosphorosilicate glass layer (BPSG) 52 in regular turn, and form the 5th photoresist layer 54 to define the contact hole district with the 5th photomask, and etching removes the silicon dioxide layer 50 in contact hole district and boron-phosphorosilicate glass floor 52 is fastened plug injection region 40 to expose P, makes boro-phosphorus glass backfill (BPSG Reflow) with high temperature then.Please refer to Fig. 1 C, the metal level 60 of growing up subsequently, and form the 6th photoresist layer 62 to define gate metal layer and source metal with the 6th photomask.Come again, please refer to Fig. 1 H and Fig. 1 I, form a protective layer 70, and define gate pad district 72 and source pad district 74 for routing with the 7th photomask with protection N type double diffusion MOS power transistors 80.
N type double diffusion MOS power transistors as above-mentioned need seven road photomasks altogether, so its photomask cost is quite high.Therefore, how some structures are finished in photomask to reduce the cost that the photomask number reduces integrated circuit, be the target that this field dealer is pursued always.
This shows that above-mentioned conventional semiconductor structure and manufacture method thereof obviously still have inconvenience and defective, and demand urgently further being improved in product structure, manufacture method and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new semiconductor structure and manufacture method thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned conventional semiconductor structure and manufacture method thereof exist, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of new semiconductor structure and manufacture method thereof, can improve general conventional semiconductor structure and manufacture method thereof, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcome the defective that conventional semiconductor structure and manufacture method thereof exist, and provide a kind of semiconductor structure and manufacture method thereof of new structure, technical problem to be solved is that it is utilized when forming oxide skin(coating), the partial oxide layer separates between clearancen or difference in height is provided, and is formed on the circuit (Bus) that is provided as conduction usefulness.So, transmission line is light requirement mask and forming in the mill not, therefore can reduce the cost of photomask.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of semiconductor structure that the present invention proposes, it comprises: an operating space, a plurality of operating units are arranged in this operating space, and those operating units receive a control signal, and according to this control signal operation; And a conducting region, be electrically connected to those operating units, so that this control signal is reached those operating units; Wherein, this conducting region has an assisted parts, a conducting part and a contact site, this assisted parts is made of non-conductive material, and separate out a plurality of spaces, this conducting part is made of conductor material, be formed on those spaces and electrically connect those operating units, this conducting region is removed the part conducting region to form at least one contact hole and to expose this assisted parts of part, and this contact site is formed on this at least one contact hole to receive this control signal and to electrically connect with this conducting part.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor structure, wherein said at least one contact hole is to form in the dry ecthing mode.
Aforesaid semiconductor structure, wherein said conducting part is made of polysilicon.
Aforesaid semiconductor structure, wherein said assisted parts forms when forming the field oxide of a defence ring simultaneously.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of double diffusion MOS power transistors that the present invention proposes, it comprises: a conducting region, in order to receive a grid control signal; And a transistor area, a plurality of double diffusion MOS power transistors are arranged in this transistor area, each double diffusion MOS power transistors has a grid and is electrically connected to this conducting region, with according to this grid control signal running; Wherein, this conducting region has an assisted parts, a conducting part and a contact site, this assisted parts is made of non-conductive material, and separate out a plurality of spaces, this conducting part is made of conductor material, be formed on those spaces and electrically connect those operating units, this conducting region is removed the part conducting region to form at least one contact hole and to expose this assisted parts of part, and this contact site is formed on this at least one contact hole to receive this grid control signal and to electrically connect with this conducting part.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid double diffusion MOS power transistors, it also comprises the periphery of at least one defence ring position in this conducting region and this transistor area, and wherein this assisted parts forms when forming the field oxide of this at least one defence ring simultaneously.
Aforesaid double diffusion MOS power transistors, wherein said conducting part is made of polysilicon.
Aforesaid double diffusion MOS power transistors, wherein said at least one contact hole is to form in the dry ecthing mode.
Aforesaid double diffusion MOS power transistors, it also comprises a dielectric layer and is formed on this conducting region, and this dielectric layer of part that is positioned on this contact hole is removed when dry ecthing.
Aforesaid double diffusion MOS power transistors, wherein said dielectric layer comprises a silicon nitride layer.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.According to a kind of MOS power transistors manufacture method that the present invention proposes, it may further comprise the steps:
A. form a field oxide layer on the semiconductor substrate, this field oxide layer comprises a defence portion and an assisted parts;
B. form a grid oxic horizon, a gate electrode and a dielectric layer in regular turn on this semiconductor-based end, to define the grid of a plurality of MOS power transistors, wherein this grid oxic horizon, this gate electrode and this dielectric layer are formed on this assisted parts, and this grid oxic horizon, this gate electrode and this dielectric layer of this assisted parts top are that part is removed, and expose this gate electrode of part to form at least one grid contact hole;
C. form a plurality of wellblocks and multiple source/drain region within this semiconductor-based end; And
D. form a metal level on those source/drain regions and this at least one grid contact hole, and remove this metal level of part to define one a source/drain region pad and a gate pad.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid MOS power transistors manufacture method, wherein said b step comprises:
B1. form a grid oxic horizon, a gate electrode and a dielectric layer in regular turn on this semiconductor-based end; And
B2. remove this grid oxic horizon, this gate electrode and this dielectric layer on this defence portion, this wellblock, and this grid oxic horizon of the part on this assisted parts, this gate electrode and this dielectric layer.
Aforesaid MOS power transistors manufacture method, wherein said b2 step are to remove this grid oxic horizon, this gate electrode and this dielectric layer with dry ecthing.
Aforesaid MOS power transistors manufacture method, wherein said dielectric layer are silicon nitride.
Aforesaid MOS power transistors manufacture method, wherein said c step comprises:
C1. inject first kind of alloy within this semiconductor-based end to form these a plurality of wellblocks;
C2. inject first kind of alloy within these a plurality of wellblocks to form this multiple source/drain region;
C3. form the monoxide layer;
C4. remove this oxide skin(coating) in the dry ecthing mode and at the side residual fraction oxide of this at least one grid contact hole and this gate electrode; And
C5. remove the zone of this exposed multiple source/drain region, to expose the subregion of these a plurality of wellblocks.
The object of the invention to solve the technical problems realizes in addition more by the following technical solutions.According to a kind of semiconductor structure that the present invention proposes, it comprises: an operating space, a plurality of operating units are arranged in this operating space, and those operating units receive a control signal, and according to this control signal operation; And a conducting region, be electrically connected to those operating units, so that this control signal is reached those operating units; Wherein, this conducting region has an assisted parts, a conducting part and a contact site, this assisted parts is made of non-conductive material, this conducting part is made of conductor material, be formed on this assisted parts and electrically connect those operating units, this conducting region is with the exposed at least one contact hole of cmp mode, and this contact site is formed on this at least one contact hole to receive this control signal and to electrically connect with this conducting part.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor structure, wherein said conducting part is made of polysilicon.
Aforesaid semiconductor structure, wherein said assisted parts forms when forming the field oxide of a defence ring simultaneously.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.According to a kind of double diffusion MOS power transistors that the present invention proposes, it comprises: a conducting region, in order to receive a grid control signal; And a transistor area, a plurality of double diffusion MOS power transistors are arranged in this transistor area, each double diffusion MOS power transistors has a grid and is electrically connected to this conducting region, with according to this grid control signal running; Wherein, this conducting region has an assisted parts, a conducting part and a contact site, this assisted parts is made of non-conductive material, this conducting part is made of conductor material, be formed on this assisted parts and electrically connect those operating units, this conducting region is with the exposed at least one contact hole of cmp mode, and this contact site is formed on this at least one contact hole to receive this grid control signal and to electrically connect with this conducting part.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid double diffusion MOS power transistors, it also comprises the periphery that at least one defence ring is positioned at this conducting region and this transistor area, and wherein this assisted parts forms when forming the field oxide of this at least one defence ring simultaneously.
Aforesaid double diffusion MOS power transistors, wherein said conducting part is made of polysilicon.
The object of the invention to solve the technical problems also realizes again in addition by the following technical solutions.According to a kind of MOS power transistors manufacture method that the present invention proposes, it may further comprise the steps:
A. form a field oxide layer on the semiconductor substrate, this field oxide comprises a defence portion and an assisted parts;
B. form a grid oxic horizon, a gate electrode and an insulating barrier in regular turn on this semiconductor-based end, to define the grid of a plurality of MOS power transistors, wherein this grid oxic horizon, this gate electrode and this dielectric layer are formed on this assisted parts;
C. form a plurality of wellblocks and multiple source/drain region within this semiconductor-based end;
D. remove this dielectric layer of this assisted parts top in the cmp mode, expose this gate electrode of part to form at least one grid contact hole; And
E. form a metal level on those source/drain regions and this at least one grid contact hole, and remove the part metals layer to define one a source/drain region pad and a gate pad.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid MOS power transistors manufacture method, wherein said b step comprises:
B1. form a grid oxic horizon, a gate electrode and an insulating barrier in regular turn on this semiconductor-based end; And
B2. remove this grid oxic horizon, this gate electrode and this dielectric layer that reach top between this defence portion and this assisted parts between this defence portion, this defence portion.
Aforesaid MOS power transistors manufacture method, wherein said dielectric layer are silicon nitride.
Aforesaid MOS power transistors manufacture method, wherein said c step comprises:
C1. inject first kind of alloy within this semiconductor-based end to form these a plurality of wellblocks;
C2. inject first kind of alloy within these a plurality of wellblocks to form this multiple source/drain region;
C3. form the monoxide layer;
C4. remove this oxide skin(coating) in the dry ecthing mode and at the side residual fraction oxide of this at least one grid contact hole and this gate electrode; And
C5. remove the zone of this exposed multiple source/drain region, to expose the subregion of these a plurality of wellblocks.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, semiconductor structure of the present invention and manufacture method thereof have following advantage and beneficial effect at least: transmission line of the present invention can not need extra photomask to define, and can in manufacturing subsequently, form conductor material on this oxide layer areas, therefore, semi-conductive manufacturing of the present invention can reduce required photomask number to reduce cost.
In sum, the present invention is relevant a kind of semiconductor structure and manufacture method thereof, when semiconductor manufacturing utilization of the present invention formed oxide skin(coating), the partial oxide layer separated between clearancen or difference in height is provided, and formed thereon with the circuit (Bus) that is provided as conduction usefulness.So, transmission line can not need extra photomask to define, and can form conductor material in manufacturing subsequently on this oxide layer areas.Therefore, semi-conductive manufacturing of the present invention can reduce required photomask number to reduce cost.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure, manufacture method or function, obvious improvement is arranged technically, and produced handy and practical effect, and has the outstanding effect of enhancement than conventional semiconductor structure and manufacture method thereof, thereby being suitable for practicality more, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Figure 1A is the manufacturing step of known N type double diffusion MOS power transistors to Fig. 1 I.
Fig. 2 A is a manufacturing step according to the N type double diffusion MOS power transistors of one first preferred embodiment of the present invention to Fig. 2 H.
Fig. 3 A is a manufacturing step according to the N type double diffusion MOS power transistors of one second preferred embodiment of the present invention to Fig. 3 G.
5: silicon substrate 10:N-epitaxial layer
12: 14: the first photoresist layers of field oxide
20: grid oxic horizon 22: gate electrode
24: the second photoresist layer 30:N+ source areas
32: the three photoresist layers in 26:P wellblock
40:P fastens 42: the four photoresist layers in plug injection region
50: silicon dioxide layer 52: the boron-phosphorosilicate glass layer
72: gate pad district 74: the source pad district
105,205: silicon substrate 110,210:N-epitaxial layer
112,212: field oxide 112a, 212a: defence portion
112b, 212b: assisted parts 114,214: the first photoresist layers
114a, 214a: defence ring 114b, 214b: conducting region
120,220: grid oxic horizon 121,221: gate electrode
221a: conducting part 122,222: dielectric layer
123,223: the second photoresist layers 124,224:P wellblock
125, the 225:N+ source/drain region 126,226: silicon dioxide layer
127,227:P fastens plug 128,228: the contact hole district
129,229: gate regions 2C-2C: hatching
130,230: metal level 130a, 230a: defence ring metal
130b, 230b: source/ drain region pad 130c, 230c: gate pad
132,232: the three photoresist layers
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to semiconductor structure and its embodiment of manufacture method, structure, step, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Spirit of the present invention is to be to utilize to form non-conductive material () process for example: field oxide or silicon dioxide etc. in the semiconductor manufacturing, also simultaneously form this non-conductive material with as assisted parts at conducting region, this conducting region wherein, for example: lock channel lines (Gate Bus Line), data wire (DataLine) etc., it is transmission as control signal, electrically connect each operating unit in the operating space in the integrated circuit, control signal is passed to those operating units makes it according to this control signal operation.Non-conductive material as assisted parts can separate out a plurality of spaces, makes the conductor material that is formed on can insert those spaces.So, etching removes the part conducting region forming at least one contact hole and to expose part during this assisted parts, can residual conductor material in those spaces.At last, deposit as the conductor of contact site when those contact holes, contact site can electrically connect with conducting part again, and this that is received with conduction controls signal to each operating unit.Therefore, do not need extra photomask to define in order to the circuit that transmits this control signal.
Next we are that example illustrates with N type double diffusion MOS power transistors.
See also and read shown in the 2A, N-epitaxial layer 110 and the field oxide 112 of on silicon substrate 105, growing up in regular turn (silicon substrate 105 and N-epitaxial layer 110 are referred to as the semiconductor-based end), and utilize first photomask to form first photoresist layer 114, to define the zone of defence ring (Guard Ring) 114a and conducting region 114b.Next, etching is not by defence portion 112a and the assisted parts 112b of conducting region 114b, then eccysis first photoresist layer 114 of the field oxide 112 of first photoresist layer, 114 coverings with the ring of formation defence simultaneously 114a.Then, see also and examine shown in Fig. 2 B, the dielectric layer 122 that forms grid oxic horizon 120, gate electrode 121 in regular turn and be electrically insulated, and utilize second photomask to form a plurality of transistorized gate regions 129 (seeing Fig. 2 C) that second photoresist layer 123 defines contact hole district 128 and is positioned at transistor area.Wherein, the material of gate electrode 121 can be polysilicon, and dielectric layer 122 can be silicon nitride (Si3N4).
See also shown in Fig. 2 C, remove not the zone that covered by second photoresist layer 123 with dry ecthing (Dry-Etching) to expose N-epitaxial layer 110 to form contact hole 128 and gate pole district 129, owing to can form some spaces between the assisted parts 112b, the polysilicon deposition that makes gate electrode 121 is on assisted parts 112b the time, and the thickness of the space segment that is surrounded at assisted parts 112b is thicker.Remove when exposing N-epitaxial layer 110 in dry ecthing, the space segment that is surrounded at assisted parts 112b still has remaining polysilicon.Then, inject the part that first alloy (is the P-semiconductor substance at this) exposes at N-epitaxial layer 110, and elevated temperature heat drives in (Drive-in) and forms P wellblock 124 with ion implantation.Then, injecting second alloy (is the N+ semiconductor substance at this) of high concentration and elevated temperature heat with ion implantation again drives in and forms N+ source/drain region 125.Be noted that contact hole 128 only forms on the subregion of conducting region, in fact the quantity of contact hole 128 then look the required conduction current of circuit or other consideration decides, and is generally most.Seeing also shown in Fig. 2 D, is the vertical view of Fig. 2 C, and Fig. 2 C be among Fig. 2 D along the profile of 2C-2C hatching.
Then, consult shown in Fig. 2 E, form a silicon dioxide layer 126 and be covered on all structures, see also Fig. 2 F then, remove the N+ source/drain region 125 of silicon dioxide layer and part to exposing P wellblock 124 in the dry ecthing mode.Because dry ecthing is to the etching speed difference of different directions, therefore will be at the side residual fraction silicon dioxide of dielectric layer 122, and the edge slyness of this residual silicon dioxide.Come in exposed P wellblock 124, to inject first alloy (is the P+ semiconductor substance at this) of high concentration again, fasten plug 127 to form P with the ion injection mode.The thickness that remains in the silicon dioxide of dielectric layer 122 sides can influence passage (Channel) length of N type double diffusion MOS power transistors, and the thickness of residual silicon dioxide depends on the deposit thickness of silicon dioxide layer 126.Therefore, the present invention can by control silicon dioxide layer 126 thickness control the passage length of N type double diffusion MOS power transistors.
See also shown in Fig. 2 G and Fig. 2 H, form a metal level 130, and form the 3rd photoresist layer 132 with the source of defining/drain region pad 130b, gate pad 130c and defence ring metal 130a with the 3rd photomask.
Next, seeing also Fig. 3 A to shown in Fig. 3 G, is the manufacturing step according to the N type double diffusion MOS power transistors of one second preferred embodiment of the present invention.To first preferred embodiment shown in Fig. 2 H, utilize cmp mode (CMP) to form contact hole on the conducting region compared to Fig. 2 A at present embodiment.
See also shown in Fig. 3 A, N-epitaxial layer 210 and the field oxide 212 of on silicon substrate 205, growing up in regular turn (silicon substrate 205 and N-epitaxial layer 210 are referred to as the semiconductor-based end), and utilize first photomask to form first photoresist layer 214, to define the zone of defence ring (Guard Ring) 214a and conducting region 214b.Next, etching is not by defence portion 212a and the assisted parts 212b of conducting region 214b, then eccysis first photoresist layer 214 of the field oxide of first photoresist layer, 214 coverings with the ring of formation defence simultaneously 214a.Then, see also shown in Fig. 3 B, the dielectric layer 222 that forms grid oxic horizon 220, gate electrode 221 in regular turn and be electrically insulated, and utilize second photomask to form second photoresist layer 223 to define a plurality of transistorized gate regions 229 that is positioned at transistor area and to form conducting region 214b (referring to Fig. 3 D).Wherein, the material of gate electrode 221 can be polysilicon, and dielectric layer 222 can be silicon nitride (Si3N4).
See also shown in Fig. 3 C, remove not with dry ecthing (Dry-Etching) zone that covered by second photoresist layer 223 with expose N-epitaxial layer 210 with the connection line that forms conducting region 214b, gate regions 229 and conducting region 214b and gate regions 229 (not shown in the figures, its in order to transmit control N type double diffusion MOS power transistors control signal to gate regions 229).Because the assisted parts 212b of conducting region 214b, the conducting part 221a of conducting region 214b (forms simultaneously with gate electrode 221, for distinguishing conveniently, partly be called conducting part 221a at conducting region 214b) than gate electrode 221 for high, in order to the carrying out of subsequent chemistry mechanical lapping.Then, inject the part that first alloy (is the P-semiconductor substance at this) exposes in N-epitaxial layer 210, and elevated temperature heat drives in (Drive-in) and forms P wellblock 224 with ion implantation.Then, injecting second alloy (is the N+ semiconductor substance at this) of high concentration and elevated temperature heat with ion implantation again drives in and forms N+ source/drain region 225.Then, forming a silicon dioxide layer 226 is covered on all structures.
See also shown in Fig. 3 D, remove the N+ source/drain region 225 of silicon dioxide layer and part to exposing P wellblock 224 in the dry ecthing mode.Because dry ecthing is to the etching speed difference of different directions, therefore will be at the side residual fraction silicon dioxide of dielectric layer 222 and conducting region 214b, and the edge slyness of this residual silicon dioxide.Come in exposed P wellblock 224, to inject first alloy (is the P+ semiconductor substance at this) of high concentration again, fasten plug 227 to form P with the ion injection mode.The thickness that remains in the silicon dioxide of dielectric layer 222 and conducting region 214b side can influence passage (Channel) length of N type double diffusion MOS power transistors, and the thickness of residual silicon dioxide depends on the deposit thickness of silicon dioxide layer 226.Therefore, the present invention can by control silicon dioxide layer 226 thickness control the passage length of N type double diffusion MOS power transistors.
See also shown in Fig. 3 E, grind, until exposing contact hole 228 in the cmp mode.Because conducting part 221a than gate electrode 221 height, causes gate electrode 221 exposed so cmp can't remove dielectric layer 222.In the N type double diffusion MOS power transistors of the present invention, in fact the quantity of contact hole 228 then look the required conduction current of circuit or other consideration decides, and is generally most.
See also shown in Fig. 3 F and Fig. 3 G, form a metal level 230, and form the 3rd photoresist layer 232 with the source of defining/drain region pad 230b, gate regions pad 230c and defence ring metal 230a with the 3rd photomask.
Aforesaid embodiment, N type double diffusion MOS power transistors only use three road photomask manufacturings to finish, and make compared to seven known road photomasks, have significantly reduced the cost of photomask.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (25)
1, a kind of semiconductor structure is characterized in that it comprises:
There are a plurality of operating units one operating space in this operating space, those operating units receive a control signal, and according to this control signal operation; And
One conducting region is electrically connected to those operating units, so that this control signal is reached those operating units;
Wherein, this conducting region has an assisted parts, a conducting part and a contact site, this assisted parts is made of non-conductive material, and separate out a plurality of spaces, this conducting part is made of conductor material, be formed on those spaces and electrically connect those operating units, this conducting region is removed the part conducting region to form at least one contact hole and to expose this assisted parts of part, and this contact site is formed on this at least one contact hole to receive this control signal and to electrically connect with this conducting part.
2, semiconductor structure according to claim 1 is characterized in that wherein said at least one contact hole is to form in the dry ecthing mode.
3, semiconductor structure according to claim 2 is characterized in that wherein said conducting part is made of polysilicon.
4, semiconductor structure according to claim 1 is characterized in that wherein said assisted parts forms simultaneously when forming the field oxide of a defence ring.
5, a kind of double diffusion MOS power transistors is characterized in that it comprises:
One conducting region is in order to receive a grid control signal; And
One transistor area has a plurality of double diffusion MOS power transistors in this transistor area, each double diffusion MOS power transistors has a grid and is electrically connected to this conducting region, to operate according to this grid control signal;
Wherein, this conducting region has an assisted parts, a conducting part and a contact site, this assisted parts is made of non-conductive material, and separate out a plurality of spaces, this conducting part is made of conductor material, be formed on those spaces and electrically connect those operating units, this conducting region is removed the part conducting region to form at least one contact hole and to expose this assisted parts of part, and this contact site is formed on this at least one contact hole to receive this grid control signal and to electrically connect with this conducting part.
6, double diffusion MOS power transistors according to claim 5, it is characterized in that it also comprises the periphery of at least one defence ring position in this conducting region and this transistor area, wherein this assisted parts forms when forming the field oxide of this at least one defence ring simultaneously.
7, double diffusion MOS power transistors according to claim 6 is characterized in that wherein said conducting part is made of polysilicon.
8, double diffusion MOS power transistors according to claim 6 is characterized in that wherein said at least one contact hole is to form in the dry ecthing mode.
9, double diffusion MOS power transistors according to claim 8 is characterized in that it also comprises a dielectric layer and is formed on this conducting region, and this dielectric layer of part that is positioned on this contact hole is removed when dry ecthing.
10, double diffusion MOS power transistors according to claim 9 is characterized in that wherein said dielectric layer comprises a silicon nitride layer.
11, a kind of MOS power transistors manufacture method is characterized in that it may further comprise the steps:
A. form a field oxide layer on the semiconductor substrate, this field oxide layer comprises a defence portion and an assisted parts;
B. form a grid oxic horizon, a gate electrode and a dielectric layer in regular turn on this semiconductor-based end, to define the grid of a plurality of MOS power transistors, wherein this grid oxic horizon, this gate electrode and this dielectric layer are formed on this assisted parts, and this grid oxic horizon, this gate electrode and this dielectric layer of this assisted parts top are that part is removed, and expose this gate electrode of part to form at least one grid contact hole;
C. form a plurality of wellblocks and multiple source/drain region within this semiconductor-based end; And
D. form a metal level on those source/drain regions and this at least one grid contact hole, and remove this metal level of part to define one a source/drain region pad and a gate pad.
12, MOS power transistors manufacture method according to claim 11 is characterized in that wherein said b step comprises:
B1. form a grid oxic horizon, a gate electrode and a dielectric layer in regular turn on this semiconductor-based end; And
B2. remove this grid oxic horizon, this gate electrode and this dielectric layer on this defence portion, this wellblock, and this grid oxic horizon of the part on this assisted parts, this gate electrode and this dielectric layer.
13, MOS power transistors manufacture method according to claim 12 is characterized in that wherein said b2 step is to remove this grid oxic horizon, this gate electrode and this dielectric layer with dry ecthing.
14, MOS power transistors manufacture method according to claim 13 is characterized in that wherein said dielectric layer is a silicon nitride.
15,, it is characterized in that wherein said c step comprises according to the described MOS power transistors manufacture method of arbitrary claim in the claim 11 to 12:
C1. inject first kind of alloy within this semiconductor-based end to form these a plurality of wellblocks;
C2. inject first kind of alloy within these a plurality of wellblocks to form this multiple source/drain region;
C3. form the monoxide layer;
C4. remove this oxide skin(coating) in the dry ecthing mode and at the side residual fraction oxide of this at least one grid contact hole and this gate electrode; And
C5. remove the zone of this exposed multiple source/drain region, to expose the subregion of these a plurality of wellblocks.
16, a kind of semiconductor structure is characterized in that it comprises:
There are a plurality of operating units one operating space in this operating space, those operating units receive a control signal, and according to this control signal operation; And
One conducting region is electrically connected to those operating units, so that this control signal is reached those operating units;
Wherein, this conducting region has an assisted parts, a conducting part and a contact site, this assisted parts is made of non-conductive material, this conducting part is made of conductor material, be formed on this assisted parts and electrically connect those operating units, this conducting region is with the exposed at least one contact hole of cmp mode, and this contact site is formed on this at least one contact hole to receive this control signal and to electrically connect with this conducting part.
17, semiconductor structure according to claim 16 is characterized in that wherein said conducting part is made of polysilicon.
18, semiconductor structure according to claim 16 is characterized in that wherein said assisted parts forms simultaneously when forming the field oxide of a defence ring.
19, a kind of double diffusion MOS power transistors is characterized in that it comprises:
One conducting region is in order to receive a grid control signal; And
One transistor area has a plurality of double diffusion MOS power transistors in this transistor area, each double diffusion MOS power transistors has a grid and is electrically connected to this conducting region, to operate according to this grid control signal;
Wherein, this conducting region has an assisted parts, a conducting part and a contact site, this assisted parts is made of non-conductive material, this conducting part is made of conductor material, be formed on this assisted parts and electrically connect those operating units, this conducting region is with the exposed at least one contact hole of cmp mode, and this contact site is formed on this at least one contact hole to receive this grid control signal and to electrically connect with this conducting part.
20, double diffusion MOS power transistors according to claim 19, it is characterized in that it also comprises the periphery that at least one defence ring is positioned at this conducting region and this transistor area, wherein this assisted parts forms when forming the field oxide of this at least one defence ring simultaneously.
21, double diffusion MOS power transistors according to claim 20 is characterized in that wherein said conducting part is made of polysilicon.
22, a kind of MOS power transistors manufacture method is characterized in that it may further comprise the steps:
A. form a field oxide layer on the semiconductor substrate, this field oxide comprises a defence portion and an assisted parts;
B. form a grid oxic horizon, a gate electrode and an insulating barrier in regular turn on this semiconductor-based end, to define the grid of a plurality of MOS power transistors, wherein this grid oxic horizon, this gate electrode and this dielectric layer are formed on this assisted parts;
C. form a plurality of wellblocks and multiple source/drain region within this semiconductor-based end;
D. remove this dielectric layer of this assisted parts top in the cmp mode, expose this gate electrode of part to form at least one grid contact hole; And
E. form a metal level on those source/drain regions and this at least one grid contact hole, and remove the part metals layer to define one a source/drain region pad and a gate pad.
23, MOS power transistors manufacture method according to claim 22 is characterized in that wherein said b step comprises:
B1. form a grid oxic horizon, a gate electrode and an insulating barrier in regular turn on this semiconductor-based end; And
B2. remove this grid oxic horizon, this gate electrode and this dielectric layer that reach top between this defence portion and this assisted parts between this defence portion, this defence portion.
24, MOS power transistors manufacture method according to claim 23 is characterized in that wherein said dielectric layer is a silicon nitride.
25,, it is characterized in that wherein said c step comprises according to the described MOS power transistors manufacture method of arbitrary claim in the claim 22 to 23:
C1. inject first kind of alloy within this semiconductor-based end to form these a plurality of wellblocks;
C2. inject first kind of alloy within these a plurality of wellblocks to form this multiple source/drain region;
C3. form the monoxide layer;
C4. remove this oxide skin(coating) in the dry ecthing mode and at the side residual fraction oxide of this at least one grid contact hole and this gate electrode; And
C5. remove the zone of this exposed multiple source/drain region, to expose the subregion of these a plurality of wellblocks.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102403223A (en) * | 2011-10-25 | 2012-04-04 | 丹东安顺微电子有限公司 | Method for manufacturing power transistor of improving uniformity of storage time Ts |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102403223A (en) * | 2011-10-25 | 2012-04-04 | 丹东安顺微电子有限公司 | Method for manufacturing power transistor of improving uniformity of storage time Ts |
| CN102403223B (en) * | 2011-10-25 | 2013-04-17 | 丹东安顺微电子有限公司 | Method for manufacturing power transistor of improving uniformity of storage time Ts |
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