CN101639497B - Static estimating method of maximum overturning electric current in distributed sleep tube power gate control circuit - Google Patents

Abstract

The invention provides a static estimating method of maximum overturning electric current in distributed sleep transistor power gate control circuit, solving the problems of long consumption time for computing the overturning electric current of the power gate control circuit and inaccurate numerical value. The method comprises the following steps of: selecting a digital integrated circuit layout; setting a plurality of standard cells in each row of the digital integrated circuit layout to be one cluster; distributing a sleep transistor to the each cluster; computing one standard cell according to the overturn characteristic of a single phase inverter in the digital integrated circuit; obtaining a peek value electric current; time sequence analyzing the each standard cell with a static time sequence analyzing tool; obtaining the sum electric current of the standard cells in the each cluster according to the result of a time sequence analyzing report; overlapping the electric current value of the standard cells in the same cluster; and obtaining the maximum overturning electric current of the each cluster. The method is applicable to designing a clustering power gate control sleep transistor in a semicustom digital circuit.

Description

The static estimating method of maximum reset current in the distributed sleep transistor power gating circuit

Technical field

The present invention relates to the power gating circuit, be specifically related to the evaluation method of maximum reset current in the distributed sleep transistor network power gating circuit.

Background technology

Along with the progress of semiconductor process techniques, the continuous reduction of characteristic line breadth, the ratio that leakage power accounts for the digital integrated circuit total power consumption increases gradually.The power gating technology is a kind of being widely used in the digital circuit, reduces the designing technique of the leakage power of circuit.The principle of power gating circuit is as shown in Figure 1: add sleep transistor insertion between the power lead of circuit or ground wire and logical circuit, when logical circuit was in holding state, the control sleep transistor insertion turn-offed, thereby reduces leakage current.Adopt NMOS to be commonly referred to footer, become header when adopting PMOS as sleep transistor insertion as sleep transistor insertion.Tie point between sleep transistor insertion and the logical circuit becomes virtually (VGND) or virtual power supply (VVDD).The optimal design of sleep transistor insertion area is the key of power gating circuit.Delay τ in the digital integrated circuit can represent with formula one:

Formula one: $\mathrm{\τ}\∝\frac{C_{\mathrm{load}}{V}_{\mathrm{DD}}}{K{(V_{\mathrm{DD}}-V_{\mathrm{th}})}^{\mathrm{\α}}}$

In formula one, C _LoadBe circuit load electric capacity, V _DDBe supply voltage, V _ThBe device threshold voltage, α is the constant relevant with technology, gets 1 usually, and K is a constant.Add sleep transistor insertion in circuit after, circuit delay becomes τ _Sleep:

Formula two: ${\mathrm{\τ}}_{\mathrm{sleep}}=\frac{C_{\mathrm{load}}{V}_{\mathrm{DD}}}{K{(V_{\mathrm{DD}}-\mathrm{\ΔV}-V_{\mathrm{th}})}^{\mathrm{\α}}}$

Wherein Δ V is the pressure drop on the sleep transistor insertion.When the circuit operate as normal, sleep transistor insertion is operated in dark linear zone, can equivalence be a resistance R _STThen Δ V is expressed as Δ V=IR _ST, wherein I is the reset current in the circuit; Be circuit when operate as normal, input signal changes the electric current in the circuit cause.The meaning of Δ V is exactly a circuit when upset takes place so, the pressure drop that produces on the sleep transistor insertion.The sleep transistor insertion resistance R _STBe inversely proportional to its channel width.Can get thus, the size of sleep transistor insertion reduces, R _STIncrease, then in circuit under the certain situation of reset current, Δ V increases, thereby postpones τ _SleepIncrease.Yet, if the size of sleep transistor insertion increases, not only cause redundant the increasing of area of circuit, the leakage current in the circuit is increased.

The design of sleep transistor insertion is abstract can to make the problem of sleep transistor insertion total area minimum under the certain condition of Δ V, shown in formula three:

object：min∑W _ST

Formula three:

subjected?toΔV≤V _c

Described W _STBe the sleep transistor insertion overall width, the length of sleep transistor insertion is the channel length minimum dimension, so its total area can be represented with overall width.V _cBe the relevant confinement voltage of circuit delay.With Δ V=IR _STAs can be known, the calculating of the reset current I of circuit occupies the status of core in the sleep transistor insertion size design in the substitution formula three.

In the power gating circuit, the computing method of reset current I are divided into two classes: the one, obtain by circuit simulation, and the 2nd, use some algorithm circuit analysis is obtained.Circuit for the n input need carry out at least 2 ⁿEmulation, expend a large amount of time, thereby circuit emulation method is not suitable for fairly large circuit.And calculate the algorithm of reset current at present, as genetic algorithm, fixing duration and become method such as duration division, be not suitable for larger circuit equally.These methods when rated output gating circuit reset current, the length that not only expends time in, and the numerical value that obtains is bigger than normal, influences constraint condition, the sleep transistor insertion size that obtains thus is bigger than normal.

Summary of the invention

The present invention solves the length that expends time in when calculating power gating circuit reset current in the prior art, and the inaccurate problem of the numerical value that obtains, and the static estimating method of maximum reset current in a kind of distributed sleep transistor power gating circuit is provided.This method is finished by following steps:

Step 1: select the digital integrated circuit domain, a plurality of standard blocks in every row of described digital integrated circuit domain are set to cluster, described each bunch distributed a sleep transistor insertion, described sleep transistor insertion is connected between positive source and each bunch, and the virtual power supply of each sleep transistor insertion is linked together;

Step 2: according to the rollover characteristics of the single phase inverter in the digital integrated circuit, the reset current of a standard block in the step 1 is calculated, obtain average current I _{Cell_avg}With peak point current I _{Cell_max}, described average current I _{Cell_avg}Be peak point current I _{Cell_max}1/2nd; Described average current I _{Cell_avg}Represent by formula four:

Formula four: $I_{\mathrm{cell}\_\mathrm{avg}}=\frac{E_{\mathrm{internal}}}{\mathrm{Vdd}\·t}$

Described E _InternalBe circuit inside energy consumption, t is the T.T. of electric current switching process, and described t is represented by formula five:

Formula five: t=0.5t _Tran+ t _Delay+ t _Rise

Described t _TranFor importing switching time, t _DelayBe circuit delay time, t _RiseFor output switching time,

Can obtain peak point current I by formula four and formula five _{Cell_max}, represent by formula six:

Formula six: $I_{\mathrm{cell}\_\max }={2I}_{\mathrm{cell}\_\mathrm{avg}}=\frac{2\left(E_{\mathrm{internal}}{+C_{\mathrm{load}}\mathrm{Vdd}}^2\right)}{\mathrm{Vdd}(0.5t_{\mathrm{tran}}+t_{\mathrm{delay}}+0.5t_{\mathrm{rise}})}$

C in the formula _LoadBe load capacitance, Vdd is a supply voltage;

Step 3: adopt static timing analysis tool Prime Time that each standard block is carried out time series analysis, generate the time series analysis report, obtain the time series analysis result;

Step 4: according to the time series analysis result who obtains in the step 3, with the reset current I of i standard block _iWith a plurality of times to t _In ⁱ, t _Out ⁱWith the peak point current I that obtains in the step 2 _{Cell_max}Expression:

When $t_{\mathrm{in}}^i\≤t\≤\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2}$ The time $I_i=\frac{{2I}_{\mathrm{cell}\_\max }}{t_{\mathrm{out}}^i-t_{\mathrm{in}}^i}(\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2}-t)$

When $\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2}\≤t\≤t_{\mathrm{out}}^i$ The time $I_i=\frac{2I_{\mathrm{cell}\_\max }}{t_{\mathrm{out}}^i-t_{\mathrm{in}}^i}(t-\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2})$

T in the formula _In ⁱWith t _Out ⁱRepresent the time that the reset current signal of time that the reset current signal of i standard block arrives and i standard block leaves respectively; Total electric current I with a plurality of standard blocks in each bunch _sRepresent with formula seven:

Formula seven: $I_s=\underset{1\≤i\≤n}{\mathrm{\Σ}}{I}_i$

N is a natural number in the formula, represents the number of the standard block in this bunch;

Step 5: adopt formula seven to superpose, obtain the maximum reset current I of each bunch with the current waveform value of a plurality of standard blocks in the cluster _{C_max}

Beneficial effect of the present invention: adopt the method for the invention that reset current is estimated, expending time in computation process is 60% to 70% of prior art, and the numerical value that obtains is compared with the numerical value that adopts prior art to obtain, accurately about 50%, reduce calculated amount and computation complexity simultaneously, and shortened the design cycle of power gating circuit.

Description of drawings

Fig. 1 is the electrical block diagram that adds sleep transistor insertion in the prior art between the power lead of power gating circuit and logical circuit, Fig. 2 is the electrical block diagram that adds sleep transistor insertion in the prior art between the power ground of power gating circuit and logical circuit, Fig. 3 is the structural representation that the present invention is based on the digital integrated circuit domain of standard block, the 1st, standard block, Fig. 4 is by the synoptic diagram of row after the sub-clustering with domain among Fig. 3, Fig. 5 is the structural representation after adding a sleep transistor insertion on the basis of Fig. 4 in every bunch, Fig. 6 is the linear model synoptic diagram of distributed sleep transistor power gating circuit shown in Figure 5, Fig. 7 is the schematic diagram of reset current in the digital integrated circuit, Fig. 8 is the input voltage of the single phase inverter in the digital integrated circuit, output voltage and reset current waveform synoptic diagram, Fig. 9 is a synoptic diagram of representing digital integrated circuit shown in Figure 3 with the form of digraph, and Figure 10 is each standard block current waveform synoptic diagram.

Embodiment

Embodiment one: in conjunction with Fig. 1 to Figure 10 this embodiment is described, the described method of present embodiment is finished by following steps:

Step 1: select the digital integrated circuit domain, a plurality of standard blocks in every row of described digital integrated circuit domain are set to cluster, described each bunch distributed a sleep transistor insertion, described sleep transistor insertion is connected between positive source and each bunch, and the virtual power supply of each sleep transistor insertion is linked together;

Step 2: according to the rollover characteristics of the single phase inverter in the digital integrated circuit, the reset current of a standard block in the step 1 is calculated, obtain average current I _{Cell_avg}With peak point current I _{Cell_max}, described average current I _{Cell_avg}Be peak point current I _{Cell_max}1/2nd; Described average current I _{Cell_avg}Represent by formula four:

Formula four: $I_{\mathrm{cell}\_\mathrm{avg}}=\frac{E_{\mathrm{internal}}}{\mathrm{Vdd}\·t}$

Described E _InternalBe circuit inside energy consumption, t is the T.T. of electric current switching process, and described t is represented by formula five:

Formula five: t=0.5t _Tran+ t _Delay+ t _Rise

Described t _TranFor importing switching time, t _DelayBe circuit delay time, t _RiseFor output switching time,

Can obtain peak point current I by formula four and formula five _{Cell_max}, represent by formula six:

Formula six: $I_{\mathrm{cell}\_\max }={2I}_{\mathrm{cell}\_\mathrm{avg}}=\frac{2\left(E_{\mathrm{internal}}{+C_{\mathrm{load}}\mathrm{Vdd}}^2\right)}{\mathrm{Vdd}(0.5t_{\mathrm{tran}}+t_{\mathrm{delay}}+0.5t_{\mathrm{rise}})}$

C in the formula _LoadBe load capacitance, Vdd is a supply voltage;

Step 3: adopt static timing analysis tool Prime Time that each standard block is carried out time series analysis, generate the time series analysis report, obtain the time series analysis result;

Step 4: according to the time series analysis result who obtains in the step 3, with the reset current I of i standard block _iWith a plurality of times to t _In ⁱ, t _Out ⁱWith the peak point current I that obtains in the step 2 _{Cell_max}Expression:

When $t_{\mathrm{in}}^i\≤t\≤\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2}$ The time $I_i=\frac{{2I}_{\mathrm{cell}\_\max }}{t_{\mathrm{out}}^i-t_{\mathrm{in}}^i}(\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2}-t)$

When $\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2}\≤t\≤t_{\mathrm{out}}^i$ The time $I_i=\frac{2I_{\mathrm{cell}\_\max }}{t_{\mathrm{out}}^i-t_{\mathrm{in}}^i}(t-\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2})$

T in the formula _In ⁱWith t _Out ⁱRepresent the time that the reset current signal of time that the reset current signal of i standard block arrives and i standard block leaves respectively; Total electric current I with a plurality of standard blocks in each bunch _sRepresent with formula seven:

Formula seven: $I_s=\underset{1\≤i\≤n}{\mathrm{\Σ}}{I}_i$

N is a natural number in the formula, represents the number of the standard block in this bunch;

Step 5: adopt formula seven to superpose, obtain the maximum reset current I of each bunch with the current waveform value of a plurality of standard blocks in the cluster _{C_max}

Fig. 3 in the present embodiment is the whole domain of integrated circuit, and 1 represents standard block, and wherein each bunch in the domain is made up of a plurality of standard blocks, and described each standard block is the integrated circuit of power consumption minimum in the digital integrated circuit; Fig. 4 is to be a logical circuit with each bunch abstract representation among Fig. 3; Fig. 5 is the circuit structure that the inventive method is suitable for, and it is to add a sleep transistor insertion on the basis of Fig. 4 between each bunch and power supply, and the virtual power supply VVDD end of all sleep transistor insertions is linked together.Described sleep transistor insertion is operated in dark linear zone when opening, at this moment, Fig. 5 can be expressed as the form of Fig. 6, described sleep transistor insertion ST ₁, ST ₂, ST ₃ST _nBe equivalent to linear resistance R _C1, R _C2, R _C3R _Cn, the logical circuit of each bunch is equivalent to current source I _C1, I _C2, I _C3I _CnRepresent the reset current of single phase inverter in the digital integrated circuit and the relation between its input voltage output voltage with Fig. 8, the switching process of electric current is: when input voltage vin when supply voltage Vdd begins to descend, reset current linear the increasing of starting from scratch, reduce to 0V up to input voltage vin, reset current is increased to average current I _{Cell_avg}, described reset current continues to increase, when reaching peak point current I _{Cell_max}In time, begin to descend, when described reset current drops to average current I _{Cell_avg}The time, output voltage V out begins during from 0V to increase, and increases to supply voltage Vdd up to output voltage V out, and described reset current is from average current I _{Cell_avg}Drop to 0, realize the electric current upset; Figure 10 be with the reset current of each standard block with a plurality of times to t _In ¹With t _Out ¹, t _In ²With t _Out ²T _In ⁿWith t _Out ⁿAnd peak point current I _{Cell_max}Expression.

The domain of the described digital integrated circuit of the described step 1 of present embodiment generates by the laying out pattern file, and is made up of a plurality of standard blocks.

The described digital integrated circuit of present embodiment can be represented with the form of digraph, referring to Fig. 9.

The described sleep transistor insertion of present embodiment can be selected pmos type, also can select nmos type, and the sleep transistor insertion described in the present embodiment is a pmos type;

The maximum reset current of the described sleep transistor insertion of present embodiment occurs in the process of circuit to the load capacitance charging; When described sleep transistor insertion was pmos type, maximum reset current occurred in the process of circuit to the load capacitance charging, and referring to Fig. 7, described process to the load capacitance charging is meant that the circuit output node is turned to the process of high level from low level; When described sleep transistor insertion was nmos type, described process to the load capacitance charging was meant that the circuit output node is turned to low level process from high level.

Obtain peak point current I in the formula five of the described step 2 of present embodiment _{Cell_max}Formula in the liberty library format file of parameter by Synopsys company exploitation in table look-up and obtain described parameter value.

Input t switching time in the liberty library format file of the described Synopsys of present embodiment company exploitation _TranWith output t switching time _RiseBe meant input signal from 10% be transformed into 90% or input signal be transformed into for 10% time from 90%.

The time series analysis that generates in the described step 3 of present embodiment report comprises the time sequence information relevant with reset current, and when described relevant time sequence information extracted employing be the Per1 language.

Parameters such as the size of the described maximum reset current of present embodiment and node capacitor, rising delay, input switching time and output switching time interrelate, node capacitor is big more, input signal switching time, circuit delay and output signal are more little switching time, and reset current is big more.

Claims (8)

1. the static estimating method of maximum reset current in the distributed sleep transistor power gating circuit,

It is characterized in that it is finished by following steps:

Step 1: select the digital integrated circuit domain, a plurality of standard blocks in every row of described digital integrated circuit domain are set to cluster, described each bunch distributed a sleep transistor insertion, described sleep transistor insertion is connected between positive source and each bunch, and the virtual power supply of each sleep transistor insertion is linked together;

Step 2: according to the rollover characteristics of the single phase inverter in the digital integrated circuit, the reset current of a standard block in the step 1 is calculated, obtain average current I _{Cell_avg}With peak point current I _{Cell_max}, described average current I _{Cell_avg}Be peak point current I _{Cell_max}1/2nd; Described average current I _{Cell_avg}Represent by formula four:

Formula four: $I_{\mathrm{cell}\_\mathrm{avg}}=\frac{E_{\mathrm{internal}}}{\mathrm{Vdd}\·t}$

Described E _InternalBe circuit inside energy consumption, t is the T.T. of electric current switching process, and described t is represented by formula five:

Formula five: t=0.5t _Tran+ t _Delay+ t _Rise

Described t _TranFor importing switching time, t _DelayBe circuit delay time, t _RiseFor output switching time,

Can obtain peak point current I by formula four and formula five _{Cell_max}, represent by formula six:

Formula six: $I_{\mathrm{cell}\_\max }={2I}_{\mathrm{cell}\_\mathrm{avg}}=\frac{2\left(E_{\mathrm{internal}}{+C_{\mathrm{load}}\mathrm{Vdd}}^2\right)}{\mathrm{Vdd}(0.5t_{\mathrm{tran}}+t_{\mathrm{delay}}+0.5t_{\mathrm{rise}})}$

C in the formula _LoadBe load capacitance, Vdd is a supply voltage;

Step 3: adopt static timing analysis tool Prime Time that each standard block is carried out time series analysis, generate the time series analysis report, obtain the time series analysis result;

Step 4: according to the time series analysis result who obtains in the step 3, with the reset current I of i standard block _iWith a plurality of times to t _In ⁱ, t _Out ⁱWith the peak point current I that obtains in the step 2 _{Cell_max}Expression:

When $t_{\mathrm{in}}^i\≤t\≤\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2}$ The time $I_i=\frac{{2I}_{\mathrm{cell}\_\max }}{t_{\mathrm{out}}^i-t_{\mathrm{in}}^i}(\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2}-t)$

When $\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2}\≤t\≤t_{\mathrm{out}}^i$ The time $I_i=\frac{2I_{\mathrm{cell}\_\max }}{t_{\mathrm{out}}^i-t_{\mathrm{in}}^i}(t-\frac{t_{\mathrm{in}}^i+t_{\mathrm{out}}^i}{2})$

T in the formula _In ⁱWith t _Out ⁱRepresent the time that the reset current signal of time that the reset current signal of i standard block arrives and i standard block leaves respectively; Total electric current I with a plurality of standard blocks in each bunch _sRepresent with formula seven:

Formula seven: $I_s=\underset{1\≤i\≤n}{\mathrm{\Σ}}{I}_i$

N is a natural number in the formula, represents the number of the standard block in this bunch;

Step 5: adopt formula seven to superpose, obtain the maximum reset current I of each bunch with the current waveform value of a plurality of standard blocks in the cluster _{C_max}

2. the static estimating method of maximum reset current in the distributed sleep transistor power gating circuit according to claim 1 is characterized in that described sleep transistor insertion is a kind of in pmos type or the nmos type.

3. the static estimating method of maximum reset current in the distributed sleep transistor power gating circuit according to claim 2, the maximum reset current that it is characterized in that described sleep transistor insertion occurs in the process of circuit to the load capacitance charging, described sleep transistor insertion is a pmos type, and the process that load capacitance is charged is the circuit output node is turned to high level from low level a process.

4. the static estimating method of maximum reset current in the distributed sleep transistor power gating circuit according to claim 2, the maximum reset current that it is characterized in that described sleep transistor insertion occurs in the process of circuit to the load capacitance charging, described sleep transistor insertion is a nmos type, and the process that load capacitance is charged is that the circuit output node is turned to low level process from high level.

5. the static estimating method of maximum reset current in the distributed sleep transistor power gating circuit according to claim 1, it is characterized in that tabling look-up in the liberty library format file of parameter by the exploitation of Synopsys company in the formula six of step 2 obtains.

6. the static estimating method of maximum reset current in the distributed sleep transistor power gating circuit according to claim 5 is characterized in that input t switching time in the liberty libraryformat file of described Synopsys company exploitation _TranWith output t switching time _RiseBe meant: input signal from 10% be transformed into 90% or input signal be transformed into for 10% time from 90%.

7. the static estimating method of maximum reset current in the distributed sleep transistor power gating circuit according to claim 1 is characterized in that it is the Perl language that step 3 is generated what adopt when information in the time series analysis report is extracted.

8. the static estimating method of maximum reset current in the distributed sleep transistor power gating circuit according to claim 1 is characterized in that the size of the described maximum reset current of step 5 and node capacitor, rising delay, input t switching time _TranWith output t switching time _RiseRelating to parameters.

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