CN109388839A - Clock system method for analyzing performance and device - Google Patents
Clock system method for analyzing performance and device Download PDFInfo
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Abstract
The present invention provides a kind of clock system method for analyzing performance and device.This method comprises: obtaining the parasitic parameter and the first emulation netlist of the interconnection line of clock system to be analyzed, time delay is added in the corresponding parameter of each afterbody phase inverter in the first emulation netlist, form the second emulation netlist delayed when addition, time delay is according to obtained by the ideal time delay of the phase inverter on each clock path and the fluctuation time delay of phase inverter, the fluctuation time delay of phase inverter is caused by piece fluctuation, according to the second emulation netlist and the parasitic parameter of interconnection line, determine the clock jitter of clock system to be analyzed, on the one hand it realizes in clock system performance evaluation, it considers and fluctuates time delay caused by piece fluctuation, improve the accuracy of the clock jitter analysis to clock system, on the other hand, it does not need again to emulate entire clock network, shorten simulation time, improve the clock jitter to clock system The efficiency of analysis.
Description
Technical Field
The present invention relates to computer technologies, and in particular, to a method and an apparatus for analyzing clock system performance.
Background
In the field of integrated circuit design, a clock system is a key for enabling an integrated circuit to work normally. As high performance integrated circuits become larger and more complex, the requirements on the performance of the clock system (e.g., clock skew) become higher and higher.
At present, complete monte carlo simulation is mainly performed in a full-customization mode, and clock deviation of a clock system is analyzed.
However, the analysis method needs a long time and is inefficient, and the simulation process takes incomplete factors into consideration, so that the clock deviation of the clock system cannot be accurately analyzed.
Disclosure of Invention
The invention provides a method and a device for analyzing the performance of a clock system, which aim to solve the technical problems that the time is long, the efficiency is low and the clock deviation cannot be accurately analyzed when the clock deviation of the clock system is analyzed at present.
In a first aspect, the present invention provides a method for analyzing clock system performance, including:
acquiring parasitic parameters of an interconnection line of a clock system to be analyzed and a first simulation netlist; the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, the clock grid is connected with a load, and the first simulation netlist comprises the connection relation of the inverters in the clock system;
adding time delay to parameters corresponding to last-stage inverters of all clock paths in the first simulation netlist to form a second simulation netlist after the time delay is added; the time delay is obtained according to the ideal time delay of the phase inverter on each clock path and the fluctuation time delay of the phase inverter, and the fluctuation time delay of the phase inverter is caused by on-chip fluctuation;
and determining the clock deviation of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line.
In the method shown above, the determining a clock bias of the clock system to be analyzed according to the second simulated netlist and the parasitic parameters of the interconnection line includes:
determining a time delay sample of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line;
and determining the statistic of the clock deviation of the clock system to be analyzed according to the time delay sample.
In the method as shown above, after determining the statistics of the clock skew of the clock system to be analyzed from the samples of the time delay, the method further comprises:
and determining whether the design conservative quantity of the clock system to be analyzed is reasonable or not according to the statistic quantity of the clock deviation.
In the method shown above, before adding a delay to a parameter corresponding to a last-stage inverter of each clock path in the first simulated netlist and forming a second simulated netlist after adding the delay, the method further includes:
acquiring the fluctuation time delay of the inverter caused by the on-chip fluctuation in an experimental mode; or,
acquiring fluctuation time delay of each inverter caused by on-chip fluctuation through a probability density function; wherein the ripple time delay of each inverter caused by the on-chip ripple follows a normal distribution.
In the method as shown above, the obtaining parasitic parameters of the interconnection line of the clock system to be analyzed and the first simulated netlist includes:
acquiring parasitic parameters of the interconnection line through a parasitic parameter extraction tool;
and acquiring the first simulated netlist through a circuit simulation tool.
In a second aspect, the present invention provides a clock system performance analysis apparatus, including:
the first acquisition module is used for acquiring parasitic parameters of an interconnection line of a clock system to be analyzed and a first simulation netlist; the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, the clock grid is connected with a load, and the first simulation netlist comprises the connection relation of the inverters in the clock system;
the adding module is used for adding time delay in parameters corresponding to last-stage inverters of all clock paths in the first simulation netlist to form a second simulation netlist after the time delay is added; the time delay is obtained according to the ideal time delay of the phase inverter on each clock path and the fluctuation time delay of the phase inverter, and the fluctuation time delay of the phase inverter is caused by on-chip fluctuation;
and the first determining module is used for determining the clock deviation of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line.
In the above apparatus, the first determining module is specifically configured to:
determining a time delay sample of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line;
and determining the statistic of the clock deviation of the clock system to be analyzed according to the time delay sample.
In the apparatus as described above, the apparatus further comprises:
and the second determining module is used for determining whether the design conservative quantity of the clock system to be analyzed is reasonable or not according to the statistic quantity of the clock deviation.
In the apparatus as described above, the apparatus further comprises:
the second acquisition module is used for acquiring the fluctuation time delay of the inverter caused by the on-chip fluctuation in an experimental mode; or,
the third acquisition module is used for acquiring fluctuation time delay of each inverter caused by on-chip fluctuation through a probability density function; wherein the ripple time delay of each inverter caused by the on-chip ripple follows a normal distribution.
In the above apparatus, the first obtaining module is specifically configured to:
acquiring parasitic parameters of the interconnection line through a parasitic parameter extraction tool;
and acquiring the first simulated netlist through a circuit simulation tool.
In a third aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps of the clock system performance analysis method provided in the first aspect described above.
The method and the device for analyzing the performance of the clock system provided by the embodiment of the invention acquire the parasitic parameters of the interconnection line of the clock system to be analyzed and a first simulation netlist, wherein the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with the clock grid, the clock grid is connected with a load, the first simulation netlist comprises the connection relation of each inverter in the clock system, time delay is added in the parameter corresponding to the last stage of inverter of each clock path in the first simulation netlist to form a second simulation netlist after the time delay is added, wherein the time delay is obtained according to the ideal time delay of each inverter on each clock path and the fluctuation time delay of the inverter, the fluctuation time delay of the inverter is caused by on-chip fluctuation, according to the second simulation netlist and the parasitic parameters of the interconnection lines, the clock deviation of the clock system to be analyzed is determined, on one hand, fluctuation time delay caused by on-chip fluctuation is considered during performance analysis of the clock system, and accuracy of clock deviation analysis of the clock system is improved, on the other hand, the sum of ideal time delay and fluctuation time delay of all inverters on a clock path is added to the parameters corresponding to the last-stage inverter of the first simulation netlist, simulation of the whole clock network is not needed, simulation time is shortened, and efficiency of clock deviation analysis of the clock system is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flowchart of an embodiment of a clock system performance analysis method according to the present invention;
FIG. 2 is a schematic structural diagram of a clock system to be analyzed according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the time delay in the clock system shown in FIG. 2;
fig. 4 is a schematic structural diagram of an embodiment of a clock system performance analysis apparatus according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," and "fourth," if any, in the description and claims of the invention and in the above-described figures are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is a schematic flowchart of an embodiment of a clock system performance analysis method according to the present invention. As shown in fig. 1, the method for analyzing the performance of a clock system according to an embodiment of the present invention includes the following steps:
s101: and acquiring parasitic parameters of the interconnection line of the clock system to be analyzed and the first simulation netlist.
Wherein the topology of the clock system is a mesh structure. The clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, and the clock grid is connected with a load. The first simulated netlist comprises the connection relation of inverters in a clock system.
Specifically, fig. 2 is a schematic structural diagram of a clock system to be analyzed in the embodiment of the present invention. It should be noted that the clock system generally includes a global clock (global clock) system, a local clock (local clock) system, and a local clock (local clock) system. In high performance designs, the local clock system employs a clock mesh (clock mesh) structure, because the clock mesh structure can reduce clock skew and attenuate the on-chip ripple (on-chip) effect on the clock system. The clock system to be analyzed in the embodiment of the invention is an area clock system with a grid structure as a topological structure.
As shown in fig. 2, the clock system includes a pre-driver module 21, a clock grid 22, and a load 23. The pre-driver module 21 includes several stages of inverters 211 therein. Illustratively, the inverter 211 in the front stage driving module 21 is shown in fig. 2 as having three stages. The plurality of inverters 211 are connected in a tree structure. In the embodiment of the invention, the inverter of the root node is defined as a first-stage inverter, and the inverter at the tail end is defined as a last-stage inverter. In the preceding stage driving module 21, each stage of the inverters 211 except the first stage inverter is connected one upper stage inverter upward and at least two lower stage inverters downward. One end of the clock grid 22 is connected to each last stage inverter and the other end is connected to the load of the clock system. The clock grid 22 is made up of metal connecting wires. The load 23 is the destination of the clock system. The front-stage driving module 21 is composed of several stages of inverters 211 cascaded. The front-stage driving module 21 includes a plurality of clock paths therein. The clock path in the embodiment of the invention is a path from the first-stage inverter to the last-stage inverter through the inverters in the intermediate stages.
Embodiments of the present invention may be performed by a computing device having computing capabilities, such as a server, a Personal Computer (PC).
Optionally, in S101, the computing device may obtain parasitic parameters of the interconnect line through a parasitic parameter extraction tool. The parasitic parameter extraction tool may be a starRC. Parasitic parameters of the interconnect line include resistance parameters, capacitance parameters, and inductance parameters. The parasitic parameters of the interconnection line will affect the propagation delay and the flip time of the clock signal on the interconnection line, and therefore, the parasitic parameters of the interconnection line need to be extracted when analyzing the performance of the clock system. StarRC is a parasitic parameter extraction tool for an interconnection line of an integrated circuit layout, is a mature tool, and is not described in detail here in a specific acquisition process. The computing device may obtain a first simulated netlist via a circuit simulation tool. The circuit simulation tool may be HSPICE. HSPICE is a general-purpose circuit simulation program that performs simulations of circuit performance, such as steady-state analysis, transient analysis, and frequency domain analysis, in integrated circuit design. Optionally, the first simulated netlist further includes a parasitic parametric model of transistors in each inverter and a load capacitance of the clock system. The HSPICE model of the transistor abstracts the parameter details of the transistor into a mutual connection relation of resistance and capacitance. The inverter in the preceding stage driving module 21 in fig. 2 is composed of a plurality of transistors. Therefore, the first simulated netlist may include connection relationships of inverters in the clock system, a parasitic parametric model of transistors in the inverters, and a load capacitance of the clock system.
After the parasitic parameters of the interconnection line of the clock system and the first simulated netlist are obtained, the parasitic parameters of the interconnection line and the first simulated netlist can be used for representing the clock system.
S102: and adding time delay in parameters corresponding to the last-stage inverters of all the clock paths in the first simulated netlist to form a second simulated netlist after the time delay is added.
The time delay is obtained according to the ideal time delay of the inverter on each clock path and the fluctuation time delay of the inverter. The ripple delay of the inverter is caused by on-chip ripple.
Specifically, in the embodiment of the present invention, when performing clock skew analysis of a clock system, time delay caused by on-chip fluctuation is considered. The sources of on-chip fluctuations include three aspects: 1. process variation between different wafers, process variation in different regions of the same wafer; 2. noise of the power supply or instability of the power supply; 3. temperature fluctuation: the operating speed of the transistors is different in different ambient temperatures; temperature differences in different areas of the same chip. On-chip fluctuations may cause the delay of the device to change, so that the performance of the actually produced clock system is greatly different from the performance obtained by the static timing analysis method. Therefore, when the performance of the clock system is analyzed, the time delay caused by on-chip fluctuation is considered, and the accuracy of the clock deviation analysis can be improved.
In the embodiment of the invention, time delay is added to the parameters corresponding to the last-stage inverters of all the clock paths in the first simulation netlist. Fig. 3 is a schematic diagram of the time delay in the clock system shown in fig. 2. Each inverter has two time delays: the ideal delay of the inverter and the ripple delay of the inverter caused by on-chip ripple. As shown in a diagram of fig. 3, the time delay of the first stage inverter is an ideal time delay D0With its fluctuation time delay delta0The sum, i.e. the time delay of the first stage inverter is D0+Δ0. In other words, the time delay of each inverter is the ideal time delay DqAnd a fluctuation time delay delta corresponding theretoqAnd (3) the sum: dq+Δq。
The ideal time delay for each inverter can be obtained by static timing analysis methods. The ripple time delay of each inverter can be obtained by the following two implementation modes:
the first mode is as follows: and acquiring fluctuation time delay of each inverter caused by on-chip fluctuation in an experimental mode. The quantitative relationship between the fluctuating delay and the ideal delay may be determined experimentally, for example, the fluctuating delay may be 30% of the ideal delay. The second way is: and acquiring fluctuation time delay of each inverter caused by on-chip fluctuation through a probability density function. Wherein the ripple time delay of each inverter caused by on-chip ripple follows normal distribution. Optionally, the fluctuating delay may also follow other distributions.
For each last-stage inverter, there will be a plurality of inverters on its corresponding clock path, and added in the first simulated netlist is the sum of the ideal delay of all inverters on that clock path and the ripple delay corresponding to all inverters. It should be noted that all the inverters in the clock path corresponding to the last-stage inverter include the last-stage inverter itself.
As shown in the b diagram in fig. 3, the time delay added to the parameters corresponding to the inverter 33 in the first simulated netlist is: the sum of the ideal delay and ripple delay of inverter 30, the ideal delay and ripple delay of inverter 31, the ideal delay and ripple delay of inverter 33: d0+Δ0+D1+Δ1+D3+Δ3. The time delay added to the parameters corresponding to inverter 34 in the first simulated netlist is: the sum of the ideal delay and ripple delay of inverter 30, the ideal delay and ripple delay of inverter 31, the ideal delay and ripple delay of inverter 34: d0+Δ0+D1+Δ1+D4+Δ4. The time delay added to the parameters corresponding to inverter 35 in the first simulated netlist is: the sum of the ideal delay and ripple delay for inverter 30, the ideal delay and ripple delay for inverter 32, the ideal delay and ripple delay for inverter 35: d0+Δ0+D2+Δ2+D5+Δ5. The added delay in the parameters corresponding to inverter 36 in the first simulated netlist is: ideal time delay and ripple time delay of inverter 30, ideal time delay of inverter 32Delay and ripple delay, ideal delay of inverter 36 and sum of ripple delay: d0+Δ0+D2+Δ2+D6+Δ6. Namely, the fluctuation time delay caused by the on-chip fluctuation is injected into the parameter corresponding to the last stage inverter in a linear superposition mode.
S103: and determining the clock deviation of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection lines.
Specifically, the computing device may perform monte carlo simulation according to the second simulation netlist added with the fluctuation delay and the ideal delay and the parasitic parameters of the interconnection line, that is, according to the distribution form of the random variable, assign a value to the random variable, and determine the clock bias of the clock system to be analyzed, where the process may be: determining a time delay sample of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line; the statistics of the clock offset of the clock system to be analyzed are determined from the samples of the time delay.
More specifically, determining the time delay of a clock signal in the clock system to be analyzed to reach a clock port of a load according to the second simulation netlist and the parasitic parameters of the interconnection line; determining the statistic of time delay according to the time delay of the clock signal reaching a clock port of a load; and determining the statistic of the clock deviation according to the statistic of the time delay.
By TiRepresenting the time delay of the clock signal to the clock port of load i. T isiIs a random variable. After completing the Monte Carlo simulation, T can be obtainediThe sample value of (2). By analyzing the sample, T can be obtainediSuch as expectation, variance, standard deviation, etc. By TjRepresenting the time delay of the clock signal to the clock port of load j. Similarly, T can be obtainedjThe statistical quantity of (a). Clock skew Sij＝Ti-Tj. I.e. can be according to TiAnd TjTo obtain SijI.e. statistics of clock skew. In addition, random variables can be analyzed by statistical methods such as linear regressionThe correlation between them.
The clock system of the clock grid structure is a multi-drive clock network, the traditional static time sequence analysis method is not suitable for analyzing the clock deviation of the clock system of the grid structure, and in the existing physical design process, the simulation method is generally used for analyzing the clock deviation of the clock system of the clock grid structure. When the fully customized simulation is performed at present, the whole clock system needs to be simulated, and in order to ensure the sufficiency and completeness of the simulation, a designer needs to perform million-order simulation, which results in lower efficiency of clock deviation analysis of the clock system. In the embodiment of the invention, because the time delay is added in the parameters of the inverter at the last stage, only the clock grid and the load need to be simulated, and the large-scale simulation of the whole clock system is not needed. Therefore, the time required by simulation is shortened, and the simulation efficiency is improved.
Optionally, in this embodiment of the present invention, after determining the statistical quantity of the clock skew of the clock system to be analyzed according to the sample of the time delay, determining whether the design conservative quantity of the clock system to be analyzed is reasonable according to the statistical quantity of the clock skew is further included. At present, the time delay of a device may be changed due to on-chip fluctuation, so that the performance of an actually produced clock system is greatly different from the performance analyzed by a simulation method. If the amount of conservation is too large, timing closure becomes very difficult; if the amount of conservation is too small, the influence of on-chip fluctuations cannot be covered, and the yield (yield) is lowered. By analyzing the statistics of the clock deviations, the maximum average clock deviation of the clock grid and the standard deviation of the clock deviations can be specified. The standard deviation of the clock deviation can be used to determine whether the amount of conservatism left for the impact of on-chip fluctuations on the clock system is sufficient. For example, assuming that the clock deviation follows a normal distribution and its standard deviation is 1 picosecond (ps), then 6 standard deviations have a value of 6ps, and it can be determined from the statistics of the clock deviation that the likelihood of the clock deviation falling outside the interval of 6ps from the expected offset is only parts per billion. If the amount of design conservatism left is 7ps, i.e., the clock skew is considered to be a maximum of possibly 7ps from the expected skew, then this amount of design conservatism is sufficient to cover the effects of on-chip fluctuations on the clock system. By the method, whether the design conservative quantity is enough can be judged, so that the robustness of the clock system can be ensured, and the design conservative quantity can be reduced.
At present, a simulation method can be adopted to analyze the clock deviation of a clock system, and the clock deviation can be estimated by combining process deviation, specifically, the clock deviation is determined according to an induced clock deviation calculation formula, however, the clock deviation calculation formula induced by the method ignores the multi-drive characteristic of a clock grid, and is only suitable for a tree-type clock system and is not suitable for a regional clock system with a grid structure in the embodiment of the invention. In addition, steps of dividing horizontal and vertical banded regions and calibrating priorities, virtually adding a single trunk into the banded regions according to the priorities, estimating the total capacitance and the maximum deviation range of the current grid, traversing the banded regions and the like can be adopted to estimate the clock deviation of the clock system, but the performance analysis by adopting the scheme is lacked compared with a simulation method, and the influence of on-chip fluctuation on the performance of the clock system is not considered.
The clock system performance analysis device provided by the embodiment of the invention obtains the parasitic parameters of the interconnection line of the clock system to be analyzed and a first simulation netlist, wherein the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with the clock grid, the clock grid is connected with a load, the first simulation netlist comprises the connection relation of each inverter in the clock system, time delay is added in the parameters corresponding to the last stage of inverter of each clock path in the first simulation netlist to form a second simulation netlist after the time delay is added, wherein the time delay is obtained according to the ideal time delay of each inverter on each clock path and the fluctuation time delay of each inverter, the fluctuation time delay of each inverter is caused by on-chip fluctuation, and according to the second simulation netlist and the parasitic parameters of the interconnection line, the clock deviation of the clock system to be analyzed is determined, on one hand, the fluctuation time delay caused by on-chip fluctuation is considered when the performance of the clock system is analyzed, and the accuracy of the clock deviation analysis of the clock system is improved, on the other hand, the sum of the ideal time delay and the fluctuation time delay of all the inverters on the clock path is added to the parameters corresponding to the last-stage inverter of the first simulation netlist, the whole clock network does not need to be simulated, the simulation time is shortened, and the efficiency of the clock deviation analysis of the clock system is improved.
Fig. 4 is a schematic structural diagram of an embodiment of a clock system performance analysis apparatus according to an embodiment of the present invention. As shown in fig. 4, the clock system performance analysis apparatus provided in the embodiment of the present invention includes: a first obtaining module 41, an adding module 42 and a first determining module 43.
The first obtaining module 41 is configured to obtain parasitic parameters of an interconnection line of the clock system to be analyzed and a first simulated netlist.
Wherein the topology of the clock system is a mesh structure. The clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, and the clock grid is connected with a load. The first simulated netlist comprises the connection relation of inverters in a clock system.
Optionally, the first simulated netlist may further include a parasitic parametric model of transistors in each inverter and a load capacitance of the clock system.
Optionally, the first obtaining module 41 is specifically configured to: and acquiring parasitic parameters of the interconnection line through a parasitic parameter extraction tool, and acquiring a first simulation netlist through a circuit simulation tool. The parasitic parameter extraction tool may specifically be starRC and the circuit simulation tool may specifically be HSPICE.
And an adding module 42, configured to add a time delay to a parameter corresponding to a last-stage inverter of each clock path in the first simulated netlist, so as to form a second simulated netlist after the time delay is added.
The time delay is obtained according to the ideal time delay of the phase inverter on each clock path and the fluctuation time delay of the phase inverter, and the fluctuation time delay of the phase inverter is caused by on-chip fluctuation.
And a first determining module 43, configured to determine a clock bias of the clock system to be analyzed according to the second simulated netlist and the parasitic parameters of the interconnection lines.
Optionally, the first determining module 43 is specifically configured to: and determining a time delay sample of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection lines, and determining the statistic of the clock deviation of the clock system to be analyzed according to the time delay sample.
Further, the apparatus further comprises: and the second determining module is used for determining whether the design conservative quantity of the clock system to be analyzed is reasonable or not according to the statistic quantity of the clock deviation.
Further, the apparatus further comprises: and the second acquisition module is used for acquiring the fluctuation time delay of the inverter caused by the on-chip fluctuation in an experimental mode. Or, the third obtaining module is configured to obtain, through a probability density function, a fluctuation delay of each inverter caused by on-chip fluctuations, where the fluctuation delay of each inverter caused by the on-chip fluctuations follows a normal distribution.
The clock system performance analysis device provided by the embodiment of the invention is provided with a first acquisition module for acquiring parasitic parameters of interconnection lines of a clock system to be analyzed and a first simulation netlist, wherein the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of inverters, the last inverter of each clock path is connected with the clock grid, the clock grid is connected with a load, the first simulation netlist comprises the connection relation of the inverters in the clock system, an adding module for adding time delay in parameters corresponding to the last inverter of each clock path in the first simulation netlist to form a second simulation netlist after the time delay is added, wherein the time delay is obtained according to ideal time delay of the inverters on each clock path and fluctuation time delay of the inverters, the device comprises a first determining module, a second determining module and a third determining module, wherein the first determining module is used for determining the clock deviation of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line, on one hand, the clock deviation analyzing accuracy of the clock system is improved by considering the fluctuation time delay caused by on-chip fluctuation when the performance of the clock system is analyzed, on the other hand, the sum of ideal time delay and fluctuation time delay of all inverters on a clock path is added to the parameters corresponding to the last-stage inverter of the first simulation netlist, the whole clock network does not need to be simulated, the simulation time is shortened, and the clock deviation analyzing efficiency of the clock system is improved.
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. The program, when executed by a processor, implements the steps of the clock system performance analysis method provided in the embodiment shown in fig. 1.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (11)
1. A method for analyzing clock system performance, comprising:
acquiring parasitic parameters of an interconnection line of a clock system to be analyzed and a first simulation netlist; the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, the clock grid is connected with a load, and the first simulation netlist comprises the connection relation of the inverters in the clock system;
adding time delay to parameters corresponding to last-stage inverters of all clock paths in the first simulation netlist to form a second simulation netlist after the time delay is added; the time delay is obtained according to the ideal time delay of the phase inverter on each clock path and the fluctuation time delay of the phase inverter, and the fluctuation time delay of the phase inverter is caused by on-chip fluctuation;
and determining the clock deviation of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line.
2. The method of claim 1, wherein determining the clock bias of the clock system to be analyzed from the second simulated netlist and the parasitic parameters of the interconnect lines comprises:
determining a time delay sample of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line;
and determining the statistic of the clock deviation of the clock system to be analyzed according to the time delay sample.
3. The method of claim 2, wherein after determining statistics of clock skew of the clock system to be analyzed from the samples of time delays, the method further comprises:
and determining whether the design conservative quantity of the clock system to be analyzed is reasonable or not according to the statistic quantity of the clock deviation.
4. The method according to any one of claims 1 to 3,
before adding a delay to a parameter corresponding to a last-stage inverter of each clock path in the first simulated netlist and forming a second simulated netlist after adding the delay, the method further includes:
acquiring the fluctuation time delay of the inverter caused by the on-chip fluctuation in an experimental mode; or,
acquiring fluctuation time delay of each inverter caused by on-chip fluctuation through a probability density function; wherein the ripple time delay of each inverter caused by the on-chip ripple follows a normal distribution.
5. A method according to any of claims 1-3, wherein said obtaining parasitic parameters of the interconnect lines of the clock system to be analyzed and the first simulated netlist comprises:
acquiring parasitic parameters of the interconnection line through a parasitic parameter extraction tool;
and acquiring the first simulated netlist through a circuit simulation tool.
6. A clock system performance analysis apparatus, comprising:
the first acquisition module is used for acquiring parasitic parameters of an interconnection line of a clock system to be analyzed and a first simulation netlist; the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, the clock grid is connected with a load, and the first simulation netlist comprises the connection relation of the inverters in the clock system;
the adding module is used for adding time delay in parameters corresponding to last-stage inverters of all clock paths in the first simulation netlist to form a second simulation netlist after the time delay is added; the time delay is obtained according to the ideal time delay of the phase inverter on each clock path and the fluctuation time delay of the phase inverter, and the fluctuation time delay of the phase inverter is caused by on-chip fluctuation;
and the first determining module is used for determining the clock deviation of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line.
7. The apparatus of claim 6, wherein the first determining module is specifically configured to:
determining a time delay sample of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line;
and determining the statistic of the clock deviation of the clock system to be analyzed according to the time delay sample.
8. The apparatus of claim 7, further comprising:
and the second determining module is used for determining whether the design conservative quantity of the clock system to be analyzed is reasonable or not according to the statistic quantity of the clock deviation.
9. The apparatus according to any one of claims 6-8, further comprising:
the second acquisition module is used for acquiring the fluctuation time delay of the inverter caused by the on-chip fluctuation in an experimental mode; or,
the third acquisition module is used for acquiring fluctuation time delay of each inverter caused by on-chip fluctuation through a probability density function; wherein the ripple time delay of each inverter caused by the on-chip ripple follows a normal distribution.
10. The apparatus according to any one of claims 6 to 8, wherein the first obtaining module is specifically configured to:
acquiring parasitic parameters of the interconnection line through a parasitic parameter extraction tool;
and acquiring the first simulated netlist through a circuit simulation tool.
11. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method steps of any one of claims 1 to 5.
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