GB0510487D0 - Rotary clock design flow - Google Patents

Rotary clock design flow

Info

Publication number
GB0510487D0
GB0510487D0 GBGB0510487.2A GB0510487A GB0510487D0 GB 0510487 D0 GB0510487 D0 GB 0510487D0 GB 0510487 A GB0510487 A GB 0510487A GB 0510487 D0 GB0510487 D0 GB 0510487D0
Authority
GB
United Kingdom
Prior art keywords
design flow
clock design
rotary clock
rotary
flow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB0510487.2A
Other versions
GB2414094A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Multigig Ltd
Original Assignee
Multigig Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0203605A external-priority patent/GB0203605D0/en
Priority claimed from GB0212869A external-priority patent/GB0212869D0/en
Priority claimed from GB0214850A external-priority patent/GB0214850D0/en
Priority claimed from GB0218834A external-priority patent/GB0218834D0/en
Priority claimed from GB0225814A external-priority patent/GB0225814D0/en
Application filed by Multigig Ltd filed Critical Multigig Ltd
Priority claimed from GB0420141A external-priority patent/GB2403045B/en
Publication of GB0510487D0 publication Critical patent/GB0510487D0/en
Publication of GB2414094A publication Critical patent/GB2414094A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/396—Clock trees
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/18—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance
    • H03B5/1841—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator
    • H03B5/1847—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator the active element in the amplifier being a semiconductor device
    • H03B5/1852—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator the active element in the amplifier being a semiconductor device the semiconductor device being a field-effect device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits
    • H03K19/018571—Coupling arrangements; Impedance matching circuits of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
    • H04L25/085—Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/04—Clock gating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
GB0510487A 2002-02-15 2003-02-14 Designing Rotary Clock Integrated Circuits Withdrawn GB2414094A (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
GB0203605A GB0203605D0 (en) 2002-02-15 2002-02-15 Hierarchical clocking system
GB0212869A GB0212869D0 (en) 2002-06-06 2002-06-06 Timing circuit cad
GB0214850A GB0214850D0 (en) 2002-06-27 2002-06-27 Sgig
GB0218834A GB0218834D0 (en) 2002-08-14 2002-08-14 Fast synchronous interconnect improved RTWO 4 phase
GB0225814A GB0225814D0 (en) 2002-11-06 2002-11-06 High accuracy high power buffer
GB0420141A GB2403045B (en) 2002-02-15 2003-02-14 Clocking network

Publications (2)

Publication Number Publication Date
GB0510487D0 true GB0510487D0 (en) 2005-06-29
GB2414094A GB2414094A (en) 2005-11-16

Family

ID=35115759

Family Applications (3)

Application Number Title Priority Date Filing Date
GB0510487A Withdrawn GB2414094A (en) 2002-02-15 2003-02-14 Designing Rotary Clock Integrated Circuits
GB0510491A Expired - Lifetime GB2413870B (en) 2002-02-15 2003-02-14 Piped buffers
GB0510488A Expired - Lifetime GB2413869B (en) 2002-02-15 2003-02-14 Blip mode driver

Family Applications After (2)

Application Number Title Priority Date Filing Date
GB0510491A Expired - Lifetime GB2413870B (en) 2002-02-15 2003-02-14 Piped buffers
GB0510488A Expired - Lifetime GB2413869B (en) 2002-02-15 2003-02-14 Blip mode driver

Country Status (1)

Country Link
GB (3) GB2414094A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109388839A (en) * 2017-08-14 2019-02-26 龙芯中科技术有限公司 Clock system method for analyzing performance and device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102438864B1 (en) * 2018-09-28 2022-08-31 램 리써치 코포레이션 Methods and systems for optimizing power delivery to an electrode in a plasma chamber
CN111934684B (en) * 2020-07-31 2022-12-20 新华三半导体技术有限公司 Buffer, clock grid circuit and signal driving method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5884386A (en) * 1981-11-16 1983-05-20 ニツタン株式会社 Signal transmission system for fire alarm relay line
US5386585A (en) * 1993-02-03 1995-01-31 Intel Corporation Self-timed data pipeline apparatus using asynchronous stages having toggle flip-flops
US5758139A (en) * 1993-10-21 1998-05-26 Sun Microsystems, Inc. Control chains for controlling data flow in interlocked data path circuits
JP3283984B2 (en) * 1993-12-28 2002-05-20 株式会社東芝 Semiconductor integrated circuit device
JP3192086B2 (en) * 1996-04-25 2001-07-23 日本電気株式会社 Semiconductor integrated circuit
JPH10224270A (en) * 1997-02-03 1998-08-21 Mitsubishi Electric Corp Transmission reception system
US6163174A (en) * 1998-05-26 2000-12-19 The University Of Rochester Digital buffer circuits
JP2000307482A (en) * 1999-04-19 2000-11-02 Fujitsu Ltd Pulse transmitter for long distance transmission
EP1047149A3 (en) * 1999-04-21 2003-02-12 Matsushita Electric Industrial Co., Ltd. Signal transmitting/receiving apparatus
US20020158668A1 (en) * 2001-04-30 2002-10-31 Tschanz James W. CMOS bus pulsing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109388839A (en) * 2017-08-14 2019-02-26 龙芯中科技术有限公司 Clock system method for analyzing performance and device

Also Published As

Publication number Publication date
GB2414094A (en) 2005-11-16
GB2413869B (en) 2006-09-27
GB0510488D0 (en) 2005-06-29
GB2413870A (en) 2005-11-09
GB0510491D0 (en) 2005-06-29
GB2413869A (en) 2005-11-09
GB2413870B (en) 2006-03-22

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)