CN101635844A - Image data transmission method and device - Google Patents
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- CN101635844A CN101635844A CN200810134469A CN200810134469A CN101635844A CN 101635844 A CN101635844 A CN 101635844A CN 200810134469 A CN200810134469 A CN 200810134469A CN 200810134469 A CN200810134469 A CN 200810134469A CN 101635844 A CN101635844 A CN 101635844A
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Abstract
The invention discloses an image data transmission method and an image data transmission device. A micro-frame header is added to received image data meeting a USB Video Class (UVC) protocol under the control of a first-in first-out memory (FIFO) so as to form an image data stream (Usb_Video_Class data stream) meeting the UVC protocol; and the Usb_Video_Class data stream passes through the FIFO and then is read by a USB controller (Usb core), so the no-drive transmission of the Usb_Video_Class data stream is realized.
Description
Technical field
The present invention relates to not have and drive the video equipment technology, refer to the image data transfer method and the device of a kind of USB of meeting video class (UVC, USBVideo Class) agreement especially.
Background technology
USB (USB, Universal Serial Bus) in the agreement, except general software and hardware electric interfaces standard etc., also comprised various classes (Class) agreement, be used for being different functional definitions standard interface separately, and the data interaction format and content on the concrete bus.The quantity of these Class agreements is very many, modal such as USB memory device class (USB Mass StorageDevice) agreement, USB alternating interface between man and computer (USB Human Interface Device) agreement, USB audio class (UAC, USB Audio CLASS) agreement, UVC agreement or the like.Wherein, support the video equipment series products of UVC agreement to comprise not having and drive camera.
It is that example describes that this paper drives camera with nothing.And the view data that claims to meet the UVC agreement is the Usb_Video_Class data flow.
According to the UVC agreement, the Usb_Video_Class data flow adopts (isochronous) transmission means synchronously.Fig. 1 is the form schematic diagram of the Usb_Video_Class data flow stipulated in the UVC agreement, as shown in Figure 1, the form of regulation Usb_Video_Class data flow is in the UVC agreement: little frame head (payload header) adds view data (payload data), wherein, payload header width in the UVC agreement is defined as 16bit, is used for the package image data.When selected high speed high bandwidth mode transmission mode, in the little frame of USB a little frame head is arranged, and i.e. three the payload data of three packets of a little frame head band, wherein each packet is 1024 bytes to the maximum.
For the nothing that realizes the Usb_Video_Class data flow is driven transmission, need add little frame head to form the Usb_Video_Class data flow to view data.At present, there is not relevant programme about how adding little frame head.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of image data transfer method, can realize that the nothing of Usb_Video_Class data flow is driven transmission.
Another object of the present invention is to provide a kind of image data transmission device, can realize that the nothing of Usb_Video_Class data flow is driven transmission.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of image data transfer method, this method comprises:
Obtain view data, under the control of push-up storage FIFO, the view data that receives is added little frame head, meet the view data Usb_Video_Class data flow of USB video class UVC agreement with formation, the USB controller reads the Usb_Video_Class data flow from FIFO.
Described under the control of push-up storage FIFO, the view data that receives is added little frame head specifically comprise:
When the empty Empty signal that detects described FIFO is effective, the view data of described acquisition is added little frame head;
When detecting continuous 3070 byte image data, the view data of described acquisition is added little frame head;
When the view data of judging described acquisition is new image frame, the view data that obtains is added little frame head.
Described judging whether to the method for new image frame is: when the frame synchronization Vsync of described FIFO signal is effective, represent the beginning of a width of cloth new images, when the synchronous Hsync signal identification of the row of described FIFO last column was effective, the expression piece image closed to an end.
The described empty Empty signal that detects FIFO effectively before, this method also comprises:
When the fast empty AlomstEmpty signal that detects described FIFO is effective, the view data of the described acquisition of buffer memory.
When the full Full signal that detects described FIFO is effective, will identifies vicious little frame head and write described FIFO, and no longer write view data in current this picture frame.
This method also comprises: during last little frame head in detecting the piece image frame, add last little frame head again behind frame synchronization Vsync invalidating signal.
A kind of image data transmission device, this image data transmission device comprises: image data acquisition module, image data processing module and FIFO, wherein,
The image data acquisition module is used to obtain view data, and sends to image data processing module;
Image data processing module is used under the control of FIFO the view data that receives being added little frame head, with formation Usb_Video_Class data flow, and sends to FIFO;
FIFO is used for transmitting control signal to image data processing module, and the Usb_Video_Class data flow that receives is read by the USB controller.
Described image data acquisition module is lighting apparatus Sensor.
The signal that described Sensor sends to image data processing module has: the clock signal Pclk as the work clock of image data processing module of Sensor output, be used to represent frame synchronization Vsync signal that whether a width of cloth new images begin, be used to represent the synchronous Hsync signal of row, 8 bit image data-signal Data[7:0 that whether last column of piece image begins];
The signal that described image data processing module sends to FIFO has: be used for sign and be added with byte enable Byten[3:0] Usb_Video_Class data flow DA[35:0] whether write writing of FIFO and enable Wren, be added with byte enable Byten[3:0] and Usb_Video_Class data flow DA[35:0]; Wherein byte enable to be used for identifying the data that added little frame head be Usb_Video_Class data flow Data[31:0] which byte is effective;
The signal that described FIFO sends to image data processing module is free Empty signal, and when empty Empty signal was effective, described image data processing module added little frame head to the view data that obtains.
The signal that described FIFO sends to image data processing module also has fast empty AlmostEmpty signal, when fast empty AlomstEmpty signal is effective, and the view data of the described acquisition of described image data processing module buffer memory.
The signal that described FIFO sends to image data processing module also has the Full signal of expiring, and when full Full signal is effective, described image data processing module will identify vicious little frame head and write described FIFO, and no longer write view data in current this picture frame.
Behind described frame synchronization Vsync invalidating signal, after finishing, view data adds little frame head.
Described image data processing module is made up of selector and buffer Buf.
As seen from the above technical solution, the present invention is by the control of FIFO, the view data that receives is added little frame head, to form the Usb_Video_Class data flow, then the Usb_Video_Class data flow is read by USB controller (Usb core) behind FIFO, thereby the nothing that has realized the Usb_Video_Class data flow is driven transmission.
Description of drawings
Fig. 1 is the form schematic diagram of the Usb_Video_Class data flow stipulated in the UVC agreement;
Fig. 2 is the composition structural representation of image data transmission device embodiment of the present invention;
Fig. 3 is the principle schematic of image data processing module among the image data transmission device embodiment of the present invention.
Embodiment
Fig. 2 is the composition structural representation of image data transmission device embodiment of the present invention, as shown in Figure 2, comprising: image data acquisition module, image data processing module and push-up storage (FIFO).
The image data acquisition module is used to obtain view data, and sends to image data processing module.Drive camera for nothing, the image data acquisition module is lighting apparatus (Sensor).
Image data processing module is used under the control of FIFO the view data that receives being added little frame head, with formation Usb_Video_Class data flow, and sends to FIFO.
FIFO is used for transmitting control signal to image data processing module, and the Usb_Video_Class data flow that receives is read by USB controller (Usb core).
One skilled in the art will appreciate that last view data after Usb core packing, (Phy) issues main frame via physical layer.
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
If the image data acquisition module is lighting apparatus Sensor, the signal that Sensor sends to image data processing module has: the clock signal (Pclk) as the work clock of image data processing module of Sensor output, be used to represent frame synchronizing signal (Vsync) that whether a width of cloth new images begin, be used to represent line synchronizing signal (Hsync) that whether last column of piece image begin, 8 bit image data-signals (Data[7:0]);
The signal that image data processing module sends to FIFO has: the Usb_Video_Class data flow DA[35:0 that writes and enable (Wren), is added with byte enable (Byten[3:0])], wherein the Usb_Video_Class data flow is 32bit (Data[31:0]), and byte enable is 4bit (Byten[3:0]) and is positioned at DA[35:0] high 4 be DA[35:32]=Byten[3:0].
Wherein, Wren is the inner signal that produces of image data processing module, in image data processing module, 36bits data DA[35:0 after the data that are used to identify the view data that added little frame head and byte enable merge]=Byten[3:0], DATA[31:0] } whether write FIFO, when Wren is effective, with DA[35:0] write FIFO.
Byte enable (Byten[3:0]): Byten[3:0] to be used for identifying the data that added little frame head be which byte of Usb_Video_Class data flow (Data[31:0]) is effective.Byten[3:0 for example]=4 ' b0011, expression DATA[31:0] in DATA[15:0] effectively; In addition, receive Byten[3:0 at main frame]=4 ' b0011 is DA[35:32]=during 4 ' b0011, main frame is no longer request in current little frame, and this little frame is empty frame (has only little frame head, do not have pictorial data).
The Usb_Video_Class data flow (Data[31:0]): Data[31:0] for having added the wide Usb_Video_Class data flow of 32bit of payload header.
The signal that FIFO sends to image data processing module has: empty (Empty) signal.Detect the Empty signal when effective in image data processing module, image data processing module adds payload header to view data.Further, the FIFO signal that sends to image data processing module can also have: fast empty (AlmostEmpty) signal.Detect the AlmostEmpty signal when effective in image data processing module, image data processing module is carried out caching to view data.Further, the FIFO signal that sends to image data processing module can also have: FIFO full (Full) signal.Detect the Full signal when effective in image data processing module, will identify vicious payload header and write FIFO, no longer write view data in this picture frame.
Need to prove, in the device shown in Figure 2, the signal that relates to each module has only illustrated signal related to the present invention, it is not shown in Figure 2 that other signal such as controller such as single-chip microcomputer send to (RST_n) signal that resets that its work of control of image data processing module enables, register controlled signal (Register control signal) etc., use for these signals, be those skilled in the art's conventional techniques means, no longer describe in detail here.
The operation principle of apparatus of the present invention embodiment shown in Figure 2 is:
The value that Vsync signal that the image data processing module basis receives and Hsync signal are determined payloadheader.Such as: when Vsync signal during effectively as by low uprising, represent the beginning of a width of cloth new images, the value of supposing little frame head is 0x0280, and when Hsync signal identification last column was effective, the expression piece image closed to an end, and the value of little frame head is 0x0282; Become again when effective from invalid at the Vsync signal, represent the beginning of another width of cloth new images, this moment, the value upset of little frame head was 0x0281, when Hsync signal identification last column is effective, represented that this width of cloth image closes to an end, and the value of little frame head is 0x0283.The value of above-mentioned definite payload header is a kind of method, also has other a lot of methods, is to realize easily for those skilled in the art, just illustrates here, and is not used in qualification the present invention.In the value of little frame head, 0x represents hexadecimal; 0x02 represents the size of little frame head, and unit is a byte.The highest significant position of low byte is 1, and expression payload header has only a byte header field (BFH, bits field head); The least significant bit correspondence image frame identification of low byte, for new image frame, this bit flipping; Last little frame in the inferior low order sign piece image frame of low byte, time low order set when little frame is last little frame of picture frame.
From definite method of the value of payload header as can be seen, in same width of cloth image, before last column, add payload header if desired, the value when its value has just begun with image is consistent.
Apparatus of the present invention need add payload header to view data in following three kinds of situations:
(1) detect the Empty signal when effective in image data processing module, image data processing module adds payload header to view data.Here the Empty signal is meant that effectively the write pointer of FIFO changes read pointer and catch up with the situation that write pointer or the motionless read pointer of write pointer catch up with write pointer;
(2) because i.e. three the payload data of three packets of a little frame head band, wherein each packet is 1024 bytes to the maximum, therefore, need add little frame head when continuous 3070 byte image data.When counter was counted 3070 bytes to pictorial data, image data processing module can produce one and write 3070 byte signals continuously, and when producing this and write 3070 byte signals continuously, view data was added payload header.
(3) clearly, begin to add little frame head in new image frame.Image data processing module when judging to new images, adds payloadheader to view data according to the Vsync signal and the Hsync signal that receive.
Further, because FIFO is from reading and writing as asynchronous clock, wherein, read the work clock that clock is USB core, write the work clock that clock is an image data processing module, therefore, when image data processing module detects the spacing wave Empty signal of FIFO when effective, may also have view data among the FIFO.Among the FIFO, the AlmostEmpty signal occurred before the Empty signal, in order to guarantee that FIFO is when the Empty signal occurs, there is not view data among the FIFO, when image data processing module detects the AlmostEmpty signal when effective, earlier view data is deposited in the buffer memory (buffer), the Empty signal that measures to be checked is when effective, and the data that will add payload header again send to FIFO.Buffer memory can adopt 8x8bit, or the buffer memory of 16 x8bit etc., as long as satisfy when the Empty signal is effective, gets final product for vacuum among the FIFO.
In addition, when last little frame appears in very difficult judgement, and the UVC agreement is not clearly stipulated yet, therefore, among the present invention, for last the little frame head in the piece image frame, after view data finishes, add, promptly after the Vsync step-down is invalid, add last little frame head again.
Further, detect the Full signal when effective, illustrate that vicious payload header writes FIFO, no longer writes view data in this picture frame in image data processing module.
Fig. 3 is the principle schematic of image data processing module among the image data transmission device embodiment of the present invention, and as shown in Figure 3, image data processing module can be by selector and the simple signal of buffer (Buf).
Wherein, suppose that Buf2 is the buffer of 32bit, Buf3 is the 16bit buffer, and Buf4 is the 32bit buffer; Selector 2, selector 3 and selector 4 are the alternative selector, and selector 1 is five to select a selector.Need to prove that at this moment, 2 pairs of input informations of selector are in direct mode operation.
The view data wide from the 8bit of Sensor enters Buf2 behind selector 2, be superimposed as the wide view data of 32bit; Selector 1 is selected little frame head under the control of Vsync signal, Hsync signal and Empty signal, and becomes the wide little frame head of 16bit behind Buf3;
The wide little frame head of view data that 32bit is wide and 16bit enters selector 3, effective at Empty signal from FIFO, perhaps write 3070 byte signals continuously when effective, selector 3 selects little frame head to export to Buf4, under other situation, select view data to export to Buf4.
In Buf4, the wide little frame head of view data that 32bit is wide and 16bit is superimposed as the wide Usb_Video_Class data flow of 32bit, and sends FIFO to by selector 4.Under the normal condition, be invalid during from the Full signal of FIFO, selector 4 is selected to export to FIFO from the data of Buf4; Only occurring unusual as designing and stagger the time, the Full signal is effective, at this moment, under the control of Full signal, selector 1 selects the vicious 0x02c0 of sign of output to give Buf3, and selector 4 selects have little frame head of mistake to export to FIFO from the sign of Buf3, and no longer writes view data in this picture frame.
Further, image data processing module can also comprise Buf1, be used for the view data from Sensor is carried out buffer memory, and from the AlomstEmpty signal of FIFO when effective, selector 2 is selected the view data of output from Buf2.Buf2 can be the buffer of 8 * 8bit, perhaps the buffer of 16 * 8bit.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. an image data transfer method is characterized in that, this method comprises:
Obtain view data, under the control of push-up storage FIFO, the view data that receives is added little frame head, meet the view data Usb_Video_Class data flow of USB video class UVC agreement with formation, the USB controller reads the Usb_Video_Class data flow from FIFO.
2. image data transfer method according to claim 1 is characterized in that, and is described under the control of push-up storage FIFO, the view data that receives added little frame head specifically comprise:
When the empty Empty signal that detects described FIFO is effective, the view data of described acquisition is added little frame head;
When detecting continuous 3070 byte image data, the view data of described acquisition is added little frame head;
When the view data of judging described acquisition is new image frame, the view data that obtains is added little frame head.
3. image data transfer method according to claim 2, it is characterized in that, described judging whether to the method for new image frame is: when the frame synchronization Vsync of described FIFO signal is effective, represent the beginning of a width of cloth new images, when the synchronous Hsync signal identification of the row of described FIFO last column was effective, the expression piece image closed to an end.
4. image data transfer method according to claim 2 is characterized in that, the described empty Empty signal that detects FIFO effectively before, this method also comprises:
When the fast empty AlomstEmpty signal that detects described FIFO is effective, the view data of the described acquisition of buffer memory.
5. according to claim 2 or 4 described image data transfer methods, it is characterized in that, when the full Full signal that detects described FIFO is effective, will identifies vicious little frame head and write described FIFO, and no longer write view data in current this picture frame.
6. image data transfer method according to claim 5 is characterized in that, this method also comprises: during last little frame head in detecting the piece image frame, add last little frame head again behind frame synchronization Vsync invalidating signal.
7. an image data transmission device is characterized in that, this image data transmission device comprises: image data acquisition module, image data processing module and FIFO, wherein,
The image data acquisition module is used to obtain view data, and sends to image data processing module;
Image data processing module is used under the control of FIFO the view data that receives being added little frame head, with formation Usb_Video_Class data flow, and sends to FIFO;
FIFO is used for transmitting control signal to image data processing module, and the Usb_Video_Class data flow that receives is read by the USB controller.
8. image data transmission device according to claim 7 is characterized in that, described image data acquisition module is lighting apparatus Sensor.
9. image data transmission device according to claim 8 is characterized in that,
The signal that described Sensor sends to image data processing module has: the clock signal Pclk as the work clock of image data processing module of Sensor output, be used to represent frame synchronization Vsync signal that whether a width of cloth new images begin, be used to represent the synchronous Hsync signal of row, 8 bit image data-signal Data[7:0 that whether last column of piece image begins];
The signal that described image data processing module sends to FIFO has: be used for sign and be added with byte enable Byten[3:0] Usb_Video_Class data flow DA[35:0] whether write writing of FIFO and enable Wren, be added with byte enable Byten[3:0] and Usb_Video_Class data flow DA[35:0]; Wherein byte enable to be used for identifying the data that added little frame head be Usb_Video_Class data flow Data[31:0] which byte is effective;
The signal that described FIFO sends to image data processing module is free Empty signal, and when empty Empty signal was effective, described image data processing module added little frame head to the view data that obtains.
10. image data transmission device according to claim 9, it is characterized in that, the signal that described FIFO sends to image data processing module also has fast empty AlmostEmpty signal, when fast empty AlomstEmpty signal is effective, the view data of the described acquisition of described image data processing module buffer memory.
11. image data processing system according to claim 10, it is characterized in that, the signal that described FIFO sends to image data processing module also has the Full signal of expiring, when full Full signal is effective, described image data processing module will identify vicious little frame head and write described FIFO, and no longer write view data in current this picture frame.
12. image data transmission device according to claim 9 is characterized in that, behind described frame synchronization Vsync invalidating signal, adds little frame head after view data finishes.
13. image data transmission device according to claim 8 is characterized in that, described image data processing module is made up of selector and buffer Buf.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102749855A (en) * | 2011-04-20 | 2012-10-24 | 南京普爱射线影像设备有限公司 | Image data transmission controller for gigabit network interface |
| CN107666582A (en) * | 2016-07-27 | 2018-02-06 | 华平信息技术股份有限公司 | Video signal conversion method and system |
| CN109040786A (en) * | 2018-09-03 | 2018-12-18 | 锐捷网络股份有限公司 | Transmission method, device, system and the storage medium of camera data |
| WO2020259457A1 (en) * | 2019-06-25 | 2020-12-30 | 华为技术有限公司 | Control method based on vertical synchronizing signal, and electronic device |
Family Cites Families (4)
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| KR100734351B1 (en) * | 2001-04-20 | 2007-07-03 | 엘지전자 주식회사 | Digital broadcasting transmit system |
| CN1223161C (en) * | 2002-07-29 | 2005-10-12 | 华为技术有限公司 | Byte transparent processing method to data flow |
| JP4789753B2 (en) * | 2006-08-28 | 2011-10-12 | 富士通セミコンダクター株式会社 | Image data buffer device, image transfer processing system, and image data buffer method |
| CN101184244A (en) * | 2007-12-25 | 2008-05-21 | 北京数码视讯科技股份有限公司 | Video coding method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102749855A (en) * | 2011-04-20 | 2012-10-24 | 南京普爱射线影像设备有限公司 | Image data transmission controller for gigabit network interface |
| CN102749855B (en) * | 2011-04-20 | 2014-05-07 | 南京普爱射线影像设备有限公司 | Image data transmission controller for gigabit network interface |
| CN107666582A (en) * | 2016-07-27 | 2018-02-06 | 华平信息技术股份有限公司 | Video signal conversion method and system |
| CN107666582B (en) * | 2016-07-27 | 2020-04-24 | 华平信息技术股份有限公司 | Video signal conversion method, system, device and video processing device |
| CN109040786A (en) * | 2018-09-03 | 2018-12-18 | 锐捷网络股份有限公司 | Transmission method, device, system and the storage medium of camera data |
| WO2020259457A1 (en) * | 2019-06-25 | 2020-12-30 | 华为技术有限公司 | Control method based on vertical synchronizing signal, and electronic device |
| US11847992B2 (en) | 2019-06-25 | 2023-12-19 | Huawei Device Co., Ltd. | Control method based on vertical synchronization signal and electronic device |
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