CN101630957A - Dual-mode prescaler with adaptive dormancy - Google Patents
Dual-mode prescaler with adaptive dormancy Download PDFInfo
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Abstract
The invention discloses a dual-mode prescaler with self-adaptive dormancy, which consists of a plurality of high-speed logic units, a logic control circuit and a plurality of MOS tubes serving as current sources, wherein each high-speed logic unit is provided with a clock trigger end, a signal input end and a signal output end, the clock trigger end of each high-speed logic unit is connected with an external clock signal CLK, the signal input end of each high-speed logic unit is connected with the output end of the logic control circuit, and the input end of the logic control circuit is connected with the signal output end of each high-speed logic unit and an external mode control signal. According to the dual-mode prescaler with the self-adaptive dormancy, one high-speed trigger is in a dormant state through the turn-off of the MOS tube serving as the current source according to the specific numerical value of the frequency division value and the mode control signal, so that electric energy is not consumed, unnecessary power consumption waste is avoided, and the purpose of reducing power consumption is achieved.
Description
Technical field
The present invention relates to electronic technology field, relate in particular to a kind of dual-modulus prescaler, can be applicable in the frequency synthesizer of phase locking in the radio frequency transceiver with self-adapting dormancy.
Background technology
Important function such as frequency synthesizer of phase locking plays in communication system synchronously, frequency conversion and channel switching are one of indispensable parts of modern communication.As shown in Figure 1, this frequency synthesizer of phase locking is made of phase frequency detector and charge pump (PFD/CP), loop filter (LPF), voltage controlled oscillator (VCO) and frequency divider.
Wherein, phase frequency detector and charge pump are phase comparison devices, are used for the phase place of the output signal of input reference signal and voltage controlled oscillator is compared, and produce the error voltage corresponding to two signal phase differences.The effect of loop filter is radio-frequency component and the noise in the filtering error voltage, to guarantee the desired performance of loop, increases the stability of system.The control of the controlled voltage of voltage controlled oscillator makes the frequency of voltage controlled oscillator draw close to the frequency of input signal, locks until eliminating frequency difference.Frequency divider is used for the frequency of the high-frequency signal of VCO output is removed in N, to reach purpose identical with reference frequency when locking.
The frequency divider of frequency synthesizer must provide a frequency dividing ratio M that can programme, and under low frequency, it can be realized with a programmable high-speed counter.But when the output frequency of frequency synthesizer was very high, high-speed counter was to be difficult to realize, and can power consumption very big.The frequency divider of big power consumption makes the stand-by time of communication system shorten.
In order to address this problem, the common employing bimodulus of people frequency splitting technology now, as shown in Figure 2.It is by a dual-modulus prescaler and two counters (count value is respectively P and S and P＜S, and they all can be programmed) composition.Dual-modulus prescaler carries out frequency division to the output signal of VCO, and its frequency dividing ratio can be selected between N or N+1.During beginning, dual-modulus prescaler carries out the N+1 frequency division to the VCO output signal, S and P counter all count to the output pulse of dual-modulus prescaler, when a predetermined S value reaches, it changes the frequency dividing ratio of dual-modulus prescaler into N, after this, the S counter stops counting, and the P counter continues the output pulse of dual-modulus prescaler is counted, after its counter value reaches a certain predetermined P value, it is with itself and S counter reset, and the frequency dividing ratio with dual-modulus prescaler reverts to N+1 again simultaneously.Whole process begins again.The frequency dividing ratio of the module of being made up of P counter, S counter and dual-modulus prescaler is: M=(N+1) S+N (P-S)=PN+S changes frequency dividing ratio by changing S.When frequency process dual-modulus prescaler frequency division, after frequency greatly reduced, the design of follow-up sub-frequency divider just was reduced to the programmable counter of design, had reduced the power consumption of whole system.
The dual-modulus prescaler power consumed accounts for more than 40% of frequency synthesizer total power consumption in the frequency divider of said structure, becomes one of part that frequency synthesis consumes energy most.The structure of dual-modulus prescaler is a lot, has 2/3,4/5,8/9 frequency division etc. multiple.Fig. 3 is 2/3 dual-modulus prescaler building-block of logic, and Fig. 4 is 4/5 dual-modulus prescaler building-block of logic.
In Fig. 3, when the control level of MC when low, 2/3 dual-modulus prescaler is in 3 patterns of removing, and at this moment, needs high speed logic unit 1 (being nominally DFF1 in Fig. 3) and high speed logic unit 2 (being nominally DFF2 in Fig. 3) two triggers to finish the division function of 3 patterns of removing jointly.When the control level of MC when being high, 2/3 dual-modulus prescaler is in 2 patterns of removing, and at this moment, needs trigger of DFF2 just can finish division function except that 2 patterns.
In Fig. 4, when the control level of MC when low, 4/5 dual-modulus prescaler is in 4 patterns of removing, at this moment, frequency division mainly is to be finished jointly by high speed logic unit 1 (being nominally DFF1 in Fig. 4) and high speed logic unit 2 (being nominally DFF2 in Fig. 4) two triggers, and high speed logic unit 3 (being nominally DFF3 in Fig. 4) only provides a high level for first NAND gate (401).When the control level of MC when being high, 4/5 dual-modulus prescaler is in 5 patterns of removing, and at this moment, needs DFF1, DFF2 and DFF3 trigger just can finish division function except that 5 patterns.
From top frequency division pattern narration, recognize that when 2/3 dual-modulus prescaler was in 2 patterns of removing, first trigger DFF1 did not have contribution to frequency division; When 4/5 dual-modulus prescaler was in 4 patterns of removing, the 3rd trigger DFF3 do not have contribution to frequency division.
In fact, be not only 2/3,4/5 dual-modulus prescaler exists does not have contribution to frequency division high speed logic unit, other is the N/N+1 dual-modulus prescaler arbitrarily, all has a high speed logic unit that frequency division is not had contribution when being in except that the N pattern.The high speed logic unit of this nothing contribution is still movable, causes unnecessary power wastage, is a big shortcoming of present dual-modulus prescaler.
Summary of the invention
(1) technical problem that will solve
At the shortcoming with above-mentioned N/N+1 dual-modulus prescaler, main purpose of the present invention is to provide a kind of dual-modulus prescaler with self-adapting dormancy, to avoid unnecessary power wastage, reaches the purpose that reduces power consumption.
(2) technical scheme
For achieving the above object, the invention provides a kind of dual-modulus prescaler with self-adapting dormancy, this dual-modulus prescaler is by a plurality of high speed logics unit, one logic control circuit and a plurality of metal-oxide-semiconductor formation as current source, the high speed logic unit has a clock trigger end, one signal input part and a signal output part, the clock of high speed logic unit triggers the external clock signal clk of termination, the signal input part of high speed logic unit connects the output of logic control circuit, the signal output part and the foreign mode control signal of the input termination high speed logic unit of logic control circuit.
In the such scheme, the mode control signal that the input of described logic control circuit receives determines the frequency division value of this dual-modulus prescaler, output at this dual-modulus prescaler can produce one by the signal of frequency division, concrete numerical value and mode control signal according to frequency division value, one of them high speed flip flop is in resting state by the shutoff as the metal-oxide-semiconductor of current source, not consumed power.
In the such scheme, described high speed logic unit is latch or trigger.
In the such scheme, described trigger is real single phase clock TSPC element circuit.
In the such scheme, described latch is a standard cell logic SCL element circuit.
In the such scheme, described metal-oxide-semiconductor as current source is a N type metal-oxide-semiconductor, or P type metal-oxide-semiconductor.
In the such scheme, described metal-oxide-semiconductor open or disconnected state is determined by mode control signal.
(3) beneficial effect
This dual-modulus prescaler provided by the invention with self-adapting dormancy, determine the frequency division value of this dual-modulus prescaler by mode control signal, output at this dual-modulus prescaler can produce one by the signal of frequency division, concrete numerical value and mode control signal according to frequency division value, one of them high speed flip flop is in resting state by the shutoff as the metal-oxide-semiconductor of current source, consumed power has not been avoided unnecessary power wastage, has reached the purpose that reduces power consumption.
Description of drawings
The explanation that relevant the present invention is more complete, and wherein other purpose and advantage, please in conjunction with the accompanying drawings with reference to following description, in the accompanying drawings:
Fig. 1 is the frequency synthesizer of phase locking structural representation;
Fig. 2 is the structural representation of integer frequency divider, has shown the position of dual-modulus prescaler;
Fig. 3 is 2/3 a traditional dual-modulus prescaler;
Fig. 4 is 4/5 a traditional dual-modulus prescaler;
Fig. 5 is 2/3 dual-modulus prescaler with self-adapting dormancy function;
Fig. 6 is 4/5 dual-modulus prescaler with self-adapting dormancy function;
Fig. 7 is the building-block of logic with dual-modulus prescaler of self-adapting dormancy;
Fig. 8 is the circuit diagram of SCL structure trigger.
Symbol description:
In Fig. 6:
601: be NAND gate
602: be NAND gate
631: be inverter
641: for or the door
611: be first trigger
612: be second trigger
613: be the 3rd trigger
621: be first NMOS pipe as current source
622: be second NMOS pipe as current source
623: be the 3rd NMOS pipe as current source
651: be first trigger input end of clock mouth
652: be second trigger input end of clock mouth
653: be the 3rd trigger input end of clock mouth
6111: be the source electrode of first trigger CLK pipe
6121: the source electrode that is second trigger CLK pipe
6131: the source electrode that is the 3rd trigger CLK pipe
MC: be mode control signal
OUT: be output port
1: the input of NAND gate (601)
2: the input of NAND gate (601)
3: the input of NAND gate (602)
4: the input of NAND gate (602)
5: or the input of door (641)
6: or the input of door (641)
Q1: be 611 logic positive output port
Q2: be 612 logic positive output port
Q3: be 613 logic positive output port
Q1: be 611 logic negative output port
Q2: be 612 logic negative output port
Q3: be 613 logic negative output port
In Fig. 8:
S: be the source electrode of CLK pipe
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
This dual-modulus prescaler provided by the invention with self-adapting dormancy, constitute by a plurality of high speed logics unit, a logic control circuit and a plurality of metal-oxide-semiconductor as current source, the high speed logic unit has a clock trigger end, a signal input part and a signal output part, the clock of high speed logic unit triggers the external clock signal clk of termination, the signal input part of high speed logic unit connects the output of logic control circuit, the signal output part and the foreign mode control signal of the input termination high speed logic unit of logic control circuit.The mode control signal that the input of described logic control circuit receives determines the frequency division value of this dual-modulus prescaler, output at this dual-modulus prescaler can produce one by the signal of frequency division, concrete numerical value and mode control signal according to frequency division value, one of them high speed flip flop is in resting state by the shutoff as the metal-oxide-semiconductor of current source, not consumed power.
This dual-modulus prescaler is used for the high-frequency signal of outside input is carried out frequency division, under the effect under the mode control signal, can obtain removing N or two kinds of fractional frequency signals of N+1.The high speed flip flop or the latch of dual-modulus prescaler have tail current.This dual-modulus prescaler is when being in except that the N pattern, and the tail current of its one or more triggers or latch can turn-off, and the signal that control is turn-offed is a mode control signal, and this makes the power consumption of pre-divider greatly also reduce when removing the N pattern.
Specifically, the dual-modulus prescaler of this self-adapting dormancy provided by the invention, its input connects radiofrequency signal usually, such as: in frequency synthesizer of phase locking, the input of this dual-modulus prescaler is connected to the output of voltage controlled oscillator.This dual-modulus prescaler is under the effect of pattern control end signal, and frequency dividing ratio can be N/N+ 1, and wherein N is a natural number.The trigger of dual-modulus prescaler is made of real single phase clock (TSPC) element circuit usually, and the latch of dual-modulus prescaler is made of standard cell logical circuit (SCL) usually.When dual-modulus prescaler was in except that the N pattern, its one or more triggers were in resting state, not consumed power.
Fig. 5 is the 2/3 dual-modulus prescaler logical circuitry with self-adapting dormancy that is proposed, and Fig. 6 is the 4/5 dual-modulus prescaler logical circuitry that adapts to dormancy that has that is proposed.In Fig. 5, when the control level of MC when being high, the output level of inverter 1 is low, and the tail current of high speed logic unit 1 (being nominally DFF1 in Fig. 5) is closed, and it is consumed power no longer; Dual-modulus prescaler removes 2 functions and is finished alone by high speed logic unit 21 (being nominally DFF2 in Fig. 5); When the control level of MC when being high, the output level of inverter 1 is high, and the tail current of DFF1 is opened, this moment dual-modulus prescaler remove 3 functions with traditional the same as shown in Figure 3, finish jointly by DFF1 and DFF2.In Fig. 6, when the control level of MC when low, the tail current of high speed logic unit 3 (being nominally DFF3 in Fig. 6) is closed, it is consumed power no longer; Dual-modulus prescaler removes 4 functions and is finished alone by high speed logic unit 1 (being nominally DFF1 in Fig. 6) and high speed logic unit 2 (being nominally DFF2 in Fig. 6), the needed high level of NAND gate (601) input by mode control signal through an inverter (603) and or (604) obtain afterwards; When the control level of MC when being high, the tail current of DFF3 is opened, this moment dual-modulus prescaler remove 5 functions with traditional the same as shown in Figure 4, finish jointly by DFF1, DFF2 and DFF3.
Fig. 5, Fig. 6 are the logical circuitrys of concrete a certain self-adapting dormancy dual-modulus prescaler.In addition, also exist 3/4,8/9 or the like multiple dual-modulus prescaler structure.In order to be without loss of generality, now ascribe these logical constructions to Fig. 7 with dual-modulus prescaler of self-adapting dormancy function.Dual-mode frequency divider is made up of N high speed flip flop (also can be latch), a N NMOS pipe and a logic control circuit, and wherein N is the integer more than or equal to 2.Among Fig. 7, M, S are the integer more than or equal to 0, and its concrete numerical value can't be certain, because will recently determine according to the frequency division of concrete dual-modulus prescaler, such as: in 2/3 frequency division, M, S are 0, in 4/5 frequency division, M=1, S=0, in 8/9 frequency division, M=2, S=1 is in 16/17 frequency division, M=3, S=2.
The clock of high speed flip flop triggers the external clock signal clk of termination, and the signal input part of high speed flip flop connects the output of logic control circuit, and the signal output part of high speed flip flop connects the input of logic control circuit.The input termination foreign mode control signal of logic control circuit.The pattern incoming end marks in Fig. 7, on the next door of mode control signal one arrow is arranged, and represents this input port.The last output port of this dual-modulus prescaler is the output port of N-M high speed flip flop.Prolong (or decline is prolonged) when the rising of CLK signal and come temporarily, except that the N-S high speed flip flop, the output state of other high speed flip flops changes, and becomes consistent with its input state.Mode control signal is determining the N-S high speed flip flop to be in work or resting state.When the N-S high speed flip flop is in work, the same with other trigger, prolong (or decline is prolonged) when the rising of CLK signal and come to become consistent temporarily with its input state; When the N-S high speed flip flop was in resting state, its state was constant, to the not contribution of frequency division of whole dual-modulus prescaler.
The trigger of forming dual-modulus prescaler all must operate at fast state, is dissipative cell.When dual-modulus prescaler was in except that the N pattern, one of them trigger was in resting state to the beneficial effect of foregoing invention exactly, consumed power not, thus saved power consumption.
For being without loss of generality, be example with as shown in Figure 6 4/5 dual-modulus prescaler below, be elaborated.It comprises: three high speed logic unit are respectively: DFF1 (611), DFF2 (612) and DFF3 (613), three NMOS pipes be as tail current source, two NAND gate, inverter and one or.
The drain electrode of first NMOS (621) pipe is connected to first trigger DFF1 (611) portion, with the switch of DFF1 as electric current.At this, the grid of NMOS (621) pipe has been connected to supply voltage.Therefore, it is often opened.
The drain electrode of second NMOS (622) pipe is connected to second trigger DFF2 (612) portion, with the switch of DFF2 as electric current.At this, the grid of NMOS (622) pipe has been connected to supply voltage.Therefore, it is often opened.
The drain electrode of the 3rd NMOS (623) pipe is connected to the 3rd trigger DFF3 (613) portion, with the switch of DFF3 as electric current.At this, the grid of NMOS (623) pipe is connected to mode control signal.Therefore, its switch is by the state decision of mode control signal.
Outside input radio frequency signal CLK has been connected to the input 651,652 and 653 of three triggers.
The positive output port Q1 of DFF1 (611) is connected to the input port D2 of DFF2 (612).
The positive output end Q2 of DFF2 (612) is connected to the input port 4 of NAND gate (602).
The negative output port Q2 of DFF2 (612) is connected to the input port 1 of NAND gate (601).
The positive output port Q3 of DFF3 (613) be connected to or the door (641) input port 5.
Mode control signal MC is connected to the input 2 of NAND gate (602) and the input of inverter.
The output of inverter be connected to or the door (641) input 6.
Or the output of door (641) is connected to the input 3 of NAND gate (602).
Three triggers are SCL structures, also can be other structures, such as: the TSPC structure.Fig. 8 is the circuit diagram of SCL structure trigger.
The principle of this dual-modulus prescaler of brief description, when MC=1, when just being high level, NMOS pipe (623) is opened, and DFF3 (613) is in normal operating conditions, and whole dual-modulus prescaler and traditional as shown in Figure 4 being as good as at this moment, are 5 frequency divisions.When MC=0, when just being low level, NMOS pipe (623) is closed, and DFF3 (613) is in resting state, and the division function of dual-modulus prescaler is finished by DFF1, DFF2.The input 3 needed high level of NAND gate (602) by mode control signal through inverter (631) and or (641) after obtain.At this moment, be 4 frequency divisions.
In sum, the present invention proposes a kind of N/N+1 dual-modulus prescaler with self-adapting dormancy function, it is according to the concrete numerical value and the mode control signal of frequency division value, and one of them high speed logic unit is in resting state, not consumed power.Obviously, this technology has reduced the power consumption when dual-modulus prescaler is in except that the N pattern, has comparatively significantly practical value and economic worth.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1, a kind of dual-modulus prescaler with self-adapting dormancy, it is characterized in that, this dual-modulus prescaler is made of a plurality of high speed logics unit, a logic control circuit and a plurality of metal-oxide-semiconductor as current source, the high speed logic unit has a clock trigger end, a signal input part and a signal output part, the clock of high speed logic unit triggers the external clock signal clk of termination, the signal input part of high speed logic unit connects the output of logic control circuit, the signal output part and the foreign mode control signal of the input termination high speed logic unit of logic control circuit.
2, the dual-modulus prescaler with self-adapting dormancy according to claim 1, it is characterized in that, the mode control signal that the input of described logic control circuit receives determines the frequency division value of this dual-modulus prescaler, output at this dual-modulus prescaler can produce one by the signal of frequency division, concrete numerical value and mode control signal according to frequency division value, one of them high speed flip flop is in resting state by the shutoff as the metal-oxide-semiconductor of current source, not consumed power.
3, the dual-modulus prescaler with self-adapting dormancy according to claim 1 is characterized in that, described high speed logic unit is latch or trigger.
4, the dual-modulus prescaler with self-adapting dormancy according to claim 3 is characterized in that, described trigger is real single phase clock TSPC element circuit.
5, the dual-modulus prescaler with self-adapting dormancy according to claim 3 is characterized in that, described latch is a standard cell logic SCL element circuit.
6, the dual-modulus prescaler with self-adapting dormancy according to claim 1 is characterized in that, described metal-oxide-semiconductor as current source is a N type metal-oxide-semiconductor, or P type metal-oxide-semiconductor.
7, according to claim 1 or 6 described dual-modulus prescalers, it is characterized in that with self-adapting dormancy, described metal-oxide-semiconductor open or disconnected state is determined by mode control signal.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102710259A (en) * | 2012-06-15 | 2012-10-03 | 江苏物联网研究发展中心 | True single-phase clock dual-mode prescaler with high speed and low power consumption |
| CN105262478A (en) * | 2015-11-16 | 2016-01-20 | 东南大学 | E-TSPC structure-based low-power 2/3 frequency divider circuit |
| CN106533436A (en) * | 2015-06-30 | 2017-03-22 | 特克特朗尼克公司 | Automatic frequency prescaler |
| CN109039331A (en) * | 2018-10-30 | 2018-12-18 | 中国电子科技集团公司第五十四研究所 | A kind of digital 8/9 pre- frequency dividing circuit for local oscillation circuit |
| CN111711447A (en) * | 2020-06-22 | 2020-09-25 | 西安博瑞集信电子科技有限公司 | Prescaler and frequency divider |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2002052727A1 (en) * | 2000-12-22 | 2002-07-04 | Koninklijke Philips Electronics N.V. | Frequency divider with reduced power consumption, apparatus based thereon, and method for power efficient frequency divider |
| DE602004026760D1 (en) * | 2003-10-23 | 2010-06-02 | Nxp Bv | FREQUENCY DIVIDER |
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2008
- 2008-07-16 CN CN2008101167317A patent/CN101630957B/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102710259A (en) * | 2012-06-15 | 2012-10-03 | 江苏物联网研究发展中心 | True single-phase clock dual-mode prescaler with high speed and low power consumption |
| CN102710259B (en) * | 2012-06-15 | 2014-08-13 | 江苏物联网研究发展中心 | True single-phase clock dual-mode prescaler with high speed and low power consumption |
| CN106533436A (en) * | 2015-06-30 | 2017-03-22 | 特克特朗尼克公司 | Automatic frequency prescaler |
| CN106533436B (en) * | 2015-06-30 | 2021-08-06 | 特克特朗尼克公司 | Automatic prescaler |
| CN105262478A (en) * | 2015-11-16 | 2016-01-20 | 东南大学 | E-TSPC structure-based low-power 2/3 frequency divider circuit |
| CN105262478B (en) * | 2015-11-16 | 2017-11-07 | 东南大学 | A kind of divider circuit of low-power consumption 2/3 based on E TSPC structures |
| CN109039331A (en) * | 2018-10-30 | 2018-12-18 | 中国电子科技集团公司第五十四研究所 | A kind of digital 8/9 pre- frequency dividing circuit for local oscillation circuit |
| CN109039331B (en) * | 2018-10-30 | 2024-02-27 | 中国电子科技集团公司第五十四研究所 | Full-digital 8/9 prescaler circuit for local oscillation circuit |
| CN111711447A (en) * | 2020-06-22 | 2020-09-25 | 西安博瑞集信电子科技有限公司 | Prescaler and frequency divider |
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