CN101630899A - Method and device for forming SPWM waveform based on embedded type NIOS soft IP core - Google Patents

Abstract

The invention relates to a method and a device for forming a SPWM waveform based on an embedded type NIOS soft IP core. The method is characterized by comprising the following steps that: 1) an SOPC system comprising an NIOS core, a PWM module, an I/O port, a timer, a memory and a register is established; the PWM comprises an input clock(CLK), an output signal(PWM_OUT), an allowing bit, a 32-bit modulo-N counter and a 32-bit comparator, and the CLK drives the 32-bit modulo-N counter to establish a cycle of the PWM-OUT signal; the comparator compares the current value with the duty ratio value of the modulo-N counter and then determines the output of the PWM_OUT; and if the current value is less than or equal to the duty ratio value, the drive logic of the PWM-OUT is zero, otherwise, the drive logic of the PWM-OUT is one; and 3) the PWM, the I/O port and the timer of the NIOS system are initialized. The invention also provides a forming device for forming the SPWM waveform based on the embedded type NIOS soft IP core method, and the device comprises the NIOS core, the PWM module, the I/O port, the timer, the memory and the register.

Description

Formation method and device based on the SPWM waveform of embedded type NIOS soft IP core

Technical field

The present invention relates to a kind of embedded system, relate in particular to a kind of formation method and device of the SPWM waveform based on embedded type NIOS soft IP core.

Background technology

Sinusoidal pulse width modulation, promptly the SPWM technology has a wide range of applications in the power electronic equipment that with the voltage source inverter circuit is core, and how producing SPWM pulse train and realization means thereof is keys of SPWM technology.

Utilize the simulation comparison method, triangular carrier and sinusoidal modulation wave are compared, can produce the SPWM pulse; Utilize digital algorithm and timing logic, also can produce the SPWM pulse.

At present existing multiple microprocessor chip as 80C196MC, TMS320F240 etc., itself is integrated with Digital PWM generation circuit.The analogy method simple, intuitive, but with the inconvenience of digitial controller interface, be difficult to satisfy complicated requirement; The digital method structure is flexible, PWM generator that especially microprocessor is built-in, use convenient.

Under the usual condition, microprocessor must carry out Interrupt Process by regularly interrupt service routine generation SPWM pulse at each carrier cycle, and processing speed is had relatively high expectations, further improve thereby also limited carrier frequency, the Processing tasks of microprocessor is also heavier simultaneously.Uncertain interrupt response can cause the phase jitter of pwm pulse in the microprocessor.

Along with the requirement of modern industry and the progress of microelectric technique, the interchange transmission has promptly turned to digital control from simulation control, and wherein the PWM technology and method is its core content.But the Digital PWM circuit is the difficult point in the design always, except the microprocessors such as 80C196MC, TMS320F240 of integrated three-phase PWM generator, all adopt the integrated circuit designing thought of medium and small specification to produce SPWM, this is very complicated, often makes circuit complexity, poor reliability.

Introduced a kind of three-phase PWM generator of realizing with monolithic large-scale F PGA below, it has characteristics such as three-phase pulse center symmetry, PWM cycle and Dead Time be able to programme, and excellent performance, flexibility and reliability height.

Prior art one:

Utilize the FPGA Field Programmable Gate Array as the control core, directly form the SPWM pulse width modulated wave in conjunction with the DDS digital frequency synthesis technology.

Prior art two:

Fig. 1 is the PWM partial design block diagram of realizing with FPGA, and it mainly is made of several parts such as pulse width register, buffer register, period register, dead band register, dead band generator, digital comparator, control logics.Pulse width register, the pulsewidth of decision three-phase PWM signal; Buffer register is realized the double buffering to pulse-width data; Period register, the chopping cycle of decision PWM; Dead band register, the Dead Time of decision upper and lower bridge arm.Pulse width register in each switch periods by microprocessor with upgrade once, its dateout through cushioning after and reference counter carry out numeric ratio, obtain three-phase PWM signal PA, PB, PC.Handle through dead-zone circuit again, produce 6 centrosymmetric PWM drive signals at last, drive 6 power devices of three-phase inverter.The PWM algorithm can adopt SPWM, i.e. sine pulse width modulation (PWM) or SVPWM, i.e. space vector PWM.

Reference counter among the FPGA is used for producing the triangular wave benchmark in the similar analog circuit, is that a least count value is 0, maximum count value is the numerical value of preserving in the period register, the forward-backward counter of counting direction alternate.The reference counter unit produces a synchronizing signal SYN when maximum count value, when it is effective, the data of three pulse width register are deposited in buffer register separately, realize double buffering, make three pulse width register when SYN is invalid, can not influence final three-phase synchronized relation by the microprocessor renewal successively.The reference counter unit produces a direction signal DIR simultaneously, can be used as the exterior interrupt (edge-triggered mode) of microprocessor, interrupts in the starting point generation of PWM switch periods.

The microprocessor software design is simpler, set period register, dead band register at initial phase, need later on only in the PWM interrupt service routine, will to calculate the three-phase pulse-width data of getting well and deliver to separately pulse width register respectively, withdraw from interrupt service routine then, wait for controller under SYN pulse control with the data latching of three pulse width register in buffer register separately.Export corresponding pulse in cycle at next PWM, interrupt simultaneously being triggered, just begun next PWM interrupt service routine.Program requirement PWM interrupt service routine has determined the PWM maximum running frequency thus less than the PWM cycle running time.Fig. 2 is the PWM oscillogram.

Prior art three:

The three-phase pulse width modulated inverter control circuit that adopts traditional HEF4752 control chip to form, this control circuit have needs more peripheral cell, and programming is than shortcomings such as complexity.

Having the following disadvantages respectively of above prior art: in technology one, utilize FPGA to produce the SPWM waveform in conjunction with DDS for the control core, the control signal that this mode produces can satisfy the requirement of general control system, but is to satisfy the control precision of system far away for topicality and control precision are required all very high this control mode of UPS.

Though in technology two foundation of control system complicated and to the designer in all very high popularization that is unfavorable for technology of the requirement of hardware and software.

Utilize traditional special integrated circuit to reduce reliability of products greatly, and for UPS is this this mode of the high product of reliability requirement has been replaced by the full-digital control mode, expensive also is the huge challenge that analog control mode faced, and the life cycle of software and hardware portability and product has just been finalized the design when design and has been unfavorable for the upgrading of product.

Summary of the invention

Technical problem to be solved by this invention provides a kind of can the selection in multiple systems configuration combination, the formation method based on the SPWM waveform of embedded type NIOS soft IP core that performance and characteristic good and cost are low.

For solving the problems of the technologies described above, the present invention adopts following technical proposals:

Formation method based on the SPWM waveform of embedded type NIOS soft IP core comprises following steps:

Foundation comprises NIOS nuclear, the PWM module, and the I/O port, timer, the SOPC system of memory and register,

PWM comprises an input clock (CLK), an output signal (PWM_OUT), and one allows the position, one 32 modulo-N counter and one 32 s' comparator, CLK drives 32 modulo-N counter, the cycle of setting up the PWM_OUT signal; Comparator is the currency and the dutyfactor value of modulo-N counter relatively, the output of decision PWM_OUT; If currency is less than or equal to dutyfactor value, then PWM_OUT drives logical zero; Otherwise driving logical one;

PWM, I/O mouth, timer in the NIOS system are carried out initialization.

Correspondingly, the present invention also provides and realizes said method ground device, and its technical scheme is:

Formation device based on the SPWM waveform of embedded type NIOS soft IP core is characterized in that this device comprises NIOS nuclear, PWM module, I/O port, timer, memory and register.

Described PWM module comprises an input clock CLK, an output signal PWM_OUT, and one allows the position, one 32 modulo-N counter and one 32 s' comparator.

The beneficial effect that technical solution of the present invention is brought:

Adopt Nios II processor and design, product can be introduced to the market rapidly, prolong the product life cycle, prevent the processor obsolescence.The reason division is as follows:

One: customizable feature set

Adopt Nios II processor, the processor technology that you will can not be confined to make in advance, but, select suitable peripheral hardware, memory and interface as required according to oneself standard customized processor.In addition, your can also be easily integrated own proprietary function makes your design have unique competitive advantage.

Two: the configuration-system performance

Your needed processor should be able to satisfy design performance demand at present and in the future.Because Future Development has uncertainty, therefore, Nios II designer must can change its design, adds a plurality of NiosII CPU, custom instruction collection, hardware accelerator, to reach new performance objective.Adopt Nios II to handle

The TM device, you can come the Adjustment System performance by the Avalon architecture for exchanging, and this framework is the proprietary interconnection technique of Altera, supports multiple parallel data passage, realizes big throughput application.

Three: the low-cost realization

When selection processor, for the function that realizes needing, you buy the processor of Duoing than actual quantity needed possibly, also may be in order to save cost, and have to buy the processor that lacks than actual needs quantity.Low-cost, customizable NiosII processor can help you to solve this difficult problem.Adopt Nios II processor, you TM can be provided with function as required, implements in price is low to moderate 35 cents low-cost Altera devices such as Cyclone (R) II FPGA.In single FPGA, realize processor, peripheral hardware, memory and I/O interface, can reduce your overall system cost.

Four: product management life cycle

For realizing the product of a success, you need introduce it to the market as early as possible, strengthen its functional characteristic to extend working time, and avoid occurring the processor obsolescence.You can transfer Nios II flush bonding processor to system by initial concept imagine and realize at short notice.This system based on Nios II processor has permanent royalty-free design permission, stands the test of time fully.In addition, owing to realize soft-core processor in FPGA, therefore can conveniently realize on-the-spot hardware and software upgrading, product can meet up-to-date standard, possess up-to-date characteristic.

In sum, when carrying out system-level exploitation, can effectively reduce R﹠D costs; Can prolong the life cycle of product; Performance requirement according to product cuts out the purpose that satisfactory processor structure reaches the reasonable resources utilization and saves cost; The integrated level of effective raising system; Effectively reduce system power dissipation.

Description of drawings

Below in conjunction with the drawings and the specific embodiments, the invention will be further described.

Fig. 1 is the circuit diagram of prior art two;

Fig. 2 is the PWM oscillogram;

Fig. 3 is the fundamental diagram of PWM module of the present invention;

Fig. 4 is the operation principle program flow diagram of PWM module of the present invention;

Fig. 5 is an interrupt routine flow chart of the present invention;

Fig. 6 is a circuit diagram of the present invention.

Embodiment

The SPWM drive signal that the embodiment of the invention utilizes fpga chip EP2C35F484C8N that ALTERA company provides and embedded soft nuclear NIOS II to realize three level mid point clamper inverters.According to the hardware platform of system requirements design based on embedded soft nuclear NIOS II; On NIOS II hardware platform basis, utilize NIOS software development environment NIOS IDE to realize the software development of system; Utilize the SPI among the SOPC BUIDING to examine existing data transaction control to outside A/D conversion chip AD7927; Customization is based on user's peripheral hardware of AVALON---the realization of PWM peripheral hardware.Utilize SOPC software-hardware synergism technology to carry out the SOC design based on FPGA or CPLD programming device.

System design comprises hardware designs and software design two large divisions.Hardware designs is meant to be set up NIOS nuclear and adds this nuclear and other necessary system modules, sets up the TCL script file, processes such as compiling download.Software design is finished in NIOS IDE.This software is the support hardware descriptive language not only, and supports the C language, therefore, can be easy to hardware components is loaded and systems soft ware is designed.The fpga chip EP2C35F484C8N that the design is based on ALTER company has finished the SOPC system of the design of whole system by the requirement of SOPC guide BUILDER cutting compliance with system, utilizes NIOS IDE to finish the design of whole system software again.

Below each system is carried out division:

The SOPC system sets up (hardware system foundation):

System mainly by being NIOS nuclear, the PWM module, the I/O port, modules such as timer and memory are formed; The PWM The Logic of Tasks is by an input clock (CLK), an output signal (PWM_OUT), and one allows the position, and one 32 modulo-N counter and one 32 s' comparator is formed.CLK drives 32 modulo-N counter, the cycle of setting up the PWM_OUT signal.Comparator is the currency and the dutyfactor value of modulo-N counter relatively, the output of decision PWM_OUT.If currency is less than or equal to dutyfactor value, then PWM_OUT drives logical zero; Otherwise driving logical one.

Referring to shown in Figure 3, register file provides enable bit, the value of modulo-N counter and the visit of dutyfactor value.Wherein the CLK_DIVIDE register determines the clock periodicity in the one-period of PWM output.The DUTY_CYCLE register has determined PWM to be output as low level clock periodicity.Read-write control to above two registers just can obtain three-phase tri-level inversion control waveform; After having finished SOPC system design and PWM operation principle, introduce the producing method of the drive signal SPWM waveform of realizing the three-phase tri-level inverter how on this basis.This value has just determined the cycle of PWM waveform when CLK_DIVIDE is write, the value that makes DUTY_CYCLE is during by sinusoidal variations, just obtain the drive waveforms of three-phase inverter, the realization of this process is finished in NIOS Integrated Development Environment NIOS IDE, and its concrete program flow diagram as shown in Figure 4.

Referring to Fig. 5, PWM in the NIOS system, I/O mouth, the configuration of the part of assemblies such as timer be invocation component the time configured, in software programming, only need just can use these assemblies to finish design very easily to carrying out some necessary initialization.

This interruption can only produce six road SPWM waveforms simultaneously, find that when we have studied the inversion drive waveforms of three level going up in the drive waveforms of four power switch pipes of brachium pontis and following brachium pontis mutually at A is complementary in twos, producing complementary signal for FPGA only needs in FPGA inside two-way SPWM waveform negate output and can obtain conducting that four road SPWM waveforms are used to drive four power switchs of A phase and finish the inversion of A phase and export respectively again.

As shown in Figure 6, the circuit diagram of a specific embodiment of the present invention, this figure only illustrate the formation circuit of single-phase SPWM drive waveforms.Use the same method and just can produce the SPWM drive waveforms of other two-phase.

Below operation principle of the present invention is described in detail:

At first introduce the carrier modulation control principle, for the three-phase tri-level inverter, every two triangular carriers with same frequency fc and identical peak A c and frequency of adopting mutually is that the sine wave of Am is compared for the fm peak value, and two triangular carrier regions are continuous.When the sinusoidal wave moment of intersecting with triangular carrier, if the amplitude of modulating wave greater than the amplitude of certain triangular carrier, is then opened corresponding switching device, otherwise, if the amplitude of modulating wave less than the amplitude of certain triangular carrier, is then turn-offed corresponding switching device.

Utilize SOPC software-hardware synergism technology to carry out the SOC design based on FPGA or CPLD programming device.System design comprises hardware designs and software design two large divisions.Hardware designs is meant to be set up NIOS nuclear and adds this nuclear and other necessary system modules, sets up the TCL script file, processes such as compiling download.SOPC system by guide's SOPCBUILDER cutting compliance with system requires is utilizing NIOS IDE to finish the design of whole system software.Software design is finished in NIOS IDE.This software is the support hardware descriptive language not only, and supports the C language, therefore, can be easy to hardware components is loaded and systems soft ware is designed.

The advantage of three level neutral-point-clamped inverter topologies: each power device only bears the bus of half Voltage is so available withstand voltage low device is realized High voltage output; Compare with traditional contravarianter voltage output waveform, The more approaching sine wave of three-level inverter output voltage wave, and harmonic content reduces; Current-rising-rate and electricity The pressure rate of change reduces, and electromagnetic interference reduces etc. greatly. Because its superior performance is studied at present and is used the most One of ripe multi-electrical level inverter structure.

Claims (3)

1, a kind of formation method of the SPWM waveform based on embedded type NIOS soft IP core is characterized in that it may further comprise the steps:

1) foundation comprises NIOS nuclear, the PWM module, and the I/O port, timer, the SOPC system of memory and register,

2) PWM comprises an input clock (CLK), an output signal (PWM_OUT), and one allows the position, one 32 modulo-N counter and one 32 s' comparator, CLK drives 32 modulo-N counter, the cycle of setting up the PWM_OUT signal; Comparator is the currency and the dutyfactor value of modulo-N counter relatively, the output of decision PWM_OUT; If currency is less than or equal to dutyfactor value, then PWM_OUT drives logical zero; Otherwise driving logical one;

3) PWM, I/O mouth, timer in the NIOS system are carried out initialization.

2, a kind of formation device of realizing the formation method of the described SPWM waveform based on embedded type NIOS soft IP core of claim 1 is characterized in that this device comprises NIOS nuclear, PWM module, I/O port, timer, memory and register.

3, formation device according to claim 2 is characterized in that described PWM module comprises an input clock CLK, an output signal PWM_OUT, and one allows the position, one 32 modulo-N counter and one 32 s' comparator.

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