CN104113064A - Active power filter control system with modularized parallel processing and method of the control system - Google Patents
Active power filter control system with modularized parallel processing and method of the control system Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02E40/20—Active power filtering [APF]
Abstract
The invention discloses an active power filter control system with modularized parallel processing. The system includes a display, a main control panel, a first slave control panel, a second slave control panel, a third slave control panel, a voltage sensor and a current sensor, the main control panel is connected with the display, the voltage sensor, and the current sensor, and the main control panel is connected with the first slave control panel, the second slave control panel and the third slave control panel. The invention also discloses a control method of the active power filter control system with modularized parallel processing. According to the control method, for industrial occasions, three-phase loads are used, high speed parallel processing capability of an FPGA is utilized to implement three-phase modularized control and perform parallel detection and processing on three-phase harmonic current, thereby shortening a computing period, increasing the number of times of harmonic detection within a certain time, improving detection precision, and satisfying various load requirements.
Description
Technical field
The invention discloses a kind of active power filter control system and method thereof of modularization parallel processing, be specifically related to a kind of harmonic wave extraction algorithm, belong to Automation of Electric Systems product and Power Quality Detection control technology field thereof.
Background technology
Active Power Filter-APF (APF) is as a kind of power electronic equipment that can dynamically suppress harmonic current and extensive concern.The compensation performance quality of APF has much relations with its control algolithm adopting.
Traditional detection logic is that A phase, B phase, C detect respectively mutually in order, then output current in order, and the computation delay that this has just caused in processor calculating process, causes computational efficiency low, and has affected the real-time of result.
Traditional algorithm time cost conventional in prior art is larger, and detection speed is low, and the harmonic track effect of entirety is also undesirable.The control method of the modularization parallel processing based on FPGA, saves time more than traditional algorithm, has therefore improved detection speed, improves overall harmonic track effect.
Summary of the invention
Technical problem to be solved by this invention is: for the defect of prior art, a kind of active power filter control system and method thereof of modularization parallel processing are provided, modular, harmonic compensation way faster more flexibly,, better adapt to electrical network and various load characteristic, the harmonic current in compensation network electric current.
The present invention is for solving the problems of the technologies described above by the following technical solutions:
A kind of active power filter control system of modularization parallel processing, comprise that display, master board, first are from control board, second from control board, the 3rd from control board, voltage sensor and current sensor, described master board is connected with display, voltage sensor, current sensor respectively, and master board also respectively with first, second, third is connected from control board, in described master board, be provided with master controller, specifically comprise: data acquisition module, the phase-locked module of line voltage, DFT controller, three-phase sliding window DFT module, three-phase reference current generation module and communication interface, described voltage sensor is connected with data acquisition module respectively with current sensor, data acquisition module respectively with the phase-locked module of line voltage, DFT controller is connected, DFT controller is connected with three-phase sliding window DFT module respectively, three-phase sliding window DFT module is being connected with three-phase reference current generation module of correspondence successively, three-phase reference current generation module is connected with communication interface respectively, described master controller is used for realizing that mains by harmonics and idle detection, line voltage are phase-locked, current reference generation, electric current and voltage controller, drive signal to produce and hardware lockout drives signal.
Described first, second, the 3rd is provided with from controller from control board, specifically comprise: from controller data acquisition module, from controller communication interface, Voltage loop controller, current loop controller, protection module and modulation module, describedly be connected with voltage sensor from controller data acquisition module, from controller data acquisition module also successively with Voltage loop controller, current loop controller, modulation module is connected, described protection module is also connected with modulation module, respectively with three Single-phase SPWM modules of output of modulation module are connected, describedly be connected with the communication interface master board from controller communication interface, also be connected with modulation module through current loop controller from controller communication interface, described from controller for realizing opening and adhesive and the release of shutoff and relay of power ratio control device.
As present invention further optimization scheme, the phase-locked module of described line voltage comprises four inputs and two outputs, described input connects respectively digital signal and the external interface module of overall situation control clock, global reset signal, three-phase voltage, and described output connects respectively the running status output port of Output rusults port and current this module.
As present invention further optimization scheme, described three-phase sliding window DFT module comprises six inputs and three outputs, described input connects respectively the overall situation and controls the RAM interface between clock, overall reset signal, the input of load-side electric current, sliding window DFT Data Update, MCU and hardware interface, and described output connects respectively the amplitude output of sliding window DFT end mark position, k subharmonic, the angle values output of k subharmonic.
As present invention further optimization scheme, described three-phase reference current generation module is harmonic wave synthetic controller, specifically comprise seven inputs and three outputs, described input connects respectively amplitude input, the angle values input of k subharmonic, the phase angle of phase-locked loop output, the benchmark output of DC bus, the harmonic synthesizer sign on input of overall situation control clock, overall reset signal, k subharmonic, and described output connects respectively the Irefn_H output of harmonic synthesizer end of synthesis flag bit, composition algorithm generation.
As present invention further optimization scheme, described Voltage loop controller from control board is voltage PID controller, specifically comprise four inputs and two outputs, described input connects respectively the overall situation and controls clock, overall reset signal, the reference voltage input of dc-link capacitance, DC capacitor voltage input, and described output connects respectively the output that finishes algorithm flag bit, voltage pid algorithm.
As present invention further optimization scheme, described current loop controller from control board is current PI D controller, specifically comprise five inputs and two outputs, described input connects respectively the overall situation to be controlled clock, overall reset signal, harmonic wave synthetic input end, three-phase tri-level output current sampled value input, current PI D and calculates opening flag position, and described output connects respectively the output of end algorithm flag bit, current PI D-algorithm.
As present invention further optimization scheme; described Single-phase SPWM module comprises five inputs and an output; described input connects respectively the overall situation and controls clock, overall reset signal, the input of monophase current adjuster, the status signal input of adjuster, guard signal input, and described output connects driving signal output part.
The invention also discloses a kind of control method of active power filter control system of the modularization parallel processing based on described, master controller is carried out three-phase parallel processing in the time that harmonic wave detects, A phase, B phase, C are carried out to detection calculations when identical, and while parallel output result, concrete steps comprise:
Step 1, voltage sensor real-time sampling three-phase voltage, be sent to respectively master controller and from controller, from controller, A phase line voltage delivers to first from controlling, and B phase line voltage delivers to second from controller, and C phase line voltage delivers to the 3rd from controller;
Step 2, current sensor detect load current, export in real time master controller to, and master control adopts DFT algorithm, and load current is carried out to harmonic wave extraction, obtains output harmonic wave electric current, and exports in real time them to three from controller;
Step 3, use external impressed current Hall element detect the output current of Active Power Filter-APF, and feed back to from controller, from controller, itself and the given signal of harmonic current receiving are compared to control, through chopper regulator, control switch pipe output current, and follow the tracks of the harmonic current detecting.
As the further preferred version of above-mentioned control method, the DFT algorithm in described step 2 is specific as follows:
If in the n-1 moment, choose N sample in three-phase sliding window DFT module:
{x(n-N),x(n-N+1),......,x(n-2),x(n-1)}；
At moment n, in three-phase sliding window DFT module, choose N sample:
{x(n-N+1),x(n-N+2),......,x(n-2),x(n-1),x(n)}；
, the computational methods in the time of n-1 moment, the n moment are as follows respectively for k spectrum unit of N sample:
The present invention adopts above technical scheme compared with prior art, all threephase load for industrial occasions, utilize the high-speed parallel disposal ability of FPGA, carry out three-phase modular control, three phase harmonic electric current is carried out to parallel detection and processing, reduce computing cycle, increase harmonic wave in certain hour and detect number of times, improve accuracy of detection, meet various loading demands.The present invention has following technique effect:
1) modularization APF, module is furnished with one from controller, and module main circuit is H bridge; Separate between each APF module, facilitate capacity extensions; Can be easy to realize parallel connection, series connection etc.;
2) centralized control; Respectively mutually separate, by master controller, modules to be controlled, system reliability is high;
3) support hot plug; Each independently APF can be connected to the grid in real time and depart from electrical network;
4) every phase has separate " single-phase " APF, is furnished with a controller for each single-phase APF, and the controller of three-phase carries out centralized control by central primary control device processed;
5) adopt FPGA high speed processor, high-speed AD dress changes chip, improves detection speed and current tracking performance, improves filter filtering characteristic.
Brief description of the drawings
Fig. 1 is overall system framework schematic diagram.
Fig. 2 is master controller theory diagram.
Fig. 3 is line voltage phase-locked loop module.
Fig. 4 is line voltage phase-locked loop module sequential chart.
Fig. 5 is to be sliding window DFT schematic diagram.
Fig. 6 is DFT sequential chart.
Fig. 7 is harmonic wave synthetic controller schematic diagram.
Fig. 8 is the synthetic sequential chart of harmonic wave.
Fig. 9 is from controller principle block diagram.
Figure 10 is voltage PID schematic diagram.
Figure 11 is voltage PID sequential chart.
Figure 12 is current PI D schematic diagram.
Figure 13 is current PI D sequential chart.
Figure 14 is Single-phase SPWM module.
Figure 15 is SPWM modulation timing figure.
Embodiment
Describe embodiments of the present invention below in detail, the example of described execution mode is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the execution mode being described with reference to the drawings, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Those skilled in the art of the present technique are understandable that, the correlation module relating in the present invention and the function of realization thereof are in device, device or the system of hardware after improvement and formation thereof, to carry computer software programs or relevant agreement conventional in prior art just can realize, and are not that computer software programs of the prior art or relevant agreement are improved.For example, the computer hardware system after improvement still can realize by loading existing operation system of software the specific function of this hardware system.Therefore, be understandable that, innovation of the present invention is improvement to hardware module in prior art and connects syntagmatic, but not be only in hardware module for realizing the software that carries about function or the improvement of agreement.
Those skilled in the art of the present technique are understandable that, the correlation module of mentioning in the present invention is the one or more hardware device in step for carrying out operation described in the application, method, flow process, measure, scheme.Described hardware device can be required object specialized designs and manufacture, or also can adopt known device in all-purpose computer or other known hardware devices.Described all-purpose computer has storage procedure Selection therein and activates or reconstruct.
Unless those skilled in the art of the present technique are appreciated that specially statement, singulative used herein " ", " one ", " described " and " being somebody's turn to do " also can comprise plural form.Should be further understood that, the wording using in specification of the present invention " comprises " and refers to and have described feature, integer, step, operation, element and/or assembly, exists or adds one or more other features, integer, step, operation, element, assembly and/or their group but do not get rid of.Should be appreciated that, when we claim element to be " connected " or " coupling " when another element, it can be directly connected or coupled to other elements, or also can have intermediary element.In addition, " connection " used herein or " coupling " can comprise wireless connections or couple.Wording "and/or" used herein comprises arbitrary unit of listing item and all combinations that one or more is associated.
Those skilled in the art of the present technique are appreciated that unless otherwise defined, all terms used herein (comprising technical term and scientific terminology) have with the present invention under the identical meaning of the general understanding of those of ordinary skill in field.Should also be understood that such as those terms that define in general dictionary and should be understood to have the meaning consistent with meaning in the context of prior art, unless and definition as here, can not explain by idealized or too formal implication.
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:
As shown in Figure 1, the master and slave core controller of FPGA is the core of whole control section to overall system framework schematic diagram, and its required practical function comprises computational load harmonic wave and idle, APF offset current control, system protection function, user interface interaction.
As shown in Figure 2, master controller is realized core algorithm to master controller theory diagram, and the hardware directly being configured by FPGA is realized, to reduce time delay; This module realizes the Core Feature of APF, comprises that mains by harmonics and idle detection, line voltage are phase-locked, current reference generation.Executed in parallel between each little module in this hardware module, intermodule has suitable communication interface.Master controller is the digitial controller based on FPGA, and its hardware module mainly comprises data acquisition module, the phase-locked module of line voltage, sliding window DFT module, reference current generation module, communication interface etc.
In Fig. 2, ea, eb, ec are three phase network voltage, and iLa, iLb, iLc are threephase load electric current; Two kinds of signals are after data acquisition module, and three phase network Voltage-output, to phase-locked module, is used for calculating line voltage phase angle, for harmonic wave provides phase angle foundation; Threephase load electric current, exports DFT controller, sliding window to, and output three phase harmonic electric current is as reference current;
Master controller, in the time that harmonic wave detects, is carried out three-phase parallel processing, and to detect 3 subharmonic as example, traditional detection logic is that A phase, B phase, C detect respectively mutually in order, then output current in order; And in the present invention, utilize the powerful parallel processing capability of FPGA, A phase, B phase, C are carried out to while detection calculations mutually, Output rusults is also parallel output, avoid the computation delay in processor calculating process, improved computational efficiency, and improved the real-time of result.
Line voltage phase-locked loop module in main controller module, as shown in Figure 3, Gclk is that the overall situation is controlled clock, U
datait is the digital signal from the three-phase voltage of external interface module; This signal and Re_PLL are the interfaces of this module and external interface module, are used for controlling external sampling speed and sequential, read sampled result.Reset is global reset signal, the soft core of its MCU from FPGA.With Flag_PLL be the Output rusults of line voltage phase-locked loop module and the running status of current this module; They are to be connected with the module that needs electrical network phase information, and Fig. 4 has provided the sequential chart of this module.
Sliding window DFT function in main controller module is first-harmonic and the harmonic spectrum of computational load side electric current, for harmonic wave synthesis module provides amplitude and the phase angle information of each harmonic wave and fundamental current.The following algorithm of sliding window DFT module basis:
If the n-1 moment, sliding window choose N sample x (n-N), x (n-N+1) ..., x (n-2), x (n-1) }; At moment n, sliding window choose N sample for x (n-N+1), x (n-N+2) ..., x (n-2), x (n-1), x (n) }; In the n-1 moment, k spectrum unit of N point DFT and in the n moment, the pass of k the spectrum unit that N is ordered is:
Fig. 5 is sliding window DFT module diagram, and DFT_Datan is load-side electric current input value, and subscript represents a, b, c phase, and In (k) is amplitude and the X of k subharmonic
k+1corresponding amplitude, θ n (k) is phase angle and the X of k subharmonic
k+1corresponding angle values, subscript represents the number of selected harmonic, R_DFT upgrades for higher level notifies sliding window DFT data, need to carry out sliding window DFT algorithm, Flag_DFT is sliding window DFT end mark position, is used for pointing out sliding window DFT to finish, and Reset is clear 0 signal of the overall situation.Flag_re and Conf be and MCU and hardware interface between the interface of RAM, be used for the number of times of configuration extraction harmonic wave, sequential chart is as Fig. 6.
By sliding window DFT algorithm process above, out be an amplitude and phase angle, so need to synthesize to produce benchmark, be used for the use of rear class, Fig. 7 is harmonic wave synthetic controller, and it has amplitude and phase angle input pin, is used for connecting amplitude and the phase angle input that sliding window DFT produces; For the phase angle of phase-locked loop output; Udc_pi is the benchmark of DC bus output; Produce Irefn_H output by composition algorithm; Flag_DFT starts to synthesize for higher level notifies harmonic synthesizer; Flagn_H is harmonic synthesizer end of synthesis flag bit; Reset is clear 0 signal of the overall situation; Fig. 8 is the sequential chart of harmonic synthesizer.After harmonic wave is synthetic, produce the given signal of harmonic wave, by communication module, export to from controller, by complete the current tracking to given harmonic wave from controller, and the turn-on and turn-off of driving power switching tube are carried out output current control.
From the theory diagram of controller as shown in Figure 9, mainly comprise from controller that data acquisition, Voltage loop controller, current loop controller, driving signal produce and hardware lockout drives signal, modulation, protection and communicate by letter etc.; Three-phase adopts same control method from controlling, difference is that input is different with given harmonic current from the line voltage of controller, and other are all identical, and this is also one of main feature of the present invention, be exactly modularization, this module turns to dilatation and parallel operation provides great aspect.
Voltage controller from controller is voltage PID controller, and as shown in figure 10, sequential chart as shown in figure 11; Uref is the reference voltage of dc-link capacitance; Uin is DC capacitor voltage; Flag_Upi is for finishing algorithm flag bit; Upi is the output of voltage pid algorithm, and it is used for the needed signal of rear class control; Reset is clear 0 signal of the overall situation.
Current controller is also current PI D controller, and as shown in Figure 12,13, Irefn_H is the synthetic output of harmonic wave; I
l_ Datan is three-phase tri-level output current sampled value; Flagn_H notifies current PI D calculation flag position for higher level; Flagn_Ipi is for finishing algorithm flag bit; Ipi_n is the output of current PI D-algorithm, and it is used for rear class and modulates needed signal; Reset is clear 0 signal of the overall situation.
Single-phase SPWM module be used for producing main circuit switch pipe driving signal, realize guard signal block.Figure 14 is Single-phase SPWM module in FPGA, and output has 4 roads to drive signal, and input has 3 road signals.Gclk is system clock, and Reset is clear 0 signal of the overall situation; I
pithe output of monophase current adjuster, Flag_I
pithe status signal of adjuster, I
piand Flag_I
pijoin with current regulator module.Reset is global reset signal; Protect is respectively signal.V
gatebe 4 road output drive signals, be connected with external drive plate.Figure 15 has provided the typical sequential chart of this module.One phase of each Single-phase SPWM module controls Active Power Filter-APF, has realized three-phase and has independently controlled, non-interfering object.
In Fig. 9, Udc is the DC voltage that external voltage transducer detects, for the Voltage loop control from control board module; The data of communication interface are input as main controller module, and the signal such as the harmonic wave that comes up by the optical fiber communication transmission of 50M is given, phase angle, for the current compensation from control module and tracking loop; Guard signal is that external module detects the output signal after unit exception, at once carries out safeguard measure processing from control module receives guard signal; PWMa PWMb PWMc, relay control signal be the output signal from controller, for opening and adhesive and the release of shutoff and relay of power ratio control device.
By reference to the accompanying drawings embodiments of the present invention are explained in detail above, but the present invention is not limited to above-mentioned execution mode, in the ken possessing those of ordinary skill in the art, can also under the prerequisite that does not depart from aim of the present invention, makes a variety of changes.The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be not depart from technical solution of the present invention content, according to technical spirit of the present invention, within the spirit and principles in the present invention, the any simple amendment that above embodiment is done, be equal to replacement and improvement etc., within all still belonging to the protection range of technical solution of the present invention.
Claims (9)
1. the active power filter control system of a modularization parallel processing, it is characterized in that: comprise that display, master board, first are from control board, second from control board, the 3rd from control board, voltage sensor and current sensor, described master board is connected with display, voltage sensor, current sensor respectively, and master board also respectively with first, second, third is connected from control board;
In described master board, be provided with master controller, specifically comprise: data acquisition module, the phase-locked module of line voltage, DFT controller, three-phase sliding window DFT module, three-phase reference current generation module and communication interface, described voltage sensor is connected with data acquisition module respectively with current sensor, data acquisition module respectively with the phase-locked module of line voltage, DFT controller is connected, DFT controller is connected with three-phase sliding window DFT module respectively, three-phase sliding window DFT module is being connected with three-phase reference current generation module of correspondence successively, three-phase reference current generation module is connected with communication interface respectively,
Described master controller is used for realizing that mains by harmonics and idle detection, line voltage are phase-locked, current reference generation;
Described first, second, the 3rd is provided with from controller from control board, specifically comprise: from controller data acquisition module, from controller communication interface, Voltage loop controller, current loop controller, drive signal to produce and hardware lockout driving signal, protection module and modulation module, describedly be connected with voltage sensor from controller data acquisition module, from controller data acquisition module also successively with Voltage loop controller, current loop controller, modulation module is connected, described protection module is also connected with modulation module, respectively with three Single-phase SPWM modules of output of modulation module are connected, describedly be connected with the communication interface master board from controller communication interface, also be connected with modulation module through current loop controller from controller communication interface,
Described from controller for realizing opening and adhesive and the release of shutoff and relay of power ratio control device.
2. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1, it is characterized in that: the phase-locked module of described line voltage comprises four inputs and two outputs, described input connects respectively digital signal and the external interface module of overall situation control clock, global reset signal, three-phase voltage, and described output connects respectively the running status output port of Output rusults port and current this module.
3. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1, it is characterized in that: described three-phase sliding window DFT module comprises six inputs and three outputs, described input connects respectively the overall situation and controls the RAM interface between clock, overall reset signal, the input of load-side electric current, sliding window DFT Data Update, MCU and hardware interface, and described output connects respectively the amplitude output of sliding window DFT end mark position, k subharmonic, the angle values output of k subharmonic.
4. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1, it is characterized in that: described three-phase reference current generation module is harmonic wave synthetic controller, specifically comprise seven inputs and three outputs, described input connects respectively the overall situation and controls clock, overall situation reset signal, the amplitude input of k subharmonic, the angle values input of k subharmonic, the phase angle of phase-locked loop output, the benchmark output of DC bus, harmonic synthesizer sign on input, described output connects respectively harmonic synthesizer end of synthesis flag bit, the Irefn_H output that composition algorithm produces.
5. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1, it is characterized in that: described Voltage loop controller from control board is voltage PID controller, specifically comprise four inputs and two outputs, described input connects respectively the overall situation and controls clock, overall reset signal, the reference voltage input of dc-link capacitance, DC capacitor voltage input, and described output connects respectively the output that finishes algorithm flag bit, voltage pid algorithm.
6. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1, it is characterized in that: described current loop controller from control board is current PI D controller, specifically comprise five inputs and two outputs, described input connects respectively the overall situation to be controlled clock, overall reset signal, harmonic wave synthetic input end, three-phase tri-level output current sampled value input, current PI D and calculates opening flag position, and described output connects respectively the output of end algorithm flag bit, current PI D-algorithm.
7. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1; it is characterized in that: described Single-phase SPWM module comprises five inputs and an output; described input connects respectively the overall situation and controls clock, overall reset signal, the input of monophase current adjuster, the status signal input of adjuster, guard signal input, and described output connects driving signal output part.
8. the control method of the active power filter control system based on modularization parallel processing claimed in claim 1, it is characterized in that, master controller is carried out three-phase parallel processing in the time that harmonic wave detects, A phase, B phase, C are carried out to detection calculations when identical, and while parallel output result, concrete steps comprise:
Step 1, voltage sensor real-time sampling three-phase voltage, be sent to respectively master controller and from controller, from controller, A phase line voltage delivers to first from controlling, and B phase line voltage delivers to second from controller, and C phase line voltage delivers to the 3rd from controller;
Step 2, current sensor detect load current, export in real time master controller to, and master control adopts DFT algorithm, and load current is carried out to harmonic wave extraction, obtains output harmonic wave electric current, and exports in real time them to three from controller;
Step 3, use external impressed current Hall element detect the output current of Active Power Filter-APF, and feed back to from controller, from controller, itself and the given signal of harmonic current receiving are compared to control, through chopper regulator, control switch pipe output current, and follow the tracks of the harmonic current detecting.
9. the control method of the active power filter control system of a kind of modularization parallel processing as claimed in claim 8, is characterized in that, the DFT algorithm in described step 2 is specific as follows:
If in the n-1 moment, choose N sample in three-phase sliding window DFT module:
{x(n-N),x(n-N+1),......,x(n-2),x(n-1)}；
At moment n, in three-phase sliding window DFT module, choose N sample:
{x(n-N+1),x(n-N+2),......,x(n-2),x(n-1),x(n)}；
, the computational methods in the time of n-1 moment, the n moment are as follows respectively for k spectrum unit of N sample:
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106159960A (en) * | 2016-08-29 | 2016-11-23 | 南京亚派科技股份有限公司 | Based on series parallel structure modular subway energy back feed device closed loop control method |
| CN106253279A (en) * | 2016-08-23 | 2016-12-21 | 南京亚派科技股份有限公司 | A kind of anti-resonance control algolithm being applied to active filter |
| CN110677194A (en) * | 2019-09-27 | 2020-01-10 | 苏州爱科赛博电源技术有限责任公司 | Synchronous communication system based on optical fiber communication |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4328241B2 (en) * | 2004-02-26 | 2009-09-09 | 東京電力株式会社 | Active filter for power |
| CN102208810A (en) * | 2011-06-03 | 2011-10-05 | 华中科技大学 | Distributed control system for cascaded multilevel active power filter |
-
2014
- 2014-06-30 CN CN201410311081.7A patent/CN104113064B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4328241B2 (en) * | 2004-02-26 | 2009-09-09 | 東京電力株式会社 | Active filter for power |
| CN102208810A (en) * | 2011-06-03 | 2011-10-05 | 华中科技大学 | Distributed control system for cascaded multilevel active power filter |
Non-Patent Citations (1)
| Title |
|---|
| 戴珂等: "采用多DSP 的级联型DSTATCOM 分散控制策略", 《高电压技术》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106253279A (en) * | 2016-08-23 | 2016-12-21 | 南京亚派科技股份有限公司 | A kind of anti-resonance control algolithm being applied to active filter |
| CN106159960A (en) * | 2016-08-29 | 2016-11-23 | 南京亚派科技股份有限公司 | Based on series parallel structure modular subway energy back feed device closed loop control method |
| CN106159960B (en) * | 2016-08-29 | 2019-05-17 | 南京亚派科技股份有限公司 | Based on the modular subway energy back feed device closed loop control method of series and parallel structure |
| CN110677194A (en) * | 2019-09-27 | 2020-01-10 | 苏州爱科赛博电源技术有限责任公司 | Synchronous communication system based on optical fiber communication |
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