CN105406752A - Control system for I-type and T-type three-level bidirectional PWM (Pulse-Width Modulation) rectifiers - Google Patents
Control system for I-type and T-type three-level bidirectional PWM (Pulse-Width Modulation) rectifiers Download PDFInfo
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Abstract
Description
技术领域 technical field
本发明涉及电子电力控制领域,尤其涉及一种I型与T型三电平双向PWM整流器控制系统。 The invention relates to the field of electronic power control, in particular to an I-type and T-type three-level bidirectional PWM rectifier control system.
背景技术 Background technique
随着分布式能源设备接入电网的数量不断增加,智能电网的快速发展,使得分布式发电设备如光伏逆变器、风电变流器接入电网;新能源汽车充电桩的需要先交流电压转换成直流电压在进入DCDC控制环节;以上设备均需要PWM型逆变器或者整流器。可双向流动的PWM整流器不仅体现出AC/DC变流特性(整流),而且还可呈现出DC/AC变流特性(有源逆变),因而确切地说,这类PWM整流器实际上是一种新型的可逆PWM变流器。三电平拓扑分为I型三电平与T型三电平两种拓扑,其中I型的三电平的4个开关管耐压都可以小于直流母线电压,而T型三电平的外管耐压必须大与母线电压,两种拓扑可以采用通用PWM脉冲发送程序,因此可以将控制器进行整合统一。PWM整流器控制需要复杂的数学运算,传统的逆变器多采用单DSP的结构,存在运算速度相对较慢、动态响应不及时的缺点,不能够满足越来越复杂的控制算法需求。I型的T型三电平拓扑对输入脉冲时序有较高的要求,I型开关状态表如表1所示,T型开关状态表如表2所示。 With the increasing number of distributed energy equipment connected to the grid and the rapid development of smart grids, distributed power generation equipment such as photovoltaic inverters and wind power converters are connected to the grid; charging piles for new energy vehicles need AC voltage conversion first The DC voltage enters the DCDC control link; the above equipment requires a PWM inverter or rectifier. The PWM rectifier with bidirectional flow not only exhibits AC/DC conversion characteristics (rectification), but also exhibits DC/AC conversion characteristics (active inverter), so to be precise, this type of PWM rectifier is actually a A new type of reversible PWM converter. The three-level topology is divided into I-type three-level topology and T-type three-level topology. Among them, the withstand voltage of the four switching tubes of the I-type three-level can be lower than the DC bus voltage, while the T-type three-level external The withstand voltage of the tube must be greater than the bus voltage. The two topologies can use a common PWM pulse sending program, so the controller can be integrated and unified. PWM rectifier control requires complex mathematical operations. Traditional inverters mostly use a single DSP structure, which has the disadvantages of relatively slow operation speed and untimely dynamic response, and cannot meet the needs of increasingly complex control algorithms. The I-type T-type three-level topology has higher requirements on the input pulse timing. The I-type switch state table is shown in Table 1, and the T-type switch state table is shown in Table 2.
表1I型三电平开关状态表 Table 1 I-type three-level switch state table
表2T型三电平开关状态表 Table 2 T-type three-level switch state table
发明内容 Contents of the invention
本发明的目的就是针对以上技术问题,设计出一种I型与T型三电平双向PWM整流器控制系统,能够兼容I型与T型两种三电平电路,能够进行复杂的数学运算,能够进行PWM脉冲检测与纠正,实现高性能的控制和接口功能。 The object of the present invention is exactly to above-mentioned technical problem, designs a kind of I type and T type three-level two-way PWM rectifier control system, can be compatible with I type and T type two kinds of three level circuits, can carry out complex mathematical operation, can Perform PWM pulse detection and correction to realize high-performance control and interface functions.
本发明的技术问题主要通过下述技术方案得以解决: Technical problem of the present invention is mainly solved by following technical scheme:
一种I型与T型三电平双向PWM整流器控制系统,包括模拟量数据采集与调理电路、IGBT磁隔离驱动电路、DSP与CPLD组成的控制电路、继电器输出与数字信号输入、故障录波与远程通信,其特征在于,霍尔传感器数据采集电路、IGBT驱动电路、开入开出接口电路与CPLD芯片相连,通信电路和故障录波电路与DSP相连,DSP与CPLD通过数据、地址总线、PWM输出信号与中断信号相连。 An I-type and T-type three-level bidirectional PWM rectifier control system, including analog data acquisition and conditioning circuit, IGBT magnetic isolation drive circuit, control circuit composed of DSP and CPLD, relay output and digital signal input, fault recording and The remote communication is characterized in that the hall sensor data acquisition circuit, the IGBT drive circuit, the input and output interface circuit are connected to the CPLD chip, the communication circuit and the fault recording circuit are connected to the DSP, and the DSP and the CPLD are connected through the data, address bus, PWM The output signal is connected to the interrupt signal.
模拟量采集电路包括信号调理电路和模数转换芯片AD7606。信号调理电路的输入信号来自于电流霍尔传感器与差分式电压测量电路,信号调理电路输出与模数转换芯片AD7606的模拟信号输入端相连。霍尔传感器通常包括用于测量逆变器输出的三个电流传感器,采用分压电阻与运算放大器采用差分的方式对交流电压与直流母线电压进行采集。 The analog quantity acquisition circuit includes a signal conditioning circuit and an analog-to-digital conversion chip AD7606. The input signal of the signal conditioning circuit comes from the current Hall sensor and the differential voltage measurement circuit, and the output of the signal conditioning circuit is connected with the analog signal input terminal of the analog-to-digital conversion chip AD7606. The Hall sensor usually includes three current sensors used to measure the output of the inverter, and uses a voltage divider resistor and an operational amplifier to collect AC voltage and DC bus voltage in a differential manner.
IGBT驱动电路采用12个Infineon公司的1ED020I12磁隔离驱动芯片,驱动电路的输入与CPLD纠正后的PWM脉冲直接相连,经过磁隔离驱动的输出信号通过一个图腾柱推挽输出后与功率器件的门极相连。 The IGBT drive circuit uses 12 1ED020I12 magnetically isolated drive chips from Infineon Company. The input of the drive circuit is directly connected to the corrected PWM pulse of the CPLD. connected.
故障录波电路由USB接口电路、SD卡接口电路组成、USB接口控制芯片组成,采用南京沁恒电子的CH376芯片与USB和与DSP相连,DSP实时对采样数据进行刷新式存储,当故障发生时,将故障前后100mS的数据,可以通过USB接口芯片分别。 The fault recording circuit is composed of a USB interface circuit, an SD card interface circuit, and a USB interface control chip. The CH376 chip of Nanjing Qinheng Electronics is used to connect with the USB and DSP. The DSP refreshes and stores the sampled data in real time. , the data of 100mS before and after the fault can be separated through the USB interface chip.
CPLD采用Xilinx公司高性能CPLD芯片XC95288XL,该芯片具备5V输入能力,可用于外设与DSP之前电平转换;在该芯片上使用硬件描述语言VHDL实现DSP输出PWM脉冲检测与纠正、开入开出逻辑扩展、故障保护控制与数字滤波功能。 The CPLD adopts Xilinx's high-performance CPLD chip XC95288XL, which has 5V input capability and can be used for level conversion between peripherals and DSP; on this chip, the hardware description language VHDL is used to realize DSP output PWM pulse detection and correction, input and output Logic expansion, fail-safe control and digital filtering functions.
DSP采用TI公司TMS320F28346浮点DSP控制器作为主控制器芯片,完成三电平PWM脉冲控制逻辑、分压电容中性点平衡控制算法、通信控制、故障录波与电网电压锁相环与直流和交流双闭环控制算法。 The DSP uses TI's TMS320F28346 floating-point DSP controller as the main controller chip to complete the three-level PWM pulse control logic, the voltage-dividing capacitor neutral point balance control algorithm, communication control, fault recording and grid voltage phase-locked loop and DC and AC double closed-loop control algorithm.
CPLD对DSP输出的三电平控制脉冲进行检测,对于I型三电平电路,如果脉冲属于表1中的潜在风险状态或者损坏状态,则CPLD将脉冲进行更换后再输出到IGBT驱动板,并向DSP发出报警信号,以1000为例,如果CPLD检测到DSP输出的PWM脉冲是1000,CPLD将脉冲更新为0100;对于T型三电平电路,如果脉冲属于表2中的损坏状态,则CPLD将脉冲进行更换后再输出到IGBT驱动板,并向DSP发出报警信号,以1001为例,如果CPLD检测到DSP输出的PWM脉冲是1001,CPLD将脉冲更新为1000,以更换后,纠正的开关管状态最少作为脉冲修改准则。 The CPLD detects the three-level control pulse output by the DSP. For the I-type three-level circuit, if the pulse belongs to the potential risk state or damage state in Table 1, the CPLD will replace the pulse and then output it to the IGBT driver board, and Send an alarm signal to the DSP, taking 1000 as an example, if the CPLD detects that the PWM pulse output by the DSP is 1000, the CPLD will update the pulse to 0100; for the T-type three-level circuit, if the pulse belongs to the damaged state in Table 2, the CPLD Replace the pulse and then output it to the IGBT driver board, and send an alarm signal to the DSP. Take 1001 as an example. If the CPLD detects that the PWM pulse output by the DSP is 1001, the CPLD will update the pulse to 1000. After the replacement, correct the switch The tube state is the least used as the pulse modification criterion.
本发明的有益效果是:可以兼容T型和I型两种三电平拓扑架构,控制系统采用DSP与CPLD的控制架构,CPLD作为协处理器负责逻辑控制、三电平PWM信号检测与纠正功能等,提高了系统可靠性,减轻了DSP的预算负担。DSP作为主处理器负责复杂控制算法的实时运算,该控制系统可以运行复杂的并网控制程序,提高逆变器的实时性与稳定性,改善逆变系统的EMI特性,具有重要的实际应用意义。 The beneficial effects of the present invention are: it can be compatible with T-type and I-type three-level topological architectures, the control system adopts the control architecture of DSP and CPLD, and CPLD is responsible for logic control, three-level PWM signal detection and correction functions as a coprocessor Etc., improved system reliability, reduced the budgetary burden of DSP. As the main processor, DSP is responsible for the real-time calculation of complex control algorithms. This control system can run complex grid-connected control programs, improve the real-time performance and stability of the inverter, and improve the EMI characteristics of the inverter system, which has important practical application significance .
附图说明 Description of drawings
图1是本发明控制系统框图。 Fig. 1 is a block diagram of the control system of the present invention.
具体实施方式 detailed description
下面通过实施例,并结合附图1,对本发明的技术方案作进一步具体的说明。 The technical solution of the present invention will be further specifically described below through the embodiments and in conjunction with the accompanying drawing 1 .
一种I型与T型三电平双向PWM整流器控制系统,包括模拟量数据采集与调理电路、IGBT磁隔离驱动电路、DSP与CPLD组成的控制电路、继电器输出与数字信号输入、故障录波与远程通信,其特征在于霍尔传感器数据采集电路、IGBT驱动电路、开入开出接口电路与CPLD芯片相连,通信电路和故障录波电路与DSP相连,DSP与CPLD通过数据、地址总线、PWM输出信号与中断信号相连。 An I-type and T-type three-level bidirectional PWM rectifier control system, including analog data acquisition and conditioning circuit, IGBT magnetic isolation drive circuit, control circuit composed of DSP and CPLD, relay output and digital signal input, fault recording and Remote communication, characterized in that Hall sensor data acquisition circuit, IGBT drive circuit, input and output interface circuit are connected with CPLD chip, communication circuit and fault recording circuit are connected with DSP, and DSP and CPLD are output through data, address bus and PWM The signal is connected to the interrupt signal.
模拟量采集电路包括霍尔电流传感器输出调理电路、分压差分式电压采集调理电路和模数转换芯片AD7606组成。信号调理电路的输出与AD7606的模拟量输入接口相连,AD7606芯片将模拟信号转变成数字信号,并通过数据总线将采样数值输入DSP。 The analog quantity acquisition circuit consists of a Hall current sensor output conditioning circuit, a differential voltage acquisition and conditioning circuit and an analog-to-digital conversion chip AD7606. The output of the signal conditioning circuit is connected with the analog input interface of AD7606, and the AD7606 chip converts the analog signal into a digital signal, and inputs the sampled value into the DSP through the data bus.
DSP对采样数据进行零飘滤波算法和三相锁相环算法后,得到预处理的三相电网电压量、逆变器输出电流量、直流侧电压量及电网电压的相位信息,通过两个直流侧电压信息完成中性点平衡计算,DSP对三相电网电压传感器信息与逆变器输出电流传感器信息进行正负序解耦控制及有无功解耦控制,完成并网控制算法,得到包含幅值与相位信息的三相逆变器输出电压信号;该信号再经过SVPWM算法得到矢量扇区、小三角形区域、作用时间等数据;DSP利用自带的EPWM模块生成T型与I型三电平兼容的PWM信号。DSP输出的PWM信号经过通过CPLD的检测与修正电路后连接到IGBT磁隔离驱动电路。 After the DSP performs the zero-drift filtering algorithm and the three-phase phase-locked loop algorithm on the sampled data, the pre-processed three-phase grid voltage, inverter output current, DC side voltage, and phase information of the grid voltage are obtained. The side voltage information completes the neutral point balance calculation, and the DSP performs positive and negative sequence decoupling control and active and reactive power decoupling control on the three-phase grid voltage sensor information and the inverter output current sensor information, and completes the grid-connected control algorithm to obtain Value and phase information of the three-phase inverter output voltage signal; the signal is then subjected to the SVPWM algorithm to obtain vector sector, small triangle area, action time and other data; DSP uses the built-in EPWM module to generate T-type and I-type three-level compatible PWM signal. The PWM signal output by the DSP is connected to the IGBT magnetic isolation drive circuit after passing through the detection and correction circuit of the CPLD.
CPLD接收开入信号与故障信号输入并转换成两个16bit数据通过数据总线传送给DSP,CPLD对IGBT故障信号进行逻辑控制,通过IO口与DSP的中断接口连接。 The CPLD receives the switch-in signal and the fault signal input and converts them into two 16-bit data and transmits them to the DSP through the data bus. The CPLD performs logic control on the IGBT fault signal, and is connected to the interrupt interface of the DSP through the IO port.
在逆变器出现故障时,DSP通过故障录波电路可将故障发生前120s与后120s的电网电压波形,逆变器输出电流波形,逆变器控制系统中间变量等通过USB驱动电路分别写入到外置U盘和SD卡;并通过USB接口存储器将故障数据读取到上位机进行故障分析。 When the inverter fails, the DSP can write the grid voltage waveform 120s before and 120s after the fault, the inverter output current waveform, and the intermediate variables of the inverter control system through the USB drive circuit through the fault recording circuit. to the external U disk and SD card; and read the fault data to the host computer through the USB interface memory for fault analysis.
CPLD对DSP输出的三电平控制脉冲进行检测,对于I型三电平电路,如果脉冲属于表1中的潜在风险状态或者损坏状态,则CPLD将脉冲进行更换后再输出到IGBT驱动板,并向DSP发出报警信号,以1000为例,如果CPLD检测到DSP输出的PWM脉冲是1000,CPLD将脉冲更新为0100;对于T型三电平电路,如果脉冲属于表2中的损坏状态,则CPLD将脉冲进行更换后再输出到IGBT驱动板,并向DSP发出报警信号,以1001为例,如果CPLD检测到DSP输出的PWM脉冲是1001,CPLD将脉冲更新为1000,以更换后,纠正的开关管状态最少作为脉冲修改准则。 The CPLD detects the three-level control pulse output by the DSP. For the I-type three-level circuit, if the pulse belongs to the potential risk state or damage state in Table 1, the CPLD will replace the pulse and then output it to the IGBT driver board, and Send an alarm signal to the DSP, taking 1000 as an example, if the CPLD detects that the PWM pulse output by the DSP is 1000, the CPLD will update the pulse to 0100; for the T-type three-level circuit, if the pulse belongs to the damaged state in Table 2, the CPLD Replace the pulse and then output it to the IGBT driver board, and send an alarm signal to the DSP. Take 1001 as an example. If the CPLD detects that the PWM pulse output by the DSP is 1001, the CPLD will update the pulse to 1000. After the replacement, correct the switch The tube state is the least used as the pulse modification criterion.
本实施例只是本发明示例的实施方式,对于本领域内的技术人员而言,在本发明公开了应用方法和原理的基础上,很容易做出各种类型的改进或变形,而不仅限于本发明上述具体实施方式所描述的方法或结构,因此前面描述的方式只是优选方案,而并不具有限制性的意义,凡是依本发明所作的等效变化与修改,都在本发明权利要求书的范围保护范围内。 This embodiment is only an exemplary embodiment of the present invention. For those skilled in the art, on the basis of the application methods and principles disclosed in the present invention, it is easy to make various types of improvements or deformations, and is not limited to this embodiment. Inventing the method or structure described in the above-mentioned specific embodiment, so the above-described method is only a preferred solution, and does not have a restrictive meaning. All equivalent changes and modifications made according to the present invention are included in the claims of the present invention. within the scope of protection.
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CN108646165A (en) * | 2018-04-12 | 2018-10-12 | 武汉能研电气有限公司 | A kind of method, system and controller improving Technics of Power Electronic Conversion equipment safety |
CN109842319A (en) * | 2019-02-22 | 2019-06-04 | 哈尔滨理工大学 | A kind of high-power charge-discharge system circuit topological structure and control method |
CN109842319B (en) * | 2019-02-22 | 2020-11-03 | 哈尔滨理工大学 | Circuit topology and control method of a high-power charging and discharging system |
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