CN204046171U - A kind of active power filter control system of modularization parallel processing - Google Patents

Abstract

The utility model discloses a kind of active power filter control system of modularization parallel processing, comprise display, master board, first from control board, second from control board, the 3rd from control board, voltage sensor and current sensor, described master board is connected with display, voltage sensor, current sensor respectively, and master board also respectively with first, second, third to be connected from control board.The utility model is all threephase load for industrial occasions, utilize the high-speed parallel disposal ability of FPGA, implementation three-phase modular controls, parallel detection and process are carried out to three phase harmonic electric current, reduce computing cycle, increase harmonic detecting number of times in certain hour, improve accuracy of detection, meet various loading demand.

Description

A kind of active power filter control system of modularization parallel processing

Technical field

The utility model discloses a kind of active power filter control system of modularization parallel processing, be specifically related to a kind of harmonic wave extraction algorithm, belong to Automation of Electric Systems product and Power Quality Detection control technology field thereof.

Background technology

Active Power Filter-APF (APF) is as a kind of power electronic equipment of dynamic harmonic inhabitation electric current and extensive concern.The compensation performance of APF is good and bad has much relations with its control algolithm adopted.

Traditional detection logic is A phase, B phase, C phase detect in order respectively, then output current in order, and this just causes the computation delay in processor calculating process, causes computational efficiency low, and have impact on the real-time of result.

Traditional algorithm time cost conventional in prior art is larger, and detection speed is low, and overall harmonic track effect is also undesirable.Based on the control method of the modularization parallel processing of FPGA, more save time than traditional algorithm, therefore improve detection speed, improve overall harmonic track effect.

Utility model content

Technical problem to be solved in the utility model is: for the defect of prior art, a kind of active power filter control system of modularization parallel processing is provided, more flexibly, modular, harmonic compensation way faster, better adaptation electrical network and various load characteristic, the harmonic current in compensation network electric current.

The utility model is for solving the problems of the technologies described above by the following technical solutions:

A kind of active power filter control system of modularization parallel processing, comprise display, master board, first from control board, second from control board, the 3rd from control board, voltage sensor and current sensor, described master board is connected with display, voltage sensor, current sensor respectively, and master board also respectively with first, second, third to be connected from control board, described master board is provided with master controller, specifically comprise: data acquisition module, the phase-locked module of line voltage, DFT controller, three-phase sliding window DFT module, three-phase reference current generation module and communication interface, described voltage sensor is connected with data acquisition module respectively with current sensor, data acquisition module is the phase-locked module with line voltage respectively, DFT controller is connected, DFT controller is connected with three-phase sliding window DFT module respectively, what three-phase sliding window DFT module was corresponding in turn to is connected with three-phase reference current generation module, three-phase reference current generation module is connected with communication interface respectively, described master controller is used for realizing that mains by harmonics and idle detection, line voltage are phase-locked, current reference generation, electric current and voltage controller, drive singal produce and hardware lockout drive singal.

Described first, second, 3rd is provided with from controller from control board, specifically comprise: from controller data acquisition module, from controller communication interface, Voltage loop controller, current loop controller, protection module and modulation module, describedly to be connected from controller data acquisition module with voltage sensor, from controller data acquisition module also successively with Voltage loop controller, current loop controller, modulation module is connected, described protection module is also connected with modulation module, output respectively with three Single-phase SPWM modules of modulation module are connected, describedly to be connected from controller communication interface with the communication interface master board, also be connected with modulation module through current loop controller from controller communication interface, described from controller for realizing controlling opening and turning off and the adhesive of relay and release of power device.

As further preferred version of the present utility model, the phase-locked module of described line voltage comprises four inputs and two outputs, described input connects the overall situation respectively and controls clock, global reset signal, the digital signal of three-phase voltage and external interface module, and described output connects the running status output port of Output rusults port and this module current respectively.

As further preferred version of the present utility model, described three-phase sliding window DFT module comprises six inputs and three outputs, described input connects the overall situation respectively and controls clock, overall reset signal, the input of load-side electric current, sliding window DFT Data Update, RAM interface between MCU and hardware interface, and described output connects sliding window DFT end mark position respectively, the amplitude of k subharmonic exports, the angle values output of k subharmonic.

As further preferred version of the present utility model, described three-phase reference current generation module is harmonic and reactive detection controller, specifically comprise seven inputs and three outputs, described input connects overall situation control clock, overall reset signal, the amplitude input of k subharmonic respectively, the angle values of k subharmonic inputs, the phase angle of phase-locked loop output, the benchmark of DC bus export, harmonic synthesizer sign on input, and described output connects the Irefn_H output of harmonic synthesizer end of synthesis flag bit, composition algorithm generation respectively.

As further preferred version of the present utility model, described from the Voltage loop controller control board be voltage PID controller, specifically comprise four inputs and two outputs, described input connects the overall situation respectively and controls clock, overall reset signal, the reference voltage input of dc-link capacitance, DC capacitor voltage input, and described output connects the output terminating algorithm flag bit, voltage pid algorithm respectively.

As further preferred version of the present utility model, described from the current loop controller control board be electric current PID controller, specifically comprise five inputs and two outputs, described input connects that the overall situation controls clock, overall reset signal, harmonic and reactive detection input, three-phase tri-level output current sampled value input, current PI D calculate opening flag position respectively, and described output connects the output of end algorithm flag bit, current PI D-algorithm respectively.

As further preferred version of the present utility model; described Single-phase SPWM module comprises five inputs and an output; described input connects the overall situation respectively and controls clock, overall reset signal, the input of single phase current regulator, the state signal input terminal of adjuster, guard signal input, and described output connects drive singal output.

The utility model adopts above technical scheme compared with prior art, all threephase load for industrial occasions, utilize the high-speed parallel disposal ability of FPGA, implementation three-phase modular controls, parallel detection and process are carried out to three phase harmonic electric current, reduce computing cycle, increase harmonic detecting number of times in certain hour, improve accuracy of detection, meet various loading demand.The utility model has following technique effect:

1) modularization APF, module is furnished with one from controller, and module main circuit is H bridge; Separate between each APF module, facilitate capacity extensions; Can be easy to realize parallel connection, series connection etc.;

2) centralized control; Each mutually separate, controlled modules by master controller, system reliability is high;

3) hot plug is supported; Each independently APF can be connected to the grid in real time and depart from electrical network;

4) often have " single-phase " APF that separate mutually, be furnished with a controller for each single-phase APF, the controller of three-phase carries out centralized control by centralized master controllers;

5) adopt FPGA high speed processor, high-speed AD dress changes chip, improves detection speed and current tracking performance, improves filter filter characteristics.

Accompanying drawing explanation

Fig. 1 is overall system block schematic illustration.

Fig. 2 is master controller theory diagram.

Fig. 3 is line voltage phase-locked loop module.

Fig. 4 is line voltage phase-locked loop module sequential chart.

Fig. 5 is sliding window DFT schematic diagram.

Fig. 6 is DFT sequential chart.

Fig. 7 is harmonic and reactive detection controller principle figure.

Fig. 8 is harmonic and reactive detection sequential chart.

Fig. 9 is from controller principle block diagram.

Figure 10 is voltage PID schematic diagram.

Figure 11 is voltage PID sequential chart.

Figure 12 is current PI D schematic diagram.

Figure 13 is current PI D sequential chart.

Figure 14 is Single-phase SPWM module.

Figure 15 is SPWM modulation timing figure.

Embodiment

Be described below in detail execution mode of the present utility model, the example of described execution mode is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the execution mode be described with reference to the drawings, only for explaining the utility model, and can not being interpreted as restriction of the present utility model.

Those skilled in the art of the present technique are understandable that, the correlation module related in the utility model and the function of realization thereof are the devices of hardware after improvement and formation thereof, device or system carry computer software programs conventional in prior art or pertinent protocols just can realize, and are not improve computer software programs of the prior art or pertinent protocols.Such as, the computer hardware system after improvement still can realize the specific function of this hardware system by loading existing operation system of software.Therefore, be understandable that, innovation of the present utility model is the improvement of hardware module in prior art and connects syntagmatic, but not be only in hardware module for realizing the improvement of software or the agreement of carrying about function.

Those skilled in the art of the present technique are understandable that, the correlation module mentioned in the utility model is the one or more hardware device for performing in step in operation, method, flow process described in the application, measure, scheme.Described hardware device for required object and specialized designs and manufacture, or also can adopt the known device in all-purpose computer or other known hardware devices.Described all-purpose computer activates or reconstructs with having storage procedure Selection within it.

Those skilled in the art of the present technique are appreciated that unless expressly stated, and singulative used herein " ", " one ", " described " and " being somebody's turn to do " also can comprise plural form.Should be further understood that, the wording used in specification of the present utility model " comprises " and refers to there is described feature, integer, step, operation, element and/or assembly, but does not get rid of and exist or add other features one or more, integer, step, operation, element, assembly and/or their group.Should be appreciated that, when we claim element to be " connected " or " coupling " to another element time, it can be directly connected or coupled to other elements, or also can there is intermediary element.In addition, " connection " used herein or " coupling " can comprise wireless connections or couple.Wording "and/or" used herein comprises one or more arbitrary unit listing item be associated and all combinations.

Those skilled in the art of the present technique are appreciated that unless otherwise defined, and all terms used herein (comprising technical term and scientific terminology) have the meaning identical with the general understanding of the those of ordinary skill in field belonging to the utility model.Should also be understood that those terms defined in such as general dictionary should be understood to have the meaning consistent with the meaning in the context of prior art, unless and define as here, can not explain by idealized or too formal implication.

Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail:

As shown in Figure 1, the master and slave core controller of FPGA is the core of whole control section to overall system block schematic illustration, and practical function needed for it comprises computational load harmonic wave and idle, APF compensating current control, system protection function, user interface interaction.

As shown in Figure 2, master controller realizes core algorithm to master controller theory diagram, the hardware implementing directly configured by FPGA, to reduce time delay; This module realizes the Core Feature of APF, comprises that mains by harmonics and idle detection, line voltage are phase-locked, current reference produces.Executed in parallel between each little module in this hardware module, intermodule has suitable communication interface.Master controller is the digitial controller based on FPGA, and its hardware module mainly comprises data acquisition module, the phase-locked module of line voltage, sliding window DFT module, reference current generation module, communication interface etc.

In Fig. 2, ea, eb, ec are three-phase power grid voltage, and iLa, iLb, iLc are threephase load electric current; Two kinds of signals are after data acquisition module, and three-phase power grid voltage exports phase-locked module to, are used for calculating grid voltage phase-angle, for harmonic wave provides phase angle foundation; Threephase load electric current, exports DFT controller, sliding window to, exports three phase harmonic electric current as reference current;

Master controller is when harmonic detecting, and carry out three-phase parallel processing, to detect 3 subharmonic, traditional detection logic is A phase, B phase, C phase detect in order respectively, then output current in order; And in the utility model, utilize the powerful parallel processing capability of FPGA, the detection calculations while that A phase, B phase, C phase being carried out, Output rusults is also parallel output, avoid the computation delay in processor calculating process, improve computational efficiency, and improve the real-time of result.

Line voltage phase-locked loop module in main controller module, as shown in Figure 3, Gclk is that the overall situation controls clock, U _datait is the digital signal of the three-phase voltage from external interface module; This signal and Re_PLL are the interfaces of this module and external interface module, are used for controlling external sample-rate and sequential, read sampled result.Reset is global reset signal, the soft core of its MCU from FPGA.The Output rusults of line voltage phase-locked loop module and the running status of this module current with Flag_PLL; They are and need the module of grid phase information to be connected, and Fig. 4 gives the sequential chart of this module.

Sliding window DFT function in main controller module is first-harmonic and the harmonic spectrum of computational load side electric current, for harmonic and reactive detection module provides amplitude and the phase angle information of each harmonic wave and fundamental current.Sliding window DFT module is according to following algorithm:

If the n-1 moment, sliding window choose N number of sample x (n-N), x (n-N+1) ..., x (n-2), x (n-1); At moment n, sliding window choose N number of sample for x (n-N+1), x (n-N+2) ..., x (n-2), x (n-1), x (n); In the n-1 moment, the kth spectrum unit of N point DFT and in the n moment, the pass of a kth spectrum unit of N point is:

$X_{k+1}=e^{j2\mathrm{\π}\frac{k}{N}}\{X_k(n-1)+x\left(n\right)-x(n-N)\}.$

Fig. 5 is sliding window DFT module diagram, and DFT_Datan is load-side current input value, and subscript represents a, b, c phase, the amplitude that In (k) is k subharmonic and X _k+1corresponding amplitude, the phase angle that θ n (k) is k subharmonic and X _k+1corresponding angle values, subscript represents the number of selected harmonic, and R_DFT notifies that sliding window DFT data upgrade for higher level, need to carry out sliding window DFT algorithm, Flag_DFT is sliding window DFT end mark position, is used for pointing out sliding window DFT to terminate, and Reset is clear 0 signal of the overall situation.Flag_re and Conf is and the interface of RAM between MCU and hardware interface, is used for the number of times of configuration extraction harmonic wave, and sequential chart is as Fig. 6.

By sliding window DFT algorithm process above, out be an amplitude and phase angle, so need to carry out synthesis to produce benchmark, be used for the use of rear class, Fig. 7 is harmonic and reactive detection controller, and it has amplitude and phase angle input pin, is used for connecting amplitude and phase angle input that sliding window DFT produces; For the phase angle that phase-locked loop exports; Udc_pi is the benchmark that DC bus exports; Produce Irefn_H by composition algorithm to export; Flag_DFT for higher level notify harmonic synthesizer start synthesis; Flagn_H is harmonic synthesizer end of synthesis flag bit; Reset is clear 0 signal of the overall situation; Fig. 8 is the sequential chart of harmonic synthesizer.After harmonic and reactive detection, produce harmonic wave Setting signal, by communication module, export to from controller, by the current tracking completed from controller given harmonic wave, and the turn-on and turn-off of driving power switching tube carry out output current control.

From the theory diagram of controller as shown in Figure 9, mainly comprise data acquisition from controller, Voltage loop controller, current loop controller, drive singal produce with hardware lockout drive singal, modulation, protection and communicate; Three-phase is from controlling to adopt same control method, difference is that input is different with given harmonic current from the line voltage of controller, and other are all identical, and this is also one of the utility model main feature, be exactly modularization, this module turns to dilatation and parallel operation provides great aspect.

Be voltage PID controller from the voltage controller controller, as shown in Figure 10, sequential chart as shown in figure 11; Uref is the reference voltage of dc-link capacitance; Uin is DC capacitor voltage; Flag_Upi is for terminating algorithm flag bit; Upi is the output of voltage pid algorithm, it be used for rear class control required for signal; Reset is clear 0 signal of the overall situation.

Current controller is also electric current PID controller, and as shown in Figure 12,13, Irefn_H is harmonic and reactive detection output; IL_Datan is three-phase tri-level output current sampled value; Flagn_H notifies current PI D calculation flag position for higher level; Flagn_Ipi is for terminating algorithm flag bit; Ipi_n is the output of current PI D-algorithm, it be used for rear class modulation required for signal; Reset is clear 0 signal of the overall situation.

Single-phase SPWM module be used for producing main circuit switch pipe drive singal, realize guard signal and block.Figure 14 is Single-phase SPWM module in FPGA, exports and has 4 road drive singal, and input has 3 road signals.Gclk is system clock, and Reset is clear 0 signal of the overall situation; I _pithe output of single phase current regulator, Flag_I _pithe status signal of adjuster, I _piand Flag_I _piconnect with current regulator module.Reset is global reset signal; Protect is signal respectively.V _gatebe 4 road output drive signals, be connected with external drive plate.Figure 15 gives the exemplary timing diagram of this module.One phase of each Single-phase SPWM module controls Active Power Filter-APF, achieves three-phase and independently controls, non-interfering object.

In Fig. 9, Udc is the DC voltage that external voltage transducer detects, and controls for the Voltage loop from control board module; The data of communication interface are input as main controller module, the signals such as the harmonic wave come up by the optical fiber communication transmission of 50M is given, phase angle, for from the current compensation of control module and tracking loop; Guard signal is the output signal after external module detects unit exception, after control module receives guard signal, at once carry out safeguard measure process; PWMa PWMb PWMc, relay control signal be output signal from controller, for controlling opening and turning off and the adhesive of relay and release of power device.

By reference to the accompanying drawings execution mode of the present utility model is explained in detail above, but the utility model is not limited to above-mentioned execution mode, in the ken that those of ordinary skill in the art possess, can also make a variety of changes under the prerequisite not departing from the utility model aim.The above, it is only preferred embodiment of the present utility model, not any pro forma restriction is done to the utility model, although the utility model discloses as above with preferred embodiment, but and be not used to limit the utility model, any those skilled in the art, do not departing within the scope of technical solutions of the utility model, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solutions of the utility model content, according to technical spirit of the present utility model, within spirit of the present utility model and principle, to any simple amendment that above embodiment is done, equivalent replacement and improvement etc., within the protection range all still belonging to technical solutions of the utility model.

Claims (7)

1. the active power filter control system of a modularization parallel processing, it is characterized in that: comprise display, master board, first from control board, second from control board, the 3rd from control board, voltage sensor and current sensor, described master board is connected with display, voltage sensor, current sensor respectively, and master board also respectively with first, second, third to be connected from control board;

Described master board is provided with master controller, specifically comprise: data acquisition module, the phase-locked module of line voltage, DFT controller, three-phase sliding window DFT module, three-phase reference current generation module and communication interface, described voltage sensor is connected with data acquisition module respectively with current sensor, data acquisition module is the phase-locked module with line voltage respectively, DFT controller is connected, DFT controller is connected with three-phase sliding window DFT module respectively, what three-phase sliding window DFT module was corresponding in turn to is connected with three-phase reference current generation module, three-phase reference current generation module is connected with communication interface respectively,

Described first, second, 3rd is provided with from controller from control board, specifically comprise: from controller data acquisition module, from controller communication interface, Voltage loop controller, current loop controller, drive singal produces and hardware lockout drive singal, protection module and modulation module, describedly to be connected from controller data acquisition module with voltage sensor, from controller data acquisition module also successively with Voltage loop controller, current loop controller, modulation module is connected, described protection module is also connected with modulation module, output respectively with three Single-phase SPWM modules of modulation module are connected, describedly to be connected from controller communication interface with the communication interface master board, also be connected with modulation module through current loop controller from controller communication interface.

2. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1, it is characterized in that: the phase-locked module of described line voltage comprises four inputs and two outputs, described input connects the overall situation respectively and controls clock, global reset signal, the digital signal of three-phase voltage and external interface module, and described output connects the running status output port of Output rusults port and this module current respectively.

3. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1, it is characterized in that: described three-phase sliding window DFT module comprises six inputs and three outputs, described input connects the overall situation respectively and controls clock, overall reset signal, the input of load-side electric current, sliding window DFT Data Update, RAM interface between MCU and hardware interface, and described output connects sliding window DFT end mark position respectively, the amplitude of k subharmonic exports, the angle values output of k subharmonic.

4. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1, it is characterized in that: described three-phase reference current generation module is harmonic and reactive detection controller, specifically comprise seven inputs and three outputs, described input connects the overall situation respectively and controls clock, overall situation reset signal, the amplitude input of k subharmonic, the angle values input of k subharmonic, the phase angle that phase-locked loop exports, the benchmark of DC bus exports, harmonic synthesizer sign on input, described output connects harmonic synthesizer end of synthesis flag bit respectively, composition algorithm produces irefn_Houtput.

5. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1, it is characterized in that: described from the Voltage loop controller control board be voltage PID controller, specifically comprise four inputs and two outputs, described input connects the overall situation respectively and controls clock, overall reset signal, the reference voltage input of dc-link capacitance, DC capacitor voltage input, and described output connects the output terminating algorithm flag bit, voltage pid algorithm respectively.

6. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1, it is characterized in that: described from the current loop controller control board be electric current PID controller, specifically comprise five inputs and two outputs, described input connects that the overall situation controls clock, overall reset signal, harmonic and reactive detection input, three-phase tri-level output current sampled value input, current PI D calculate opening flag position respectively, and described output connects the output of end algorithm flag bit, current PI D-algorithm respectively.

7. the active power filter control system of a kind of modularization parallel processing as claimed in claim 1; it is characterized in that: described Single-phase SPWM module comprises five inputs and an output; described input connects the overall situation respectively and controls clock, overall reset signal, the input of single phase current regulator, the state signal input terminal of adjuster, guard signal input, and described output connects drive singal output.