CN101625705A - Verification environment system and construction method thereof - Google Patents

Abstract

The embodiment of the present invention discloses a verification environment system and its construction method, wherein the construction method of the verification environment includes: obtaining the port information required to build the verification environment, generating a hierarchical structure of the verification environment; The required components of the hierarchical structure of the verification environment are built layer by layer in the direction of anti-configuration data flow. The implementation of the present invention can realize the effective reuse and rapid construction of the verification environment.

Description

Verify the environment system and its construction method

technical field

The invention relates to the technical field of verification, in particular to a verification environment system and a construction method thereof.

Background technique

Verification is an indispensable process in the chip product development process to prove whether the design function is realized and implemented correctly. In order to better complete the verification, the verification personnel need to often build an appropriate and efficient verification environment around the design. With the rapid development of the field of chip verification in the past 20 years, there are various methods to build the verification environment. At present, it is more commonly used in the industry to build around the top-level simulation. The purpose of building around the top-level simulation is to generate a verification environment that just satisfies the design under test (DUT, DesignUnder Test) based on the top-level simulation information. It has the advantages of simplicity and flexibility.

To build around the top layer of the simulation, the functional modules and control modules required by the environment are usually prepared in advance, and then they are uniformly instantiated and connected in the top layer of the simulation to complete the construction of the entire verification environment. This method solves the problem of combining with the characteristics of the verification business, makes the verification more targeted, is good at finding design loopholes, and has a relatively simple structure and flexible control.

The main idea of building a verification environment around the top-level simulation is based on the top-level simulation, which uniformly defines the required signals, instantiates the DUT top-level modules, writes and instantiates the required functional timing modules or verification IP (VIP, Verification Intellectual Property, verify the reused parts) module, and finally complete the connection and debugging of signals between modules. The process of building the verification environment around the top layer of the simulation is shown in Figure 1 below.

The characteristics of building a verification environment around the top layer of simulation are:

1. According to the call direction, the generation of sequential layer components depends on the encapsulation layer and functional layer;

2. Each functional timing module or verification IP module and DUT are uniformly instantiated in the simulation top layer, and they have the same status;

3. The relationship between each functional timing module or verification IP module and DUT is all reflected in the simulation top layer;

4. The verification components and reference models in the encapsulation layer and functional layer are hidden under each functional timing module or verification IP module, and are invisible to the top layer of simulation;

5. There is no unified construction main line and automated construction ideas, and it needs to rely too much on manual editing by verifiers, but subsequent modifications are more convenient.

During the creation process of the present invention, the inventor found that with the increasing complexity of chip business, the method of building a verification environment around the simulation top layer provided by the prior art has some disadvantages:

The method provided by the existing technology to build a verification environment around the simulation top layer requires verification personnel to invest more and more energy and time in verification management and development of related functional modules. Because the method of building the verification environment around the top layer of the simulation focuses all the focus on the top layer of the simulation, and relies too much on the manual work of the verification personnel. At the same time, it also gives the verification personnel a lot of randomness outside the top layer of the simulation, so it is easy to cause each DUT. There is no communication and reuse between verification environments, and many human errors. If there are many top-level functional modules in the simulation, the workload for the verification personnel will also increase exponentially. With the rapid expansion of the existing chip verification scale, the continuous reduction of its development cycle and the continuous improvement of verification quality requirements, the method of building around the top layer of simulation cannot fully satisfy us to quickly build a verification environment that is appropriate to product characteristics.

Contents of the invention

The embodiment of the present invention provides a method for building a verification environment and a verification environment system, which can realize effective reuse and rapid construction of the verification environment.

In order to solve the above problems, an embodiment of the present invention provides a method for building a verification environment, including:

Obtain the port information needed to build the verification environment, and generate a hierarchical structure in the verification environment starting from the top level of the design under test

According to the port signals originating from the top layer of the design under test, the required components of the hierarchical structure of the verification environment are built layer by layer in the direction of the reverse configuration flow.

Correspondingly, the embodiment of the present invention also provides a verification environment system. The system uses port signals originating from the top layer of the design under test, and is built layer by layer in the direction of anti-configuration flow, including:

The top layer of the design under test obtains the port information required to build the verification environment, and converts the obtained port information into port signals that can be recognized by the verification environment; the verification environment starts with the top layer of the design under test after being named after the top layer of the design under test The hierarchical structure; the port signals are grouped and delivered;

The simulation top layer is generated according to the port signals of the grouped and packaged top-level module of the design under test with the same name, and the instantiation of the components required for the verification environment hierarchical structure is completed in it;

The timing interface layer is used to generate the code file of the bus function model and the monitoring function module in the manner with the same name as the port signal of the simulation top layer, and connect the verification IP according to the bus function model and the port signal of the monitoring function module module or signal configuration module;

The encapsulation layer encapsulates the relevant information of the bus function model and the standard interface signal in the port signal of the monitoring function module in commands and functions, for the user to pass the commands and functions, and verify that the IP module has a correct understanding of the bus function. Control or process the port signals in the model and monitoring function modules;

In the functional layer, the self-defined interface signals of the bus function model and the port signals of the monitoring function module exist in the configuration use case of the signal configuration module with the same name, so that the user can directly configure the use case.

Implementing the embodiments of the present invention has the following beneficial effects:

The verification environment system and its construction method provided by the embodiments of the present invention are based on the DUT top-level port information and the verification IP module, and advance in layers in the direction of anti-configuration data flow, and gradually and quickly establish each component required in the verification environment , until the use case is configured, the effective reuse and rapid construction of the verification environment are realized.

Description of drawings

Figure 1 is a schematic diagram of the process of building a verification environment around the simulation top layer in the prior art;

Fig. 2 is a schematic flowchart of the first embodiment of the verification environment construction method provided by the embodiment of the present invention;

Fig. 3 is a schematic flowchart of the second embodiment of the verification environment construction method provided by the embodiment of the present invention;

Fig. 4 is a schematic structural diagram of a verification environment system provided by an embodiment of the present invention.

Detailed ways

The embodiment of the present invention provides a method for building a verification environment and a verification environment system. Through the port information at the top layer of the DUT, the construction instructions are transmitted in the direction of the reverse configuration flow, so as to realize the signal-based functional layering and effective reuse of environmental components, and Reduce the gap between design and verification.

Referring to FIG. 2 , it is a schematic flowchart of the first embodiment of the verification environment building method provided by the embodiment of the present invention.

In step 100, the top layer of the design under test obtains externally provided port information;

In step 101, the obtained port information is converted into a port signal that can be recognized by the verification environment;

In step 102, according to the port signal, a hierarchical structure starting from the top layer of the design under test in the verification environment is generated;

In step 103, the simulation top layer is generated and defined in a manner having the same name as the port signal of the top layer of the design under test, and the instantiation of components required for verifying the hierarchical structure of the environment is completed within the simulation top layer; specifically, in the simulation top layer Complete the instantiation of the top layer of the design under test, the bus function model, the monitoring function module, and the clock/reset signal generation module.

In step 104, generate the code file of the bus function model and the monitoring function module at the sequential interface layer with the same name as the port signal of the simulation top layer;

In step 105, according to the standard interface signal in the port signal of described bus functional model and monitoring function module, connect corresponding verification IP (VIP, Verification Intellectual Property, verification reuse part) module; Specifically, comprise step 1050, step 1051 , step 1052:

In step 1050, according to the standard interface signal of the bus function model and the port signal of the monitoring function module, the verification IP module of the bus function model and the verification IP module of the monitoring function module are connected, and the standard interface signal is terminated at the timing interface layer;

In step 1051, the relevant information of the standard interface signal is delivered to the encapsulation layer, and encapsulated in corresponding commands and functions;

In step 1052, call the command or function, and control or process the port signals in the bus function model and the monitoring function module through the verification IP module of the bus function model and the verification IP module of the monitoring function module;

In step 106, according to the bus function model and the self-defined interface signal in the port signal of the monitoring function module, connect the corresponding signal configuration module. Specifically, steps 1060 and 1061 are included:

In step 1060, according to the self-defining interface signal in the bus function model and the self-defining interface signal in the non-DUT port signal of the monitoring function module, connect the signal configuration module generated in the manner of the same name; and through the respective signal configuration module passed into the configuration use case.

In step 1061, the self-defined interface signal continues to be transmitted to the functional layer along the port signal flow direction, and exists in the configuration use case of the signal configuration module with the same name, for the user to directly configure the use case. The use case configuration means that the user directly performs parameter configuration or scene configuration on the configuration signal transmitted to the use case.

The verification environment construction method provided by the embodiment of the present invention is based on the top-level port information of the DUT and the verification IP module, and advances hierarchically in the direction of the anti-configuration data flow, and gradually and quickly establishes various components required in the verification environment until Configure use cases to realize the effective reuse and rapid construction of the verification environment.

Fig. 3 is a schematic flowchart of the second embodiment of the verification environment construction method provided by the embodiment of the present invention;

The method for building the verification environment based on the DUT top layer provided by the embodiment of the present invention uses the DUT top layer port signal information as a data flow, which is gradually transmitted and gradually decreased (each port signal is terminated on the corresponding layer), until the port signal is Zero, the process is opposite to the direction of configuring the data flow, and the specific implementation process is described in detail below.

In step 200, the top layer of the DUT obtains externally provided port information, specifically: all information on the top layer of the DUT that is different from other environments, through automatic processing, obtains the port information required to build the verification environment, and manages it effectively. There are usually the following types of management categories (the following categories are for reference only, designers can add according to specific usage, but the method is the same):

1. Clock and reset signal;

2. Input non-standard protocol signals;

3. Input standard protocol signal;

4. Output non-standard protocol signals;

5. Output standard protocol signal.

In step 201, the simulation top layer is generated and defined in the manner of the same name as the port signal of the top layer of the tested design packaged by grouping, and the instantiation of the components required for the verification environment hierarchical structure is completed in the simulation top layer; it can be based on The port information obtained by the top layer of the DUT generates and defines the port signals of the simulation top layer, the bus function module (BFM, Bus Function Model) and the monitoring function module (Monitor) with the same name as the DUT top layer port signal, and determines the top layer of the simulation The instantiation of each module (DUT, BFM, Monitor, clock/reset signal generation module) is completed within the module.

In step 202, generate the code file of the bus function model and the monitoring function module at the sequential interface layer with the same name as the port signal of the simulation top layer; it can be based on the port information of the simulation top layer, with the same name as the simulation top layer signal , respectively automatically generate BFM and Monitor code files at the timing interface layer. It should be noted that the code files of the BFM and Monitor are actually used to process the output information of the DUT, and the output information includes the processing of the output signal and the output signal, such as connecting the output signal of the DUT to the standard output data Verify the IP module, or merge, split or convert the data or enable of the output signal, that is, send the data of the DUT output signal to the encapsulation layer for processing.

The input signal of the top layer of the simulation is the output signal of the BFM. Correspondingly, the output signal of the top layer of the simulation is the input signal of the Monitor (note: the clock, reset and output feedback signals are all used as the input signals of the BFM and the Monitor), and all configurations are It comes from the BFM, after being output by the BFM to the top layer of the simulation, it passes through the top layer of the DUT, and then output to the Monitor by the top layer of the simulation. .

It should be noted that the BFM and Monitor port signals can be divided into standard protocol interface signals and user-defined interface signals according to their functional significance. The standard protocol signal is automatically connected to the VIP module and ends here; while the custom interface signal is automatically connected to the signal configuration module with the same name and continues to be passed down.

In step 203, the DUT interface signal terminated at the timing interface layer transmits related information to the encapsulation layer, and finally the encapsulation layer processes it. At the encapsulation layer, the DUT port signals terminated at the timing interface layer are embodied in encapsulated commands or functions, and the verifier applies control or incentives to the DUT port signals terminated at the timing interface layer by executing related commands or functions, Provides input to the verification DUT.

In step 204, the DUT top-level interface signals (non-standard interface signals, clock, reset and related control variable signals) that are not terminated in the sequential interface layer are directly passed to the functional layer through the signal configuration module, and exist in the configuration use case with the same name , the user only needs to configure it directly; for the CPU interface signal of the standard protocol, the platform needs to additionally manage the register information of the DUT and reflect it in the configuration use case.

It should be noted that the CPU not only needs to provide commands and functions in the standard package, but also needs to have objects to operate on. The register information of the DUT is the object of the encapsulation layer operation. Through automatic processing, the encapsulated commands and functions can recognize these register information, and let this information be reflected in the configuration use case.

The following procedures illustrate the process of building the above-mentioned verification environment:

a. For a DUT top-level aaa module, it obtains the port information required to build a verification environment from the outside.

module aaa(...)//reset and clock signal input clk_sys; input rst_n;//input control signal (non-standard protocol interface signal) input a;//input standard protocol interface signal input d;//output control signal (non-standard protocol interface signal) Standard protocol interface signal)

output b;//output standard protocol interface signal output c;...endmodule

b. Generate the simulation top layer from the DUT top layer aaa with the same name.

module harness ()//reset and clock signal wire clk_sys; wire rst_n;//input control signal (non-standard protocol interface signal) wire a;//input standard protocol interface signal wire d;//output control signal wire b;/ /Output standard protocol interface signal wire c; aaa U_aaa(...); //DUT input signal continues to pass down through BFM BFM U_BFM(//input.clk_sys (clk_sys), .rst_n (rst_n), //output.a (a), .d (d)

);//DUT input signal continues to pass down through Moniotr Monitor U_Monitor(//input.clk_sys (clk_sys), .rst_n (rst_n), .b (b), .c (c));//Reset clock function The module is automatically connected, and the DUT reset and clock signal information is passed to the parameter configuration use case rst_clk U_rst_clk(//output.clk_sys (clk_sys), .rst_n (rst_n)); endmodule

c. Generate BFM and Monitor with the same name from the simulation.

BFM

module BFM(...)//reset and clock signal input clk_sys; input rst_n;//input control signal (non-standard protocol interface signal) input a;//input standard protocol interface signal input d;//each function with standard signal The timing modules are correspondingly connected, and the standard signals terminate here, but

Its relevant information is passed to the relevant control layer through the functional module, and combined with the register information to achieve the configuration use case. cpu_function U_cpu_function(//input.clk_sys (clk_sys), .rst_n (rst_n), //output.d (d)); // Correspondingly connected to the non-standard signal configuration function timing module, the non-standard signal is passed to the Relevant control layer, to achieve the configuration use case. signal_cfg U_signal_cfg(//input.clk_sys (clk_sys), .rst_n (rst_n), //output.a (a)...);...endmodule

Monitor

module Moniotr (...)//reset and clock signal input clk_sys; input rst_n;//input control signal (non-standard protocol signal) input b;

//Output the standard protocol interface signal input c;//Connect to the assertion monitoring function module correspondingly, and pass the relevant information to the relevant processing program through the assertion monitoring function module. The role of the assertion monitoring function module here is to monitor the timing of the relevant signals received by the monitoring function module. assert_function U_assert_function(//input.clk_sys (clk_sys).rst_n (rst_n).b (b), .c (c)); // Correspondingly connected to each sampling function module or verification IP module, the signal terminates here, but related The information is passed to the handler through the sampling function block or the verification IP block. sample_function U_sample_function(//input.clk_sys (clk_sys).rst_n (rst_n).b (b), .c (c));...endmodule

The verification environment construction method provided by the embodiment of the present invention is based on the top-level port information of the DUT and the verification IP module, and advances hierarchically in the direction of the anti-configuration data flow, and gradually and quickly establishes various components required in the verification environment until Configure use cases to realize the effective reuse and rapid construction of the verification environment.

Referring to FIG. 4 , it is a schematic structural diagram of a verification environment system provided by an embodiment of the present invention.

The verification environment system is built layer by layer in the direction of anti-configuration data flow based on port signals originating from the top layer of the design under test, including:

The top layer of the design under test 1, obtains the port information required to build the verification environment, and converts the obtained port information into a port signal that the verification environment can recognize; it is named after the top layer of the design under test to generate the top layer of the design under test in the verification environment The initial layered structure; the port signals are grouped and packaged and transmitted; it should be noted that, at the top layer 1 of the DUT, there are all information different from other environments, and the embodiment of the present invention obtains the layered structure of the verification environment through automatic processing. The required port information and manage it effectively.

Simulation top level 2 is generated according to the same name of the port signals of the top level 1 modules of the design under test that are grouped and packaged, and the instantiation of components required for the hierarchical structure of the verification environment is completed in it; specifically, according to the port obtained from the top level of the DUT Information, with the same name as the DUT top-level port signal, generate and define the port signals of the simulation top-level, bus function module 210 (BFM, Bus Function Model) and monitoring function module 211 (Monitor), and complete each module in the simulation top-level (DUT, BFM, Monitor, clock/reset signal generation module) instantiation.

The timing interface layer 3 is used for the mode with the same name as the port signal of the simulation top layer 2, in which the code files of the bus function model 210 and the monitoring function module 211 are generated, and according to the bus function model 210 and the monitoring function module 211 The port signal is connected to the verification IP module or the signal configuration module; specifically, the port signals of the BFM210 and Monitor211 can be divided into standard protocol interface signals and custom interface signals according to the functional significance. The standard protocol signal is automatically connected to the VIP module and ends here; while the custom interface signal is automatically connected to the signal configuration module with the same name and continues to be passed down.

The encapsulation layer 4 encapsulates the relevant information of the standard interface signal in the port signal of the bus function model 210 and the monitoring function module 211 into corresponding commands and functions, so that the user can pass the commands and functions to verify the IP module's The port signals in the bus function model 210 and the monitoring function module 211 are controlled or processed;

In the functional layer 5, the self-defined interface signals of the bus function model 210 and the port signals of the monitoring function module 211 exist in the configuration use case of the signal configuration module with the same name, so that the user can directly configure the use case.

Referring to FIG. 5 , it is a schematic structural diagram of the top layer of the design under test in the verification environment system shown in FIG. 4 provided by an embodiment of the present invention;

The top level 1 of the design under test consists of:

A signal receiving module 10, configured to acquire externally provided port information;

The signal processing module 11 is used to convert the port information obtained by the signal receiving module into port signals that can be recognized by the verification environment, and to generate a layer starting from the top layer of the design under test in the verification environment named after the top layer 1 of the design under test Structure; It should be noted that the hierarchical structure of the verification environment generated by the name of the top-level 1 of the design under test can be distinguished from other environments;

The signal sending module 12 is used to send the port signals processed by the signal processing module to the simulation top layer after grouping and packaging. It should be noted that the port signal of the top layer 1 of the design under test is used to generate the configuration signal variables and component interface signals in the hierarchical structure of the verification environment with the same name, which is easy to identify the verification environment and has good readability and maintainability and portability.

Referring to FIG. 6, it is a schematic structural diagram of the simulation top layer in the verification environment system shown in FIG. 4 provided by an embodiment of the present invention;

The simulation top level 2 includes:

The signal receiving module 20 is used to receive the port signal packaged by grouping sent by the top-level signal sending module of the design under test;

Component generation module 21 generates and defines the components needed for the hierarchical structure such as the timing interface layer, packaging layer and functional layer of the verification environment with the same name as the top-level port signal of the design under test; the components generated and defined by the component generation module 21 Parts include:

The bus function module 210 is used to transmit the port signals of the hierarchical structure of the verification environment;

A monitoring function module 211, configured to manage and control various information in the hierarchical structure of the verification environment;

The component instantiation module 22 is used to complete the instantiation of the components required for the hierarchical structure such as the timing interface layer, the encapsulation layer and the functional layer; specifically, in the simulation top layer 2, complete the top layer 1 of the design under test, the bus Instantiation of the function module 210, the monitoring function module 211, and the clock/reset signal generation module;

The signal sending module 23 is configured to send the signal processed by the simulation top layer to the timing interface layer.

Referring to FIG. 7, it is a schematic structural diagram of the timing interface layer in the verification environment system shown in FIG. 4 provided by an embodiment of the present invention;

The timing interface layer 3 includes:

The signal receiving module 30 is used to receive the port signals of the bus function model 210 and the monitoring function module 211 sent by the signal sending module 20 of the simulation top layer 2;

The code generating module 31 is used to generate the code files of the bus function module 210 and the monitoring function module 211 in a manner with the same name as the port signal of the simulation top layer 2; it should be noted that the bus function module 210 and the monitoring function module 211 code file is actually used to process the DUT output information, the DUT output information includes the processing of the input signal and the output signal, such as connecting the output signal of the DUT to the standard output data VIP module, or processing the output signal The data can be merged, split or converted, that is, the data output by the DUT is sent to the encapsulation layer for processing.

The signal processing module 32 is used to connect the corresponding verification IP module according to the standard interface signal in the port signal of the bus function model 210 and the monitoring function module 211; according to the self-defined interface signal and the monitoring function module of the bus function model The user-defined interface signal in the non-DUT port signal is connected to the corresponding signal configuration module;

The signal sending module 33 sends the related information of the standard interface signal to the encapsulation layer 4 ; sends the user-defined interface signal to the functional layer 5 .

Referring to FIG. 8 , it is a schematic structural diagram of the encapsulation layer in the verification environment system shown in FIG. 4 provided by an embodiment of the present invention;

Described encapsulation layer 4 comprises:

The signal receiving module 40 is used to receive the relevant information of the standard interface signal sent by the signal sending module 32 of the timing interface layer 3;

An encapsulation module 41, configured to encapsulate relevant information of the standard interface signal in corresponding commands and functions;

The verification module 42 invokes the command or function to control or process the port signals in the bus function model 210 and the monitoring function module 211 through the verification IP module of the bus function model and the verification IP module of the monitoring function module. It should be noted that, for the standard interface signals of the DUT, the platform also needs to additionally manage the register information of the DUT, which is reflected in the configuration use case.

Referring to FIG. 9, it is a schematic structural diagram of the functional layer in the verification environment system shown in FIG. 4 provided by an embodiment of the present invention;

The functional layer 5 includes:

The signal receiving module 50 is used to receive the self-defined interface signal sent by the signal sending module 32 of the timing interface layer 3;

The signal configuration module 51 is configured to store the self-defined interface signal with the same name in the configuration use case of the signal configuration module for the user to configure the use case.

The verification environment system provided by the embodiment of the present invention is based on the top-level port information of the DUT and the verification IP module, and advances hierarchically in the direction of anti-configuration data flow, and gradually and quickly establishes each component required in the verification environment until the configuration use case , to realize the effective reuse and rapid construction of the verification environment, and its beneficial effects are as follows:

1. Based on objective information and resources, with automatic control and management, a verification environment suitable for the product can be quickly built, and the verification IP module can also be effectively reused;

2. Since this technology uses DUT top-level port information to generate corresponding components, variables and signals have a unified definition, coupled with automatic control and relative management, the readability, maintainability and portability of the environment are very good. At the same time, designers and verification personnel are unified in the variable naming of DUT signals, and there is a large space for communication in environmental use, and the use gap (such as configuration) has been greatly reduced, and the efficiency has been improved;

3. Depending on the automatic construction of the top layer of the DUT, with the unified test of the control process, the verification personnel do not need to invest too much energy in the subsequent construction and debugging, which reduces the investment in resources during the construction of the verification environment;

4. It greatly reduces human manual operations, so that there are no too many human factors in the environment, the probability of error is extremely small, and with the increase of interface signals, the workload cannot be reflected;

5. The structure and form are unified at all levels, and the environmental quality can be guaranteed uniformly, which is also conducive to the development of review activities.

Through the above description of the implementation manners, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus a necessary hardware platform, and of course can also be implemented entirely by hardware. Based on this understanding, all or part of the contribution made by the technical solution of the present invention to the background technology can be embodied in the form of software products, and the computer software products can be stored in storage media, such as ROM/RAM, magnetic disks, optical disks, etc. , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute the methods described in various embodiments or some parts of the embodiments of the present invention.

The above disclosure is only a preferred embodiment of the present invention, which certainly cannot limit the scope of rights of the present invention. Therefore, equivalent changes made according to the claims of the present invention still fall within the scope of the present invention.

Claims (13)

1, a kind of building method of verification environment is characterized in that, comprising:

Obtain and build the required port information of verification environment, produce the hierarchy that begins with tested design top layer in the verification environment;

According to the port signal that is derived from tested design top layer, successively build the required parts of verification environment hierarchy with the direction of anti-configuration data stream.

2, the building method of verification environment as claimed in claim 1 is characterized in that, obtains the port information of building the required tested design top layer of verification environment, produces the hierarchy of verification environment, comprising:

Obtain the port information that the outside provides by tested design top layer;

The port information that is obtained is converted into the port signal that verification environment can be discerned;

Name nominating with tested design top layer produces the hierarchy that begins with tested design top layer in the verification environment.

3, the building method of verification environment as claimed in claim 1 is characterized in that, according to the port signal that is derived from tested design top layer, successively builds the required parts of verification environment hierarchy with the direction of anti-configuration data stream, comprising:

The port signal of tested design top layer is divided into groups to pack and transmit,, produce also definition emulation top layer, in described emulation top layer, finish the exampleization of the required parts of hierarchy of verification environment in the mode of the same name with the port signal of tested design top layer;

In the mode of the same name, produce the code file of bus functional model and monitoring function module at the sequential interface layer with the port signal of described emulation top layer;

According to the standard interface signal in the port signal of described bus functional model and monitoring function module, connect corresponding checking IP module;

According to the self defined interface signal in the port signal of described bus functional model and monitoring function module, connect corresponding signal configures module.

4, the building method of verification environment as claimed in claim 3 is characterized in that, finishes the exampleization of the required parts of verification environment hierarchy in described emulation top layer, comprising:

In described emulation top layer, finish the exampleization of tested design top layer, bus functional model, monitoring function module, clock/reset signal generation module.

5, the building method of verification environment as claimed in claim 3 is characterized in that, according to the standard interface signal in the port signal of described bus functional model and monitoring function module, connects corresponding checking IP module, comprising:

According to the standard interface signal of the port signal of described bus functional model and monitoring function module, the checking IP module of the checking IP module of connecting bus functional mode and monitoring function module, described standard interface signal terminates in described sequential interface layer;

The relevant information of described standard interface signal is delivered to encapsulated layer, and is encapsulated in corresponding order and the function;

Call described order or function,, described port signal in bus functional model and monitoring function module is controlled or handled by the checking IP module of described bus functional model and the checking IP module of monitoring function module.

6, the building method of verification environment as claimed in claim 3 is characterized in that, according to the self defined interface signal in the port signal of described bus functional model and monitoring function module, connects corresponding signal configures module, comprising:

According to the self defined interface signal in the port signal of described bus functional model and monitoring function module, connect the signal configures module that produces in mode of the same name;

Described self defined interface signal continues to be delivered to functional layer along the direction of port signal stream, and is present in the described signal configures modules configured use-case in mode of the same name, directly carries out the use-case configuration for the user.

7, a kind of verification environment system is characterized in that, to be derived from the port signal of tested design top layer, successively builds the required parts of verification environment with the direction of anti-configuration data stream, comprising:

Tested design top layer obtains and builds the required port information of verification environment, and the port information that is obtained is converted into the port signal that verification environment can be discerned; Name nominating with tested design top layer produces the hierarchy that begins with tested design top layer in the verification environment; Port signal is divided into groups to pack and transmit;

The emulation top layer according to the port signal generation of the same name of the top-level module of the tested design that is grouped packing, and is finished the exampleization of the required parts of verification environment hierarchy therein;

The sequential interface layer, be used for the mode of the same name with the port signal of described emulation top layer, produce the code file of bus functional model and monitoring function module therein, and according to the port signal of described bus functional model and monitoring function module, connectivity verification IP module or signal configures module;

Encapsulated layer, the relevant information of the standard interface signal in the port signal of described bus functional model and monitoring function module is encapsulated in order and the function,, described port signal in bus functional model and monitoring function module is controlled or handled by described order and function for the user by checking IP module;

Functional layer is present in the self defined interface signal in the port signal of bus functional model and monitoring function module in the described signal configures modules configured use-case in mode of the same name, directly carries out the use-case configuration for the user.

8, verification environment system as claimed in claim 7 is characterized in that, described tested design top layer comprises:

Signal receiving module is used to obtain the port information that the outside provides;

Signal processing module, the port information that is used for that signal receiving module is obtained are converted into the port signal that verification environment can be discerned, and produce the hierarchy that begins with tested design top layer in the verification environment with the name nominating of tested design top layer;

Signal transmitting module after being used for will dividing into groups through the port signal that signal processing module is handled to pack, sends to the emulation top layer.

9, verification environment system as claimed in claim 7 is characterized in that, described emulation top layer comprises:

Signal receiving module is used to receive the port signal that is grouped packing that is sent from tested design top layer signals sending module;

The parts generation module produces and defines the required parts of sequential interface layer, encapsulated layer and functional layer in the verification environment in the top level ports signal of tested design mode of the same name;

Parts exampleization module is used to finish the exampleization to described sequential interface layer, encapsulated layer and the required parts of functional layer;

Signal transmitting module, the signal that is used for handling through the emulation top layer is sent to the sequential interface layer.

10, verification environment system as claimed in claim 7 is characterized in that, the parts that described parts generation module produces and defines comprise:

The bus functionality module is used for transmitting the port signal of verification environment;

The monitoring function module is used for the various information of verification environment are managed and control.

11, verification environment system as claimed in claim 10 is characterized in that, described sequential interface layer comprises:

Signal receiving module is used to receive the described bus functional model that emulation top layer signals sending module sent and the port signal of monitoring function module;

Code generation module is used to generate the code file of bus functionality module and monitoring function module;

Signal processing module is used for the standard interface signal according to the port signal of described bus functional model and monitoring function module, connects corresponding checking IP module; According to the self defined interface signal in the port signal of described bus functional model and monitoring function module, connect corresponding signal configures module;

Signal transmitting module is sent to encapsulated layer with the relevant information of described standard interface signal; Described self defined interface signal is sent to functional layer.

12, verification environment system as claimed in claim 11 is characterized in that, described encapsulated layer comprises:

Signal receiving module is used to receive the relevant information of the standard interface signal that the sequential interface layer sent;

Package module is used for the relevant information of described standard interface signal is encapsulated in corresponding order and function;

Authentication module calls described order or function, by the checking IP module of described bus functional model and the checking IP module of monitoring function module, the port signal in bus functional model and the monitoring function module is controlled or is handled.

13, verification environment system as claimed in claim 11 is characterized in that, described functional layer comprises:

Signal receiving module is used to receive the self defined interface signal that the sequential interface layer is sent;

The signal configures module is used for described self defined interface signal is present in described signal configures modules configured use-case in mode of the same name, carries out the use-case configuration for the user.

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