CN101625705A - Verification environment system and construction method thereof - Google Patents
Verification environment system and construction method thereof Download PDFInfo
- Publication number
- CN101625705A CN101625705A CN200810029309A CN200810029309A CN101625705A CN 101625705 A CN101625705 A CN 101625705A CN 200810029309 A CN200810029309 A CN 200810029309A CN 200810029309 A CN200810029309 A CN 200810029309A CN 101625705 A CN101625705 A CN 101625705A
- Authority
- CN
- China
- Prior art keywords
- signal
- module
- verification environment
- top layer
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Small-Scale Networks (AREA)
Abstract
The embodiment of the invention discloses a verification environment system and a construction method thereof. The construction method of a verification environment comprises the following steps: acquiring port information required by the construction of the verification environment and generating a layered structure of the verification environment; and constructing, layer by layer, parts required by the layered structure of the verification environment in a direction opposite to configured data stream according to port signals from a tested designed top layer. The verification environment system and the construction method thereof can realize effective reuse and fast construction of the verification environment.
Description
Technical field
The present invention relates to the verification technique field, relate in particular to a kind of verification environment system and building method thereof.
Background technology
Checking is a requisite process in order to prove whether design function is realized and correctly realize in the chip product exploitation link, and in order to finish checking better, and the checking personnel often need to build appropriateness, verification environment efficiently around design.Along with the fast development in chip checking field over nearly 20 years, verification environment built various methods.At present in the industry cycle relatively more commonly used is to build around the emulation top layer, is in order to produce the verification environment of being satisfied with this tested design (DUT, DesignUnder Test) just according to the emulation top layer information around the emulation top layer, has simple and advantage flexibly.
Build around the emulation top layer, usually each functional module and the control module of environment needs are ready in advance, in the emulation top layer, unify exampleization then and be connected them, to finish building of whole verification environment.This mode has solved the problem that combines with the checking business characteristic well, makes that checking is pointed, is good at finding the design leak, and structure is also fairly simple, controls also flexible.
The main thought of building verification environment around the emulation top layer is to be basis with the emulation top layer, within it the needed signal of portion's unified Definition, exampleization DUT top-level module, write and needed each function tfi module of exampleization or checking IP (VIP, Verification Intellectual Property, parts are reused in checking) module, and finally finish the connection and the debugging of each intermodule signal.Verification environment build process around the emulation top layer is illustrated in fig. 1 shown below.
The characteristics of building verification environment around the emulation top layer are:
1, by call direction, the generation of sequential layer parts depends on encapsulated layer and functional layer;
2, by unified exampleization, they have equal status in the emulation top layer for each function tfi module or checking IP module and DUT;
3, the relation between each function tfi module or checking IP module and the DUT all is embodied in the emulation top layer;
4, each verification component and reference model are hidden under each function tfi module or the checking IP module in encapsulated layer, the functional layer, are sightless for the emulation top layer;
5, the ununified thought of building of building main line and robotization need depend on checking personnel's manual editing too much, but that subsequent modification gets up is more convenient.
The inventor finds the continuous increase along with the professional complexity of chip in creation process of the present invention, the mode of building verification environment around the emulation top layer that prior art provides is just like shortcoming:
The mode of building verification environment around the emulation top layer that prior art provides need the checking personnel drops into increasing energy and time and carries out verification management, and the relevant functional module of exploitation.Owing to build the mode of verification environment around the emulation top layer all focuses have all been concentrated on the emulation top layer, and too rely on checking personnel's manual work, simultaneously outside the emulation top layer, also given the checking personnel a lot of randomness, so cause easily between each DUT verification environment and can't exchange and reuse, and mistake of a lot of artificial property.If emulation top-level functionality module is many, for the checking personnel workload also will be doubled and redoubled.Enlarge rapidly in existing chip checking scale, and its construction cycle constantly reduction and checking quality requirements improve constantly etc. under the situation, can not satisfy our fast construction appropriateness fully in the verification environment of products characteristics around the emulation top layer mode of building.
Summary of the invention
The embodiment of the invention provides a kind of building method of verification environment, and verification environment system, can realize effectively reusing and fast construction of verification environment.
For addressing the above problem, the embodiment of the invention provides a kind of building method of verification environment, comprising:
Obtain and build the required port information of verification environment, produce the hierarchy that begins with tested design top layer in the verification environment
According to the port signal that is derived from tested design top layer, successively build the required parts of hierarchy of verification environment with the direction of anti-configuration flow.
Accordingly, the embodiment of the invention also provides a kind of verification environment system, and described system successively builds with the direction of anti-configuration flow to be derived from the port signal of tested design top layer, comprising:
Tested design top layer obtains and builds the required port information of verification environment, and the port information that is obtained is converted into the port signal that verification environment can be discerned; Name nominating with tested design top layer produces the hierarchy that begins with tested design top layer in the verification environment; Port signal is divided into groups to pack and transmit;
The emulation top layer according to the port signal generation of the same name of the tested design top-level module that is grouped packing, and is finished the exampleization of the required parts of verification environment hierarchy therein;
The sequential interface layer, be used for the mode of the same name with the port signal of described emulation top layer, produce the code file of bus functional model and monitoring function module therein, and according to the port signal of described bus functional model and monitoring function module, connectivity verification IP module or signal configures module;
Encapsulated layer, the relevant information of the standard interface signal in the port signal of described bus functional model and monitoring function module is encapsulated in order and the function,, described port signal in bus functional model and monitoring function module is controlled or handled by described order and function for the user by checking IP module;
Functional layer is present in the self defined interface signal in the port signal of bus functional model and monitoring function module in the described signal configures modules configured use-case in mode of the same name, directly carries out the use-case configuration for the user.
Implement embodiments of the invention, have following beneficial effect:
Verification environment system that the embodiment of the invention provides and building method thereof, be on the basis of DUT top level ports information and checking IP module, advance with anti-configuration data flow path direction layering, progressively, set up each parts that need in the verification environment apace, until the configuration use-case, realized effectively reusing and fast construction of verification environment.
Description of drawings
Fig. 1 is the verification environment build process synoptic diagram that prior art centers on the emulation top layer;
Fig. 2 is the schematic flow sheet of verification environment building method first embodiment that provides of the embodiment of the invention;
Fig. 3 is the schematic flow sheet of verification environment building method second embodiment that provides of the embodiment of the invention;
Fig. 4 is the structural representation of the verification environment system that provides of the embodiment of the invention.
Embodiment
The embodiment of the invention provides a kind of building method of verification environment, and verification environment system, by the port information of DUT top layer, build instruction with the direction transmission of anti-configuration flow, realize the environment parts based on the functional stratification of signal with effectively reuse, and reduce design and verify between estrangement.
Referring to Fig. 2, the schematic flow sheet of verification environment building method first embodiment that provides for the embodiment of the invention.
In step 100, tested design top layer obtains the port information that the outside provides;
In step 101, the port information that is obtained is converted into the port signal that verification environment can be discerned;
In step 102,, produce the hierarchy that begins with tested design top layer in the verification environment according to described port signal;
In step 103, in the mode of the same name, produce and definition emulation top layer with the port signal of tested design top layer, in described emulation top layer, finish the exampleization of the required parts of verification environment hierarchy; Particularly, in described emulation top layer, finish the exampleization of tested design top layer, bus functional model, monitoring function module, clock/reset signal generation module.
In step 104,, produce the code file of bus functional model and monitoring function module at the sequential interface layer in the mode of the same name with the port signal of described emulation top layer;
In step 105,, connect corresponding checking IP (parts are reused in checking for VIP, Verification Intellectual Property) module according to the standard interface signal in the port signal of described bus functional model and monitoring function module; Particularly, comprise step 1050, step 1051, step 1052:
In step 1050, standard interface signal according to the port signal of described bus functional model and monitoring function module, the checking IP module of the checking IP module of connecting bus functional mode and monitoring function module, described standard interface signal terminates in described sequential interface layer;
In step 1051, the relevant information of described standard interface signal is delivered to encapsulated layer, and is encapsulated in corresponding order and the function;
In step 1052, call described order or function, by the checking IP module of described bus functional model and the checking IP module of monitoring function module, the port signal in bus functional model and the monitoring function module is controlled or handled;
In step 106,, connect corresponding signal configures module according to the self defined interface signal in the port signal of described bus functional model and monitoring function module.Particularly, comprise step 1060, step 1061:
In step 1060,, connect the signal configures module that produces in mode of the same name according to the self defined interface signal in the non-DUT port signal of self defined interface signal in the described bus functional model and monitoring function module; And be delivered in the configuration use-case by signal configures module separately.
In step 1061, described self defined interface signal continues to be delivered to functional layer along the direction of port signal stream, and is present in the described signal configures modules configured use-case in mode of the same name, directly carries out the use-case configuration for the user.Described use-case configuration is meant that the user directly to being delivered to the configuration signal of use-case, carries out parameter configuration or scene configuration.
The building method of the verification environment that the embodiment of the invention provides, be on the basis of DUT top level ports information and checking IP module, advance with anti-configuration data flow path direction layering, progressively, set up each parts that need in the verification environment apace, until the configuration use-case, realized effectively reusing and fast construction of verification environment.
Fig. 3 is the schematic flow sheet of verification environment building method second embodiment that provides of the embodiment of the invention;
The building method that the embodiment of the invention provides based on the verification environment of DUT top layer, be to be data stream with DUT top level ports signal message, progressively transmit, progressively successively decrease (each port signal is terminated transmission on corresponding layer), till port signal is zero, its process is opposite with the direction of configuration data stream, and the specific implementation process as detailed below.
In step 200, tested design top layer obtains port information that the outside provides specifically: have any different in all information of other environment at the DUT top layer, handle by robotization, obtain and build the needed port information of verification environment, and manage effectively.Management category has following several (following classification is only for reference, and the deviser can increase according to concrete operating position, but method is the same) usually:
One, clock, reset signal;
Two, input nonstandard protocol signal;
Three, input standard agreement signal;
Four, output nonstandard protocol signal;
Five, outputting standard protocol signal.
In step 201, with the port signal mode of the same name of the tested design top layer that is grouped packing, produce also definition emulation top layer, in described emulation top layer, finish the exampleization of the required parts of verification environment hierarchy; Can be for according to the port information that gets access to from the DUT top layer, with with DUT top level ports signal mode of the same name, produce and define emulation top layer, bus functionality module (BFM, and in top layer is decided in emulation, finish the exampleization of each module (DUT, BFM, Monitor, clock/reset signal generation module) Bus Function Model) and the port signal of monitoring function module (Monitor).
In step 202,, produce the code file of bus functional model and monitoring function module at the sequential interface layer in the mode of the same name with the port signal of described emulation top layer; Port information be can be,, BFM and Monitor code file automatically produced respectively at the sequential interface layer in the mode of the same name with the emulation top layer signals according to the emulation top layer.Need to prove, the code file of described BFM and Monitor is actually and is used for handling DUT output information, described output information comprises the processing to output signal and output signal, be connected to the output data checking IP module of standard such as output signal with DUT, perhaps to the data of output signal or enable to merge, operations such as partition or conversion are promptly delivered to encapsulated layer to the data of DUT output signal and are handled.
The input signal of emulation top layer is the output signal of BFM, correspondingly, the output signal of emulation top layer be Monitor input signal (annotate: clock, reset and output feedback signal all as the input signal of BFM and Monitor), all configurations all derive from BFM, after exporting to the emulation top layer by BFM, through the DUT top layer, export to Monitor by the emulation top layer again.。
Need to prove that BFM and Monitor port signal according to functional meaning, can be divided into standard protocol interface signal and self defined interface signal.The standard agreement signal links to each other with the VIP module automatically, and ends in this; The self defined interface signal then links to each other in mode of the same name with the signal configures module automatically, and continues down to transmit.
In step 203, the DUT interface signal in described sequential interface layer termination passes to encapsulated layer with relevant information, is finally handled by encapsulated layer.At encapsulated layer, the DUT port signal that ends in the sequential interface layer is embodied in the packaged order or function, the checking personnel come to apply control or excitation to the described DUT port signal that ends in the sequential interface layer by carrying out relevant order or function, and DUT provides input to checking.
In step 204, the DUT top layer interface signal (non-standard interface signal, clock, reset and relevant control variable signal) that does not end at the sequential interface layer is directly delivered to functional layer by the signal configures module, and be present in the configuration use-case in mode of the same name, the user only needs directly to its configuration; And, need the register information of this DUT of platform additional management, and be embodied in the configuration use-case for the cpu i/f signal of standard agreement.
Need to prove that CPU not only needs to provide order and the function in the standard packaging, also need the object of operation.The register information of DUT is exactly the object of encapsulated layer operation, handles by robotization, can be so that the order and the function of encapsulation be familiar with these register informations, and allow these imformosomes dispose in the use-case now.
Below by program the build process of above-mentioned verification environment is described:
A, for a DUT top layer aaa module, it has obtained from the outside builds the required port information of verification environment.
| Module aaa (...) // reset and clock signal input clk_sys; Input rst_n; // input control signal (nonstandard protocol interface signal) input a; // input standard protocol interface signal input d; // output control signal (nonstandard protocol interface signal) |
| Output b; // outputting standard protocol interface signal output c; Endmodule |
B, by DUT top layer aaa generation emulation of the same name top layer.
| Module harness () // reset and clock signal wire clk_sys; Wire rst_n; // input control signal (nonstandard protocol interface signal) wire a; // input standard protocol interface signal wire d; // output control signal wire b; // outputting standard protocol interface signal wire c; Aaa U_aaa (...); //DUT input signal by BFM continue down to transmit BFM U_BFM (//input .clk_sys (clk_sys), .rst_n (rst_n), //output .a (a) .d (d) |
| ); //DUT input signal by Moniotr continue down to transmit Monitor U_Monitor (//input .clk_sys (clk_sys), .rst_n (rst_n), .b (b) .c (c)); // link to each other automatically with the reset clock functional module, DUT resets and clock information signal is delivered to parameter configuration use-case rst_clk U_rst_clk (//output .clk_sys (clk_sys) .rst_n (rst_n)) by this module; Endmodule |
C, by emulation generation of the same name BFM and Monitor.
BFM
| Module BFM (...) // reset and clock signal input clk_sys; Input rst_n; // input control signal (nonstandard protocol interface signal) input a; // input standard protocol interface signal input d; // link to each other corresponding with each function tfi module of standard signal, standard signal ends at this, but |
| Its relevant information is delivered to relevant key-course by this functional module, and in conjunction with register information, reaches the configuration use-case.Cpu_function U_cpu_function (//input .clk_sys (clk_sys), .rst_n (rst_n), //output .d (d)); // link to each other corresponding with non-standard signal configuration feature tfi module, non-standard signal is delivered to relevant key-course by this functional module, reaches the configuration use-case.signal_cfg?U_signal_cfg( //input .clk_sys (clk_sys)， .rst_n (rst_n)， //output .a (a) …… )； …… endmodule |
Monitor
| Module Moniotr (...) // reset and clock signal input clk_sys; Input rst_n; // input control signal (nonstandard protocol signal) input b; |
| // outputting standard protocol interface signal input c; // with assert that the monitoring function module is corresponding and link to each other, by asserting that the monitoring function module is delivered to relevant handling procedure with relevant information.The effect of monitoring function module of asserting here is that the coherent signal that the monitoring function module receives is carried out the sequential monitoring.Assert_function U_assert_function (//input .clk_sys (clk_sys) .rst_n (rst_n) .b (b) .c (c)); // corresponding continuous with each sampling functional module or checking IP module, signal terminating is in this, but relevant information is delivered to handling procedure by sampling functional module or checking IP module.sample_function?U_sample_function( //input .clk_sys (clk_sys) .rst_n (rst_n) .b (b)， .c (c) )； …… endmodule |
The building method of the verification environment that the embodiment of the invention provides, be on the basis of DUT top level ports information and checking IP module, advance with anti-configuration data flow path direction layering, progressively, set up each parts that need in the verification environment apace, until the configuration use-case, realized effectively reusing and fast construction of verification environment.
Referring to Fig. 4, be the structural representation of the verification environment system that provides of the embodiment of the invention.
Described verification environment system is being derived from the port signal of tested design top layer, successively builds with the direction of anti-configuration data stream, comprising:
Tested design top layer 1 obtains and builds the required port information of verification environment, and the port information that is obtained is converted into the port signal that verification environment can be discerned; Name nominating with tested design top layer produces the hierarchy that begins with tested design top layer in the verification environment; Port signal is divided into groups to pack and transmit; Need to prove that have any different in all information of other environment at DUT top layer 1, the embodiment of the invention is handled by robotization, obtains the needed port information of the hierarchy of building verification environment, and manages effectively.
Emulation top layer 2 according to the port signal generation of the same name of top layer 1 module of the tested design that is grouped packing, and is finished the exampleization of the required parts of hierarchy of verification environment therein; Particularly, according to the port information that gets access to from the DUT top layer, with with DUT top level ports signal mode of the same name, produce and define emulation top layer, bus functionality module 210 (BFM, and in top layer is decided in emulation, finish the exampleization of each module (DUT, BFM, Monitor, clock/reset signal generation module) Bus Function Model) and the port signal of monitoring function module 211 (Monitor).
Encapsulated layer 4, the relevant information of the standard interface signal in the port signal of described bus functional model 210 and monitoring function module 211 is encapsulated in corresponding order and the function,, described port signal in bus functional model 210 and monitoring function module 211 is controlled or handled by described order and function for the user by checking IP module;
Referring to Fig. 5, the structural representation of tested design top layer in the verification environment system as shown in Figure 4 that provides for the embodiment of the invention;
Described tested design top layer 1 comprises:
Signal receiving module 10 is used to obtain the port information that the outside provides;
Signal transmitting module 12 after being used for will dividing into groups through the port signal that signal processing module is handled to pack, sends to the emulation top layer.Need to prove that the port signal of tested design top layer 1 is used for each configuration signal variable and unit interface signal in the hierarchy of generation verification environment of the same name, is convenient to like this discern this verification environment, and good readability, maintainability and transplantability are arranged.
Referring to Fig. 6, the structural representation of emulation top layer in the verification environment system as shown in Figure 4 that provides for the embodiment of the invention;
Described emulation top layer 2 comprises:
Signal receiving module 20 is used to receive the port signal that is grouped packing that is sent from tested design top layer signals sending module;
Parts exampleization module 22 is used to finish the exampleization to described sequential interface layer, encapsulated layer and the required parts of functional layer hierarchical structure; Particularly, in emulation top layer 2, finish bus functionality module 210, monitoring function module 211, and the exampleization of clock/reset signal generation module to tested design top layer 1;
Signal transmitting module 23, the signal that is used for handling through the emulation top layer is sent to the sequential interface layer.
Referring to Fig. 7, the structural representation of sequential interface layer in the verification environment system as shown in Figure 4 that provides for the embodiment of the invention;
Described sequential interface layer 3 comprises:
Signal receiving module 30 is used to receive the described bus functional model 210 that the signal transmitting module 20 of emulation top layer 2 sent and the port signal of monitoring function module 211;
Signal transmitting module 33 is sent to encapsulated layer 4 with the relevant information of described standard interface signal; Described self defined interface signal is sent to functional layer 5.
Referring to Fig. 8, the structural representation of encapsulated layer in the verification environment system as shown in Figure 4 that provides for the embodiment of the invention;
Described encapsulated layer 4 comprises:
Signal receiving module 40 is used to receive the relevant information of the standard interface signal that the signal transmitting module 32 of sequential interface layer 3 sent;
Referring to Fig. 9, the structural representation of functional layer in the verification environment system as shown in Figure 4 that provides for the embodiment of the invention;
Described functional layer 5 comprises:
Signal receiving module 50 is used to receive the self defined interface signal that the signal transmitting module 32 of sequential interface layer 3 is sent;
Signal configures module 51 is used for described self defined interface signal is present in described signal configures modules configured use-case in mode of the same name, carries out the use-case configuration for the user.
The verification environment system that the embodiment of the invention provides, be on the basis of DUT top level ports information and checking IP module, advance with anti-configuration data flow path direction layering, progressively, set up each parts that need in the verification environment apace, until the configuration use-case, realize effectively reusing and fast construction of verification environment, its beneficial effect is as follows:
1, based on objective information and resource, rely on robotization control and management, can build the verification environment of proper product apace, checking IP module also can effectively be reused;
2, because this technology has adopted DUT top level ports information to produce corresponding parts, and variable and signal have had uniform definition, add robotization control and relative management, make that readability, maintainability and the transplantability of environment are all very good.Simultaneously, designer and checking personnel are unified in the variable name of DUT signal, have very big communication space on environment uses, and use estrangement (such as configuration) to have significantly and reduce, and efficient gets a promotion;
3, the robotization of depending on the DUT top layer is built, and the unified test of control procedure has been arranged, and the checking personnel are follow-up not to be needed to drop into too much energy and build and debug, and has reduced the input of resource in the verification environment build process;
4, reduced the manual operation of artificial property in large quantities, made not have too much human factor in the environment, error probability is minimum, and along with the increasing of interface signal, workload can not embody;
5, unified framework and form at all levels, environmental quality can obtain unified assurance, also helps carrying out of evaluation activity.
Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential hardware platform, can certainly all implement by hardware.Based on such understanding, all or part of can the embodying that technical scheme of the present invention contributes to background technology with the form of software product, this computer software product can be stored in the storage medium, as ROM/RAM, magnetic disc, CD etc., comprise that some instructions are with so that a computer equipment (can be a personal computer, server, the perhaps network equipment etc.) carry out the described method of some part of each embodiment of the present invention or embodiment.
Above disclosed is a kind of preferred embodiment of the present invention only, can not limit the present invention's interest field certainly with this, and therefore the equivalent variations of doing according to claim of the present invention still belongs to the scope that the present invention is contained.
Claims (13)
1, a kind of building method of verification environment is characterized in that, comprising:
Obtain and build the required port information of verification environment, produce the hierarchy that begins with tested design top layer in the verification environment;
According to the port signal that is derived from tested design top layer, successively build the required parts of verification environment hierarchy with the direction of anti-configuration data stream.
2, the building method of verification environment as claimed in claim 1 is characterized in that, obtains the port information of building the required tested design top layer of verification environment, produces the hierarchy of verification environment, comprising:
Obtain the port information that the outside provides by tested design top layer;
The port information that is obtained is converted into the port signal that verification environment can be discerned;
Name nominating with tested design top layer produces the hierarchy that begins with tested design top layer in the verification environment.
3, the building method of verification environment as claimed in claim 1 is characterized in that, according to the port signal that is derived from tested design top layer, successively builds the required parts of verification environment hierarchy with the direction of anti-configuration data stream, comprising:
The port signal of tested design top layer is divided into groups to pack and transmit,, produce also definition emulation top layer, in described emulation top layer, finish the exampleization of the required parts of hierarchy of verification environment in the mode of the same name with the port signal of tested design top layer;
In the mode of the same name, produce the code file of bus functional model and monitoring function module at the sequential interface layer with the port signal of described emulation top layer;
According to the standard interface signal in the port signal of described bus functional model and monitoring function module, connect corresponding checking IP module;
According to the self defined interface signal in the port signal of described bus functional model and monitoring function module, connect corresponding signal configures module.
4, the building method of verification environment as claimed in claim 3 is characterized in that, finishes the exampleization of the required parts of verification environment hierarchy in described emulation top layer, comprising:
In described emulation top layer, finish the exampleization of tested design top layer, bus functional model, monitoring function module, clock/reset signal generation module.
5, the building method of verification environment as claimed in claim 3 is characterized in that, according to the standard interface signal in the port signal of described bus functional model and monitoring function module, connects corresponding checking IP module, comprising:
According to the standard interface signal of the port signal of described bus functional model and monitoring function module, the checking IP module of the checking IP module of connecting bus functional mode and monitoring function module, described standard interface signal terminates in described sequential interface layer;
The relevant information of described standard interface signal is delivered to encapsulated layer, and is encapsulated in corresponding order and the function;
Call described order or function,, described port signal in bus functional model and monitoring function module is controlled or handled by the checking IP module of described bus functional model and the checking IP module of monitoring function module.
6, the building method of verification environment as claimed in claim 3 is characterized in that, according to the self defined interface signal in the port signal of described bus functional model and monitoring function module, connects corresponding signal configures module, comprising:
According to the self defined interface signal in the port signal of described bus functional model and monitoring function module, connect the signal configures module that produces in mode of the same name;
Described self defined interface signal continues to be delivered to functional layer along the direction of port signal stream, and is present in the described signal configures modules configured use-case in mode of the same name, directly carries out the use-case configuration for the user.
7, a kind of verification environment system is characterized in that, to be derived from the port signal of tested design top layer, successively builds the required parts of verification environment with the direction of anti-configuration data stream, comprising:
Tested design top layer obtains and builds the required port information of verification environment, and the port information that is obtained is converted into the port signal that verification environment can be discerned; Name nominating with tested design top layer produces the hierarchy that begins with tested design top layer in the verification environment; Port signal is divided into groups to pack and transmit;
The emulation top layer according to the port signal generation of the same name of the top-level module of the tested design that is grouped packing, and is finished the exampleization of the required parts of verification environment hierarchy therein;
The sequential interface layer, be used for the mode of the same name with the port signal of described emulation top layer, produce the code file of bus functional model and monitoring function module therein, and according to the port signal of described bus functional model and monitoring function module, connectivity verification IP module or signal configures module;
Encapsulated layer, the relevant information of the standard interface signal in the port signal of described bus functional model and monitoring function module is encapsulated in order and the function,, described port signal in bus functional model and monitoring function module is controlled or handled by described order and function for the user by checking IP module;
Functional layer is present in the self defined interface signal in the port signal of bus functional model and monitoring function module in the described signal configures modules configured use-case in mode of the same name, directly carries out the use-case configuration for the user.
8, verification environment system as claimed in claim 7 is characterized in that, described tested design top layer comprises:
Signal receiving module is used to obtain the port information that the outside provides;
Signal processing module, the port information that is used for that signal receiving module is obtained are converted into the port signal that verification environment can be discerned, and produce the hierarchy that begins with tested design top layer in the verification environment with the name nominating of tested design top layer;
Signal transmitting module after being used for will dividing into groups through the port signal that signal processing module is handled to pack, sends to the emulation top layer.
9, verification environment system as claimed in claim 7 is characterized in that, described emulation top layer comprises:
Signal receiving module is used to receive the port signal that is grouped packing that is sent from tested design top layer signals sending module;
The parts generation module produces and defines the required parts of sequential interface layer, encapsulated layer and functional layer in the verification environment in the top level ports signal of tested design mode of the same name;
Parts exampleization module is used to finish the exampleization to described sequential interface layer, encapsulated layer and the required parts of functional layer;
Signal transmitting module, the signal that is used for handling through the emulation top layer is sent to the sequential interface layer.
10, verification environment system as claimed in claim 7 is characterized in that, the parts that described parts generation module produces and defines comprise:
The bus functionality module is used for transmitting the port signal of verification environment;
The monitoring function module is used for the various information of verification environment are managed and control.
11, verification environment system as claimed in claim 10 is characterized in that, described sequential interface layer comprises:
Signal receiving module is used to receive the described bus functional model that emulation top layer signals sending module sent and the port signal of monitoring function module;
Code generation module is used to generate the code file of bus functionality module and monitoring function module;
Signal processing module is used for the standard interface signal according to the port signal of described bus functional model and monitoring function module, connects corresponding checking IP module; According to the self defined interface signal in the port signal of described bus functional model and monitoring function module, connect corresponding signal configures module;
Signal transmitting module is sent to encapsulated layer with the relevant information of described standard interface signal; Described self defined interface signal is sent to functional layer.
12, verification environment system as claimed in claim 11 is characterized in that, described encapsulated layer comprises:
Signal receiving module is used to receive the relevant information of the standard interface signal that the sequential interface layer sent;
Package module is used for the relevant information of described standard interface signal is encapsulated in corresponding order and function;
Authentication module calls described order or function, by the checking IP module of described bus functional model and the checking IP module of monitoring function module, the port signal in bus functional model and the monitoring function module is controlled or is handled.
13, verification environment system as claimed in claim 11 is characterized in that, described functional layer comprises:
Signal receiving module is used to receive the self defined interface signal that the sequential interface layer is sent;
The signal configures module is used for described self defined interface signal is present in described signal configures modules configured use-case in mode of the same name, carries out the use-case configuration for the user.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100293098A CN101625705B (en) | 2008-07-08 | 2008-07-08 | Verification environment system and construction method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100293098A CN101625705B (en) | 2008-07-08 | 2008-07-08 | Verification environment system and construction method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101625705A true CN101625705A (en) | 2010-01-13 |
| CN101625705B CN101625705B (en) | 2011-08-24 |
Family
ID=41521554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100293098A Expired - Fee Related CN101625705B (en) | 2008-07-08 | 2008-07-08 | Verification environment system and construction method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101625705B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102622471A (en) * | 2012-02-22 | 2012-08-01 | 山东华芯半导体有限公司 | Integrated circuit front-end verification method |
| CN104714870A (en) * | 2015-03-26 | 2015-06-17 | 浪潮集团有限公司 | Method for verifying large-scale interconnection chips based on BFM |
| WO2016197768A1 (en) * | 2016-01-04 | 2016-12-15 | 中兴通讯股份有限公司 | Chip verification method, device, and system |
| CN109444726A (en) * | 2018-10-12 | 2019-03-08 | 盛科网络（苏州）有限公司 | The inspection method and check device of test and excitation behavior congruence |
| CN110515604A (en) * | 2019-08-09 | 2019-11-29 | 北京物芯科技有限责任公司 | The acquisition methods and device of the executable program file of verification environment |
| CN111176926A (en) * | 2019-12-30 | 2020-05-19 | 山东方寸微电子科技有限公司 | IP (Internet protocol) core simulation system and simulation method based on double-port SRAM (static random Access memory) |
| CN113947048A (en) * | 2021-10-21 | 2022-01-18 | 杭州云合智网技术有限公司 | Interface connection method for verifying design to be tested and related equipment |
| CN114968864A (en) * | 2022-07-28 | 2022-08-30 | 飞腾信息技术有限公司 | Verification environment construction method, chip verification method and system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1609862A (en) * | 2004-11-19 | 2005-04-27 | 华南理工大学 | IP nuclear simulation confirmation platform based on PCI bus and proving method thereof |
| CN100399341C (en) * | 2006-03-31 | 2008-07-02 | 电子科技大学 | Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method |
-
2008
- 2008-07-08 CN CN2008100293098A patent/CN101625705B/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102622471B (en) * | 2012-02-22 | 2014-07-09 | 山东华芯半导体有限公司 | Integrated circuit front-end verification method |
| CN102622471A (en) * | 2012-02-22 | 2012-08-01 | 山东华芯半导体有限公司 | Integrated circuit front-end verification method |
| CN104714870A (en) * | 2015-03-26 | 2015-06-17 | 浪潮集团有限公司 | Method for verifying large-scale interconnection chips based on BFM |
| WO2016197768A1 (en) * | 2016-01-04 | 2016-12-15 | 中兴通讯股份有限公司 | Chip verification method, device, and system |
| CN106940428A (en) * | 2016-01-04 | 2017-07-11 | 中兴通讯股份有限公司 | Chip verification method, apparatus and system |
| CN109444726B (en) * | 2018-10-12 | 2021-01-26 | 盛科网络（苏州）有限公司 | Method and device for checking consistency of test excitation behaviors |
| CN109444726A (en) * | 2018-10-12 | 2019-03-08 | 盛科网络（苏州）有限公司 | The inspection method and check device of test and excitation behavior congruence |
| CN110515604A (en) * | 2019-08-09 | 2019-11-29 | 北京物芯科技有限责任公司 | The acquisition methods and device of the executable program file of verification environment |
| CN111176926A (en) * | 2019-12-30 | 2020-05-19 | 山东方寸微电子科技有限公司 | IP (Internet protocol) core simulation system and simulation method based on double-port SRAM (static random Access memory) |
| CN111176926B (en) * | 2019-12-30 | 2023-08-15 | 山东方寸微电子科技有限公司 | IP core simulation system and simulation method based on dual-port SRAM |
| CN113947048A (en) * | 2021-10-21 | 2022-01-18 | 杭州云合智网技术有限公司 | Interface connection method for verifying design to be tested and related equipment |
| CN114968864A (en) * | 2022-07-28 | 2022-08-30 | 飞腾信息技术有限公司 | Verification environment construction method, chip verification method and system |
| CN114968864B (en) * | 2022-07-28 | 2022-10-25 | 飞腾信息技术有限公司 | Verification environment construction method, chip verification method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101625705B (en) | 2011-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101625705B (en) | Verification environment system and construction method thereof | |
| CN106291336B (en) | A kind of real-time method for down loading of FPGA test configurations code stream and system | |
| CN106021044B (en) | Reusable spi bus protocol module verification environment platform and its verification method | |
| CN103235593B (en) | A kind of blower fan master control hardware Auto-Test System and method of testing based on PLC | |
| CN103678093B (en) | A kind of automated test frame and method of testing | |
| WO2015106605A1 (en) | Method for testing station level of intelligent substation | |
| CN104053164B (en) | Things-internet gateway test system and method | |
| CN108460199B (en) | CNI modeling system | |
| CN114036013B (en) | Multi-module synchronous verification platform and verification method for transponder chip based on UVM | |
| CN206384166U (en) | Aircraft general-utility test platform | |
| CN102750301B (en) | Blueprint generating method for integrated avionic system model aiming at architecture analysis and design language (AADL) description | |
| CN107506303A (en) | Method, apparatus and system for automatic test | |
| CN105306156A (en) | Remote sensing satellite data transmission product automatic testing system and method | |
| CN103744356A (en) | Intelligent dynamically-configurable controller of tool based on DSP (Digital Signal Processor)/FPGA (Field Programmable Gate Array) and control method | |
| CN107122304A (en) | A kind of JTAG remote debugging methods | |
| CN104866423A (en) | Software configuration item test method and system | |
| CN110058974A (en) | A kind of USB PD fast charge protocol chip checking method based on RISC_V processor | |
| CN104391190A (en) | Remote diagnosis system for measuring instrument and diagnosis method thereof | |
| CN107678958A (en) | A kind of method of testing for comprehensive parameters display system software | |
| CN105024873A (en) | Protocol conformance testing system and method based on equipment and scene simulation | |
| CN110769002A (en) | LabVIEW-based message analysis method, system, electronic device and medium | |
| KR20090039069A (en) | A framework apparatus of mobile and method for providing interoperability between component | |
| CN106292584B (en) | A kind of flexible manufacturing system based on modular control unit | |
| Hacker et al. | A framework to evaluate multi-use flexibility concepts simultaneously in a co-simulation environment and a cyber-physical laboratory. | |
| CN103812905A (en) | Internet of things terminal application integrated generation system and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110824 Termination date: 20200708 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |