CN101620639A - 100-M network Ethernet synchronous precise data collector - Google Patents
100-M network Ethernet synchronous precise data collector Download PDFInfo
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Abstract
The invention relates to high-speed data collection, in particular to a 100-M network Ethernet synchronous precise data collector. The collector adopts a 8-bit A/D converter to convert an analogue signal into a high-precision digital signal which latches a vibration data signal so that the vibration data signal is received by a DSP collection unit according to a given time sequence; and an industrial computer reads information from the DSP as required and can randomly read structural vibration data by an external computer according to the requirements of a tester. In addition, the invention provides the vibration signal data with 8-bit high precision, stores a great amount of vibration signal data on the computer, and has the advantages of 100-M network Ethernet synchronous precise data collection, reliable work, synchronization requirement satisfaction and easy popularization and implementation.
Description
Technical field
The invention belongs to field of information processing, relate to the high data rate collection, especially a kind of 100-M network Ethernet synchronous precise data collector.
Background technology
When object was carried out structure analysis, analysis of vibration signal was an important step.Analyze the precise data collector that the RST of needs meets the demands in conjunction with the electronic circuit technology development according to structure vibration signals, the data of the sensor acquisition of monitoring of structures vibration are continuous more in effective zone, the actual signal that collects is true more, accuracy is high more, the device that so just needs a kind of superpower arithmetic capability, high speed acquisition to handle.By long term monitoring and analysis, can draw many information of structure, so can carry out for a long time, measure continuously, accurately the quality that is determining the structure analysis quality to a great extent to structural vibration to the structural vibration data.
Traditional vibration signal acquisition device exist acquisition channel few, need that data space is big, net synchronization capability is weak, multichannel collecting speed is low and shortcoming such as cost costliness.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art part, provide that a kind of acquisition channel is many, sampling rate is high, reliable operation and 100-M network Ethernet synchronous data collection device with low cost.
The present invention realizes that the technical scheme of purpose is:
A kind of 100-M network Ethernet synchronous precise data collector, comprise collection plate (1), DSP collecting unit (2), 100-M network Ethernet communication unit (3), peripheral hardware industrial computer (4), collection plate (1) comprises multiple signals conditioning unit (1-1) and A/D converting unit (1-2) thereof, an one synchronous trigger collection unit (1-4) and a logic control element (1-3), wherein each signal condition unit (1-1) of collection plate receives one road analog input signal (5), and will export the simulating signal that is complementary as input end after this analog input signal process amplification and the Filtering Processing with its A/D converting unit (1-2), the A/D converting unit is that parallel digital signal outputs to DSP collecting unit (2) with this analog signal conversion, the image data transmission ends of DSP collecting unit (2) links to each other with peripheral hardware industrial computer (4) by 100-M network Ethernet communication unit (3), the output terminal of the synchronous triggering unit on the collection plate (1) links to each other with the input end of the logic control element (1-3) of this collection plate (1), and DSP collecting unit (2) carries out gating by the logic control element (1-3) of collection plate.
And, the A/D conversion and control output terminal of the logic control element (1-3) on the collection plate (1) connects the control input end of the A/D converting unit (1-2) on this collection plate (1), the programmed control output terminal of the logic control element (1-3) on the collection plate (1) connects the control input end of the eprom memory (2-2) on this collection plate (1), the 100-M network Ethernet Communication Control output terminal of the logic control element (1-3) on the collection plate (1) connects the control input end of the 100-M network Ethernet communication interface unit (4) on this collection plate (1), and a plurality of data isolation control output end of the logic control element (1-3) on the collection plate (1) connects each the data isolation chip (1-2-2-1) on this collection plate (1). (1-2-2-2). and (1-2-2-3). (1-2-2-4). control input end (1-2-2-5).
And the serial ports of described 100-M network Ethernet communication unit (3) links to each other with the input end of level transferring chip (2-3) and finishes the communication of DSP collecting unit (2) and peripheral hardware industrial computer (4).
And, described A/D converting unit (1-2) adopts 8 analog to digital converters (1-2-1), described signal condition unit (1-1) is a voltage amplifier circuit, its synchronous acquisition trigger element (1-4) adopts the external signal mode to produce a level triggers signal, 23 of described logic control element (1-4), 24,25,30 pin successively with 1 of DSP central die (2-1), 144,142,141 4 address pin link to each other, its 41 (STRB), 42 (R/w), 19,20 pin successively with 12 of DSP central die, 13,120 (INT2), 121 (INT1) pin is connected, its 14 pin links to each other with synchronous triggering unit (1-4), its 11 pin links to each other with 22 pin (OENPP) of eprom memory (2-2), they are 3 years old, 1,41,42,43,44 pin successively with 3 (ESET) of 100-M network Ethernet communication unit (3), 1 (SEN), 33 (SD[7]), 19 (ORD), 18 (OWR), 16 (IRO) pin links to each other, they are 31 years old, 32 pin successively with 19 (OE) of bilateral level translator (2-3), 1 (DIR) pin links to each other, they are 12 years old, 13 successively with 40 (STRB) of DSP central die (2-1), 41 (R/W) pin links to each other, they are 34 years old, 33,35,37,40 pin successively with 19 (OE) of data isolation chip (1-2-2-1), 19 (OE) of data isolation chip (1-2-2-2), 19 (OE) of data isolation chip (1-2-2-3), 19 (OE) of data isolation chip (1-2-2-4), 19 (OE) pin of data isolation chip (1-2-2-5) links to each other, 24 (R/C) pin of its 36 pin and A/D conversion chip (1-2-1-1), 24 (R/C) pin of A/D conversion chip (1-2-1-2), 24 (R/C) pin of A/D conversion chip (1-2-1-3), 24 (R/C) pin of A/D conversion chip (1-2-1-4), 24 (R/C) pin of A/D conversion chip (1-2-1-5) links to each other.
And, described DSP collecting unit (2) is by DSP central die (2-1), bilateral level translator (2-3), eprom memory (2-2), reset circuit (2-4) is formed, D0 to the D7 pin of DSP central die (2-1) links to each other with eight input ends of bilateral level translator (2-3) by the eight bit data line, eight output terminals of bilateral level translator (2-3) connect the eight bit data input end of eprom memory (5-3) respectively, eight input ends of the eight bit data input end of 100-M network Ethernet communication unit (3) and bilateral level translator (2-3), the sixteen bit address input end of eprom memory (2-2) connects the A0-A15 pin of DSP central die (2-1), the A0-A4 pin of DSP central die (2-1) connects five bit address lines of 100-M network Ethernet mouth communication unit (3), the A20-A23 of DSP central die (5-6), the read-write pin is connected 23 of logic control element (1-3) with the STRB pin, 24,25,30,13,12 pin, first interrupt source of DSP central die (2-1) links to each other with 20 pin of logic control element (1-3), and second interrupt source of DSP central die (2-1) links to each other with 19 pin of logic control element.
And, the A0-A4 of described 100-M network Ethernet communication unit (3) successively with 30 of DSP central die (2-1), 29,27,26,24 pin link to each other, the A0 pin of 100-M network Ethernet communication unit (3) and A/D conversion chip (1-2-1-1), (1-2-1-2), (1-2-1-3), (1-2-1-4), BYTE pin (1-2-1-5) links to each other, the ESET pin of 100-M network Ethernet communication unit (3) links to each other with 1 pin with 3 pin of logic control element (1-3) respectively with the SEN pin, the SD[0 of 100-M network Ethernet communication unit (3)]-SD[7] link to each other with the data output end of bilateral level transferring chip (2-3), SA[7 wherein] pin links to each other the IRO of 100-M network Ethernet communication unit (3) with 41 pin of logic control element (1-3), OWR, ORD end successively with 44 of logic control element (1-3), 43,42 pin link to each other.
Advantage of the present invention and beneficial effect are:
1, the electricity processing of external synchronous triggering signal process synchronous trigger circuit of the present invention changes the DSP collecting unit over to through logic control element and sends the synchronous acquisition order, this order is passed to logic control element by the DSP collecting unit, logic control element sends signal opening signal acquisition channel, structure vibration signals enters collection plate and is converted into digital signal, digital signal is received by the DSP collecting unit by bus, after digital signal is handled and is analyzed through the DSP collecting unit, process 100-M network Ethernet communication unit spreads out of the computing machine to peripheral hardware, so the present invention can read the structural vibration data by the computing machine of peripheral hardware at any time according to tester's requirement.
2, to adopt 8 A/D converters be high-precision digital signal with analog signal conversion in the present invention, and this digital signal makes the vibration data signal be received by the DSP collecting unit according to given sequential by latching, and industrial computer can need read information from DSP by it.
3, the invention provides 8 high-precision vibration signal data, and make its storage in a large number on computers, have 100-M network Ethernet synchronous precise data acquisition, reliable operation, can satisfy the advantage of requirement synchronously and easy promotion and implementation.
Description of drawings
Fig. 1 is a control circuit block scheme of the present invention;
Fig. 2 is the signal condition element circuit structural drawing of Fig. 1;
Fig. 3 is the peripheral hardware annexation synoptic diagram of the DSP central die of Fig. 1;
Fig. 4 is the logic control element of Fig. 1 and the annexation synoptic diagram of peripheral hardware.
Embodiment
The invention will be further described below by specific embodiment, and following examples are descriptive, is not determinate, can not limit protection scope of the present invention with this.
A kind of 100-M network Ethernet synchronous precise data collector, comprise collection plate 1, DSP collecting unit 2,100-M network Ethernet communication unit 3, peripheral hardware industrial computer 4, collection plate 1 comprises multiple signals conditioning unit 1-1 and A/D converting unit 1-2 thereof, an one synchronous trigger collection unit 1-4 and a logic control element 1-3, wherein each signal condition unit 1-1 of collection plate receives two road analog input signals 5, and will export the simulating signal that is complementary as input end after this analog input signal process amplification and the Filtering Processing with its A/D converting unit 1-2, the A/D converting unit is that parallel digital signal outputs to DSP collecting unit 2 with this analog signal conversion, the image data transmission ends of DSP collecting unit 2 links to each other with peripheral hardware industrial computer 4 by 100-M network Ethernet communication unit 3, the output terminal of the synchronous triggering unit on the collection plate 1 links to each other with the input end of the logic control element 1-3 of this collection plate 1, and DSP collecting unit 2 carries out gating by the logic control element 1-3 of collection plate.
In the present embodiment, the chip that DSP collecting unit 2 is selected for use is TMS320VC33-150, the chip that A/D converting unit 1-2 selects for use is Ad976acr, and the chip that logic control element 1-3 selects for use is Lattice m4a5, and the chip that 100-M network Ethernet communication unit 3 is selected for use is DM9000A.
The A/D conversion and control output terminal of logic control element 1-3 on the collection plate 1 connects the control input end of the A/D converting unit 1-2 on this collection plate 1, the programmed control output terminal of logic control element 1-3 on the collection plate 1 connects the control input end of the eprom memory 2-2 on this collection plate 1, the 100-M network Ethernet Communication Control output terminal of logic control element 1-3 on the collection plate 1 connects the control input end of the 100-M network Ethernet communication interface unit 4 on this collection plate 1, and a plurality of data isolation control output end of the logic control element 1-3 on the collection plate 1 connects the control input end of each the data isolation chip 1-2-2-1.1-2-2-2.1-2-2-3.1-2-2-4.1-2-2-5 on this collection plate 1.A/D converting unit 1-2 adopts 8 analog to digital converter 1-2-1, described signal condition unit 1-1 is a voltage amplifier circuit, its synchronous acquisition trigger element 1-4 adopts the external signal mode to produce a level triggers signal, 23 of described logic control element 1-4,24,25,30 pin successively with 1 of DSP central die 2-1,144,142,141 4 address pin link to each other, its 41 (STRB), 42 (R/w), 19,20 pin successively with 12 of DSP central die, 13,120 (INT2), 121 (INT1) pin is connected, its 14 pin links to each other with synchronous triggering unit 1-4, its 11 pin links to each other with 22 pin (OENPP) of eprom memory 2-2, they are 3 years old, 1,41,42,43,44 pin successively with 3 (ESET) of 100-M network Ethernet communication unit 3,1 (SEN), 33 (SD[7]), 19 (ORD), 18 (OWR), 16 (IRO) pin links to each other, they are 31 years old, 32 pin successively with 19 (OE) of bilateral level translator 2-3,1 (DIR) pin links to each other, they are 12 years old, 13 successively with 40 (STRB) of DSP central die 2-1,41 (R/W) pin links to each other, they are 34 years old, 33,35,37,40 pin successively with 19 (OE) of data isolation chip 1-2-2-1,19 (OE) of data isolation chip 1-2-2-2,19 (OE) of data isolation chip 1-2-2-3,19 (OE) of data isolation chip 1-2-2-4,19 (OE) pin of data isolation chip 1-2-2-5 links to each other, 24 (R/C) pin of its 36 pin and A/D conversion chip 1-2-1-1,24 (R/C) pin of A/D conversion chip 1-2-1-2,24 (R/C) pin of A/D conversion chip 1-2-1-3,24 (R/C) pin of A/D conversion chip 1-2-1-4,24 (R/C) pin of A/D conversion chip 1-2-1-5 links to each other.
DSP collecting unit 2 is by DSP central die 2-1, bilateral level translator 2-3, eprom memory 2-2, reset circuit 2-4 forms, D0 to the D7 pin of DSP central die 2-1 links to each other with eight input ends of bilateral level translator 2-3 by the eight bit data line, eight output terminals of bilateral level translator 2-3 connect the eight bit data input end of eprom memory 5-3 respectively, eight input ends of the eight bit data input end of 100-M network Ethernet communication unit 3 and bilateral level translator 2-3, the sixteen bit address input end of eprom memory 2-2 connects the A0-A15 pin of DSP central die 2-1, the A0-A4 pin of DSP central die 2-1 connects five bit address lines of 100-M network Ethernet mouth communication unit 3, the A20-A23 of DSP central die 5-6, the read-write pin is connected 23 of logic control element 1-3 with the STRB pin, 24,25,30,13,12 pin, first interrupt source of DSP central die 2-1 links to each other with 20 pin of logic control element 1-3, and second interrupt source of DSP central die 2-1 links to each other with 19 pin of logic control element.
In the present embodiment, the chip that bilateral level translator 2-3 selects for use is Lvc245, and the chip that eprom memory is selected for use is W27c512.
The serial ports of 100-M network Ethernet communication unit 3 links to each other with the input end of level transferring chip 2-3 and finishes the communication of DSP collecting unit 2 and peripheral hardware industrial computer 4.The A0-A4 of 100-M network Ethernet communication unit 3 successively with 30 of DSP central die 2-1,29,27,26,24 pin link to each other, the A0 pin of 100-M network Ethernet communication unit 3 and A/D conversion chip 1-2-1-1,1-2-1-2,1-2-1-3,1-2-1-4, the BYTE pin of 1-2-1-5 links to each other, the ESET pin of 100-M network Ethernet communication unit 3 links to each other with 1 pin with 3 pin of logic control element 1-3 respectively with the SEN pin, the SD[0 of 100-M network Ethernet communication unit 3]-SD[7] link to each other with the data output end of bilateral level transferring chip 2-3, SA[7 wherein] pin links to each other the IRO of 100-M network Ethernet communication unit 3 with 41 pin of logic control element 1-3, OWR, ORD end successively with 44 of logic control element 1-3,43,42 pin link to each other.Fig. 1 is used for 100-M network Ethernet synchronous precise data collector, and waits for the acquisition instructions of external synchronous triggering signal.Signal condition unit 1-1 receives one road analog input signal, and will export the simulating signal that is complementary as the input end with A/D converting unit 1-2 after this analog input signal process amplification and the Filtering Processing; The input end of A/D converting unit 1-2 receives the above-mentioned simulating signal of a signal condition unit 1-1 output, and is parallel digital signal output with above-mentioned analog signal conversion; The image data transmission ends of DSP collecting unit 2 links to each other with peripheral hardware industrial computer 4 by 100-M network Ethernet communication unit 3, finishes the communication of industrial computer and processor; DSP collecting unit 2 is worked to the various piece gating by logic control element 1-3, and transfers the data of A/D converting unit 1-2 output to peripheral hardware industrial computer 4 by network interface communication unit 3 after simple process and carry out further data analysis processing.
Handling procedure of the present invention is stored in eprom memory 2-2, makes program and data separating among the data isolation unit 1-2-2, and system stability and operating rate are improved.
Fig. 2 is used to realize the simulated data conditioning, the input signal that simulated data process signal condition unit 1-1 and A/D converting unit 1-2 are complementary.
Fig. 3 and Fig. 4 be used for controlling of sampling, data processing and with the communication function of industrial computer.The A20-A23 of DSP central die 2, R/W, STRB pin connect the control port of giving A/D converting unit 1-2, bilateral level translator 2-3, eprom memory 2-2,100-M network Ethernet communication unit 3 with 23,24,25,30,13,12 pin of logic control element 1-3 by the decoding of logic control element 2 respectively.Peripheral hardware industrial computer 4 leans on the interrupt mode communication with DSP central die 2, after peripheral hardware industrial computer 4 is given 3 one data reading orders of 100-M network Ethernet communication unit, synchronous triggering signal is given the instruction of logic control element 1-3 synchronized sampling simultaneously, DSP collecting unit 2 enters interrupt handling routine, DSP collecting unit 2 is passed to logic control element 1-3 with control signal, logic control element 1-3 sends the signal sampling channel that signal is opened gating, structure vibration signals enters collection plate and is converted into digital signal, digital signal is received by DSP collecting unit 2 by bus, after digital signal is handled and is analyzed through DSP collecting unit 2, the computing machine that process 100-M network Ethernet unit 3 spreads out of to peripheral hardware.
Claims (6)
1, a kind of 100-M network Ethernet synchronous precise data collector, it is characterized in that: comprise collection plate (1), DSP collecting unit (2), 100-M network Ethernet communication unit (3), peripheral hardware industrial computer (4), collection plate (1) comprises multiple signals conditioning unit (1-1) and A/D converting unit (1-2) thereof, an one synchronous trigger collection unit (1-4) and a logic control element (1-3), wherein each signal condition unit (1-1) of collection plate receives one road analog input signal (5), and will export the simulating signal that is complementary as input end after this analog input signal process amplification and the Filtering Processing with its A/D converting unit (1-2), the A/D converting unit is that parallel digital signal outputs to DSP collecting unit (2) with this analog signal conversion, the image data transmission ends of DSP collecting unit (2) links to each other with peripheral hardware industrial computer (4) by 100-M network Ethernet communication unit (3), the output terminal of the synchronous triggering unit on the collection plate (1) links to each other with the input end of the logic control element (1-3) of this collection plate (1), and DSP collecting unit (2) carries out gating by the logic control element (1-3) of collection plate.
2,100-M network Ethernet synchronous precise data collector according to claim 1, it is characterized in that: the A/D conversion and control output terminal of the logic control element (1-3) on the collection plate (1) connects the control input end of the A/D converting unit (1-2) on this collection plate (1), the programmed control output terminal of the logic control element (1-3) on the collection plate (1) connects the control input end of the eprom memory (2-2) on this collection plate (1), the 100-M network Ethernet Communication Control output terminal of the logic control element (1-3) on the collection plate (1) connects the control input end of the 100-M network Ethernet communication interface unit (4) on this collection plate (1), and a plurality of data isolation control output end of the logic control element (1-3) on the collection plate (1) connects each the data isolation chip (1-2-2-1) on this collection plate (1). (1-2-2-2). and (1-2-2-3). (1-2-2-4). control input end (1-2-2-5).
3,100-M network Ethernet synchronous precise data collector according to claim 1 is characterized in that: the serial ports of described 100-M network Ethernet communication unit (3) links to each other with the input end of level transferring chip (2-3) and finishes the communication of DSP collecting unit (2) and peripheral hardware industrial computer (4).
4,100-M network Ethernet synchronous precise data collector according to claim 1 and 2, it is characterized in that: described A/D converting unit (1-2) adopts 8 analog to digital converters (1-2-1), described signal condition unit (1-1) is a voltage amplifier circuit, its synchronous acquisition trigger element (1-4) adopts the external signal mode to produce a level triggers signal, 23 of described logic control element (1-4), 24,25,30 pin successively with 1 of DSP central die (2-1), 144,142,141 4 address pin link to each other, its 41 (STRB), 42 (R/w), 19,20 pin successively with 12 of DSP central die, 13,120 (INT2), 121 (INT1) pin is connected, its 14 pin links to each other with synchronous triggering unit (1-4), its 11 pin links to each other with 22 pin (OENPP) of eprom memory (2-2), they are 3 years old, 1,41,42,43,44 pin successively with 3 (ESET) of 100-M network Ethernet communication unit (3), 1 (SEN), 33 (SD[7]), 19 (ORD), 18 (OWR), 16 (IRO) pin links to each other, they are 31 years old, 32 pin successively with 19 (OE) of bilateral level translator (2-3), 1 (DIR) pin links to each other, they are 12 years old, 13 successively with 40 (STRB) of DSP central die (2-1), 41 (R/W) pin links to each other, they are 34 years old, 33,35,37,40 pin successively with 19 (OE) of data isolation chip (1-2-2-1), 19 (OE) of data isolation chip (1-2-2-2), 19 (OE) of data isolation chip (1-2-2-3), 19 (OE) of data isolation chip (1-2-2-4), 19 (OE) pin of data isolation chip (1-2-2-5) links to each other, 24 (R/C) pin of its 36 pin and A/D conversion chip (1-2-1-1), 24 (R/C) pin of A/D conversion chip (1-2-1-2), 24 (R/C) pin of A/D conversion chip (1-2-1-3), 24 (R/C) pin of A/D conversion chip (1-2-1-4), 24 (R/C) pin of A/D conversion chip (1-2-1-5) links to each other.
5, according to claim 1 or 3 described 100-M network Ethernet synchronous precise data collectors, it is characterized in that: described DSP collecting unit (2) is by DSP central die (2-1), bilateral level translator (2-3), eprom memory (2-2), reset circuit (2-4) is formed, D0 to the D7 pin of DSP central die (2-1) links to each other with eight input ends of bilateral level translator (2-3) by the eight bit data line, eight output terminals of bilateral level translator (2-3) connect the eight bit data input end of eprom memory (5-3) respectively, eight input ends of the eight bit data input end of 100-M network Ethernet communication unit (3) and bilateral level translator (2-3), the sixteen bit address input end of eprom memory (2-2) connects the A0-A15 pin of DSP central die (2-1), the A0-A4 pin of DSP central die (2-1) connects five bit address lines of 100-M network Ethernet mouth communication unit (3), the A20-A23 of DSP central die (5-6), the read-write pin is connected 23 of logic control element (1-3) with the STRB pin, 24,25,30,13,12 pin, first interrupt source of DSP central die (2-1) links to each other with 20 pin of logic control element (1-3), and second interrupt source of DSP central die (2-1) links to each other with 19 pin of logic control element.
6,100-M network Ethernet synchronous precise data collector according to claim 3, it is characterized in that: the A0-A4 of described 100-M network Ethernet communication unit (3) successively with 30 of DSP central die (2-1), 29,27,26,24 pin link to each other, the A0 pin of 100-M network Ethernet communication unit (3) and A/D conversion chip (1-2-1-1), (1-2-1-2), (1-2-1-3), (1-2-1-4), BYTE pin (1-2-1-5) links to each other, the ESET pin of 100-M network Ethernet communication unit (3) links to each other with 1 pin with 3 pin of logic control element (1-3) respectively with the SEN pin, the SD[0 of 100-M network Ethernet communication unit (3)]-SD[7] link to each other with the data output end of bilateral level transferring chip (2-3), SA[7 wherein] pin links to each other the IRO of 100-M network Ethernet communication unit (3) with 41 pin of logic control element (1-3), OWR, ORD end successively with 44 of logic control element (1-3), 43,42 pin link to each other.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102999643A (en) * | 2011-11-22 | 2013-03-27 | 北京泛华恒兴科技有限公司 | Insulation type data acquisition card |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102999643A (en) * | 2011-11-22 | 2013-03-27 | 北京泛华恒兴科技有限公司 | Insulation type data acquisition card |
| CN102999644A (en) * | 2011-11-22 | 2013-03-27 | 北京泛华恒兴科技有限公司 | Multifunctional isolated data acquisition card |
| CN102999644B (en) * | 2011-11-22 | 2015-11-25 | 上海恩艾仪器有限公司 | Multi-function separation-type data collecting card |
| CN102999643B (en) * | 2011-11-22 | 2015-11-25 | 上海恩艾仪器有限公司 | Isolated data collecting card |
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Application publication date: 20100106 |