CN207992753U - Based on monolithic processor controlled multi-channel data acquisition processing system - Google Patents
Based on monolithic processor controlled multi-channel data acquisition processing system Download PDFInfo
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- CN207992753U CN207992753U CN201820281717.1U CN201820281717U CN207992753U CN 207992753 U CN207992753 U CN 207992753U CN 201820281717 U CN201820281717 U CN 201820281717U CN 207992753 U CN207992753 U CN 207992753U
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- data acquisition
- dsp processor
- processing system
- singlechip controller
- acquisition processing
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Abstract
The utility model discloses based on monolithic processor controlled multi-channel data acquisition processing system, it include mainly dsp processor, singlechip controller and signal pickup assembly, the dsp processor connects singlechip controller by two-port RAM, the signal pickup assembly connects singlechip controller by data processing module, the dsp processor is connected with reset circuit, the reset circuit is also connected with singlechip controller, the utility model uses the dsp processor with high-precision and high speed, and singlechip controller is connected with as control processor, it is communicated with the external world convenient for system extension, easy to use and cost is relatively low, it can effectively ensure the real-time processing of data.
Description
Technical field
The utility model is related to data processing fields, are to be based on monolithic processor controlled multi-channel data acquisition specifically
Processing system.
Background technology
Data acquisition is the process to one or more signal acquisition object informations, with the development of computer technology, number
Also increasingly extensive according to the application of acquisition system, data acquisition is a vital link in industrial control system, is being produced
In the process, generally require to detect temperature, humidity, flow and the pressure and other parameters of links at any time, meanwhile, it will also be to some inspection
The arbitrary parameter of measuring point carries out random challenge, and obtained testing result is extracted and is made a policy to be compared, and adjusts
Whole control program, in addition, in process of scientific research, maintenance data acquisition system can get a large amount of multidate information and acquisition section
The important means of data is learned, data collecting system is for converting analog signals into the digital signal that computer can identify.
Data collecting system is generally by data input channel, data storage and management, data processing, data output and display
This five parts form, and input channel will realize the detection to measurand, the work such as sampling and signal conversion, data storage with
Management stores collected data with memory, corresponding database is established, and be managed and call, at data
Reason is exactly to delete related interference noise, irrelevant information and necessary information from collected initial data, extract reaction quilt
The important information of characteristics of objects is surveyed, data output and display are exactly that data are exported and shown in a suitable form；And it counts
Its speed and precision is still depended on according to the quality of acquisition system is main, but the requirement of real-time is also gradually carried in recent years
Height, it is difficult and of high cost that there are still hardware designs in the domestic data acquisition processing system used at present based on dsp processor
The shortcomings that and workload it is larger, it is therefore desirable to such a data signal acquisition system realizes that the accurate of data-signal is adopted in real time
Collection.
Utility model content
The purpose of this utility model is to provide based on monolithic processor controlled multi-channel data acquisition processing system, using tool
Have high-precision and high speed dsp processor, and be connected with singlechip controller be used as control processor, convenient for system extension and
The external world is communicated, and easy to use and cost is relatively low, can effectively ensure the real-time processing of data.
The utility model is achieved through the following technical solutions：Based on monolithic processor controlled multi-channel data acquisition processing system
System, includes mainly dsp processor, singlechip controller and signal pickup assembly, and the dsp processor is connected by two-port RAM
Singlechip controller is connect, the signal pickup assembly connects singlechip controller, the dsp processor by data processing module
It is connected with reset circuit, the reset circuit is also connected with singlechip controller.
Further is that the utility model is better achieved, and especially uses following setting structures：The data processing module
Including A/D conversion circuits and sequentially connected signal conditioning circuit, low-pass filter circuit, shaping circuit and optical coupling isolation circuit,
The signal pickup assembly connection signal modulate circuit, the optical coupling isolation circuit connect singlechip controller, the low pass filtered
Wave circuit and shaping circuit are all connected with A/D conversion circuits.
Further is that the utility model is better achieved, and especially uses following setting structures：The A/D conversion circuits connect
Dsp processor is connect, the reset circuit connects A/D conversion circuits.
Further is that the utility model is better achieved, and especially uses following setting structures：The singlechip controller
It is also associated with FLASH memory, SRAM and display.
Further is that the utility model is better achieved, and especially uses following setting structures：The dsp processor also connects
It is connected to decoder.
Further is that the utility model is better achieved, and especially uses following setting structures：The two-port RAM uses
With two groups of independent data bus, address bus and the C6711DSK dual port RAMs for reading signal wire.
Further is that the utility model is better achieved, and especially uses following setting structures：The dsp processor uses
TMS320C6711DSK。
The utility model compared with prior art, has the following advantages and advantageous effect：
The utility model uses the side that the dsp processor with high-precision and high speed is combined with singlechip controller device
Formula, in conjunction with the characteristics of data sampling, making full use of the stronger data-handling capacity of dsp processor and microcontroller control in electric system
The autgmentability of device processed is communicated convenient for system extension with the external world, and easy to use and cost is relatively low, can effectively protect
Demonstrate,prove the real-time processing of data.
Description of the drawings
Fig. 1 is the structural schematic diagram of the utility model.
Specific implementation mode
The embodiments of the present invention are described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning
Same or similar element or element with the same or similar functions are indicated to same or similar label eventually.Below by ginseng
The embodiment for examining attached drawing description is exemplary, it is intended to for explaining the utility model, and should not be understood as to the utility model
Limitation.
Embodiment 1：
Include mainly dsp processor, list as shown in Figure 1, being based on monolithic processor controlled multi-channel data acquisition processing system
Piece machine controller and signal pickup assembly, the dsp processor connect singlechip controller, the signal by two-port RAM
Harvester connects singlechip controller by data processing module, and the dsp processor is connected with reset circuit, the reset
Circuit is also connected with singlechip controller, in the fault detect for electric system, it is contemplated that data sampling in electric system
Feature calculates active power and reactive power using the strong feature of dsp processor data-handling capacity, to voltage and current value into
Row higher hamonic wave is analyzed；The high-speed cruising ability of dsp processor and the function that can realize numerical data filtering ensure at DSP
Reason device can meet the requirement of system real time, and two-port RAM is arranged between dsp processor and singlechip controller can be real
The transmission of existing data, and error free transmission may be implemented according to communication protocol, more I/O signals, DSP are will appear in system
The I/O signal wires of processor and singlechip controller are handled, wherein the most I/O signals of singlechip controller processing, by
There are communication protocol and dsp processor to control A/D conversion circuits when dsp processor and singlechip controller are in data transmission
Read-write control signal, so the part I/O signal wires of dsp processor can be used.
Further is that the utility model is better achieved, and especially uses following setting structures：The data processing module
Including A/D conversion circuits and sequentially connected signal conditioning circuit, low-pass filter circuit, shaping circuit and optical coupling isolation circuit,
The signal pickup assembly connection signal modulate circuit, the optical coupling isolation circuit connect singlechip controller, the low pass filtered
Wave circuit and shaping circuit are all connected with A/D conversion circuits, A/D conversion circuits be suitable for it is real-time, need to carry out Multi-path synchronous
The requirement of sampling designs, and can carry out the multi-channel synchronal sampling of high speed.
Embodiment 2：
The present embodiment is further optimized based on the above embodiments, as shown in Figure 1, further is preferably real
Existing the utility model, especially uses following setting structures：The A/D conversion circuits connect dsp processor, and the reset circuit connects
A/D conversion circuits are connect, in system starts, the collected data of signal pickup assembly are adjusted by signal conditioning circuit
Reason, using being linked into after filtering in A/D conversion circuits, the A/D conversion circuits synchronize sampling, A/D to multiple signals
Conversion circuit sends gathered data to dsp processor, and corresponding operation is carried out after receiving sampled data by dsp processor
Reason, finally transmits the result to two-port RAM, and send a signal to singlechip controller, singlechip controller can be by data
Presentation of information over the display, and completes operational order by receiving host computer instruction.
Further is that the utility model is better achieved, and especially uses following setting structures：The singlechip controller
It is also associated with FLASH memory, SRAM and display, singlechip controller can receive host computer instruction, show in the display
Registration evidence.
Further is that the utility model is better achieved, and especially uses following setting structures：The dsp processor also connects
It is connected to decoder, since dsp processor is connected with two-port RAM, and the data channel of A/D conversion circuits can be selected into line number
According to read-write, so need to be arranged decoder to dsp processor to the address signal of dsp processor into row decoding processing.
Further is that the utility model is better achieved, and especially uses following setting structures：The two-port RAM uses
With two groups of independent data bus, address bus and the CY7C135 dual port RAMs for reading signal wire, dsp processor and list can be made
Piece machine controller accesses internal storage simultaneously, at the same time run when be efficiently completed fast exchange data, dsp processor to
When two-port RAM transmission data, while the corresponding position to singlechip controller transmission data information and in two-port RAM,
When singlechip controller is to two-port RAM transmission data, while to dsp processor transmission data information and in two-port RAM
In corresponding position, further improve exchange data reliability.
Further is that the utility model is better achieved, and especially uses following setting structures：The dsp processor uses
TMS320C6711DSK, TMS320C6711DSK are transmitted with extraneous information by being set to 2 internal interfaces, wherein one
It includes then the devices such as multichannel serial and clock that a interface, which facilitates carry out memory expansion, another interface, is carried for inside chip
For bus signals.
The above is only the preferred embodiment of the utility model, not does limit in any form to the utility model
System, any simple modification made by the above technical examples according to the technical essence of the present invention, equivalent variations, each falls within
Within the scope of protection of the utility model.
Claims (7)
1. being based on monolithic processor controlled multi-channel data acquisition processing system, it is characterised in that：Include mainly dsp processor, list
Piece machine controller and signal pickup assembly, the dsp processor connect singlechip controller, the signal by two-port RAM
Harvester connects singlechip controller by data processing module, and the dsp processor is connected with reset circuit, the reset
Circuit is also connected with singlechip controller.
2. according to claim 1 be based on monolithic processor controlled multi-channel data acquisition processing system, it is characterised in that：Institute
State data processing module include A/D conversion circuits and sequentially connected signal conditioning circuit, low-pass filter circuit, shaping circuit and
Optical coupling isolation circuit, the signal pickup assembly connection signal modulate circuit, the optical coupling isolation circuit connection microcontroller control
Device, the low-pass filter circuit and shaping circuit are all connected with A/D conversion circuits.
3. according to claim 1 be based on monolithic processor controlled multi-channel data acquisition processing system, it is characterised in that：Institute
It states dsp processor to connect with A/D conversion circuits, the reset circuit connects A/D conversion circuits.
4. according to claim 1-3 any one based on monolithic processor controlled multi-channel data acquisition processing system,
It is characterized in that：The singlechip controller is also associated with FLASH memory, SRAM and display.
5. according to claim 1-3 any one based on monolithic processor controlled multi-channel data acquisition processing system,
It is characterized in that：The dsp processor is also associated with decoder.
6. according to claim 1-3 any one based on monolithic processor controlled multi-channel data acquisition processing system,
It is characterized in that：The two-port RAM is used with two groups of independent data bus, address bus and the C6711DSK for reading signal wire
Dual port RAM.
7. according to claim 1-3 any one based on monolithic processor controlled multi-channel data acquisition processing system,
It is characterized in that：The dsp processor uses TMS320C6711DSK.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820281717.1U CN207992753U (en) | 2018-02-28 | 2018-02-28 | Based on monolithic processor controlled multi-channel data acquisition processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820281717.1U CN207992753U (en) | 2018-02-28 | 2018-02-28 | Based on monolithic processor controlled multi-channel data acquisition processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207992753U true CN207992753U (en) | 2018-10-19 |
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|---|---|---|---|
| CN201820281717.1U Expired - Fee Related CN207992753U (en) | 2018-02-28 | 2018-02-28 | Based on monolithic processor controlled multi-channel data acquisition processing system |
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| Country | Link |
|---|---|
| CN (1) | CN207992753U (en) |
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2018
- 2018-02-28 CN CN201820281717.1U patent/CN207992753U/en not_active Expired - Fee Related
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