CN101606134B - 地址转换方法和设备 - Google Patents

地址转换方法和设备 Download PDF

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Publication number
CN101606134B
CN101606134B CN2008800043245A CN200880004324A CN101606134B CN 101606134 B CN101606134 B CN 101606134B CN 2008800043245 A CN2008800043245 A CN 2008800043245A CN 200880004324 A CN200880004324 A CN 200880004324A CN 101606134 B CN101606134 B CN 101606134B
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China
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address
page
leaf
memory page
memory
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Expired - Fee Related
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CN2008800043245A
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English (en)
Chinese (zh)
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CN101606134A (zh
Inventor
布赖恩·约瑟夫·科佩茨
维克托·罗伯茨·奥格斯堡
詹姆斯·诺里斯·迪芬德尔费尔
托马斯·安德鲁·萨托里乌斯
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN2008800043245A 2007-02-07 2008-02-07 地址转换方法和设备 Expired - Fee Related CN101606134B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/672,066 US8239657B2 (en) 2007-02-07 2007-02-07 Address translation method and apparatus
US11/672,066 2007-02-07
PCT/US2008/053338 WO2008098140A1 (en) 2007-02-07 2008-02-07 Address translation method and apparatus

Publications (2)

Publication Number Publication Date
CN101606134A CN101606134A (zh) 2009-12-16
CN101606134B true CN101606134B (zh) 2013-09-18

Family

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Family Applications (1)

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CN2008800043245A Expired - Fee Related CN101606134B (zh) 2007-02-07 2008-02-07 地址转换方法和设备

Country Status (12)

Country Link
US (1) US8239657B2 (enExample)
EP (1) EP2118753B1 (enExample)
JP (2) JP2010518519A (enExample)
KR (1) KR101057526B1 (enExample)
CN (1) CN101606134B (enExample)
BR (1) BRPI0806994A2 (enExample)
CA (1) CA2675702A1 (enExample)
IN (1) IN2014MN01739A (enExample)
MX (1) MX2009007982A (enExample)
RU (1) RU2461870C2 (enExample)
TW (1) TWI381275B (enExample)
WO (1) WO2008098140A1 (enExample)

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US8626989B2 (en) * 2011-02-02 2014-01-07 Micron Technology, Inc. Control arrangements and methods for accessing block oriented nonvolatile memory
US10387324B2 (en) * 2011-12-08 2019-08-20 Intel Corporation Method, apparatus, and system for efficiently handling multiple virtual address mappings during transactional execution canceling the transactional execution upon conflict between physical addresses of transactional accesses within the transactional execution
US9460018B2 (en) 2012-05-09 2016-10-04 Qualcomm Incorporated Method and apparatus for tracking extra data permissions in an instruction cache
RU2504000C1 (ru) * 2012-07-20 2014-01-10 Открытое акционерное общество "КОНСТРУКТОРСКОЕ БЮРО "КОРУНД-М" (ОАО КБ "КОРУНД-М") Способ копирования данных в кэш-памяти и устройство для его осуществления
US8819342B2 (en) 2012-09-26 2014-08-26 Qualcomm Incorporated Methods and apparatus for managing page crossing instructions with different cacheability
US9600419B2 (en) 2012-10-08 2017-03-21 International Business Machines Corporation Selectable address translation mechanisms
US9280488B2 (en) 2012-10-08 2016-03-08 International Business Machines Corporation Asymmetric co-existent address translation structure formats
US9740624B2 (en) 2012-10-08 2017-08-22 International Business Machines Corporation Selectable address translation mechanisms within a partition
US9355032B2 (en) 2012-10-08 2016-05-31 International Business Machines Corporation Supporting multiple types of guests by a hypervisor
US9355040B2 (en) 2012-10-08 2016-05-31 International Business Machines Corporation Adjunct component to provide full virtualization using paravirtualized hypervisors
US9348757B2 (en) 2012-10-08 2016-05-24 International Business Machines Corporation System supporting multiple partitions with differing translation formats
US9804969B2 (en) * 2012-12-20 2017-10-31 Qualcomm Incorporated Speculative addressing using a virtual address-to-physical address page crossing buffer
KR102002900B1 (ko) 2013-01-07 2019-07-23 삼성전자 주식회사 메모리 관리 유닛을 포함하는 시스템 온 칩 및 그 메모리 주소 변환 방법
US20140310500A1 (en) * 2013-04-11 2014-10-16 Advanced Micro Devices, Inc. Page cross misalign buffer
US9632948B2 (en) * 2014-09-23 2017-04-25 Intel Corporation Multi-source address translation service (ATS) with a single ATS resource
US11442760B2 (en) 2016-07-01 2022-09-13 Intel Corporation Aperture access processors, methods, systems, and instructions
US11106596B2 (en) * 2016-12-23 2021-08-31 Advanced Micro Devices, Inc. Configurable skewed associativity in a translation lookaside buffer
US11176091B2 (en) * 2017-09-29 2021-11-16 Intel Corporation Techniques for dynamic multi-storage format database access
US20190163642A1 (en) 2017-11-27 2019-05-30 Intel Corporation Management of the untranslated to translated code steering logic in a dynamic binary translation based processor
US11061824B2 (en) * 2019-09-03 2021-07-13 Microsoft Technology Licensing, Llc Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative

Citations (2)

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CN1369808A (zh) * 2001-07-18 2002-09-18 智权第一公司 储存存储器型式数据的转译旁视缓冲器
CN1632741A (zh) * 2003-12-23 2005-06-29 凌阳科技股份有限公司 处理器中读取未对齐资料的方法与装置

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JPH05298186A (ja) * 1992-04-20 1993-11-12 Nec Corp 情報処理装置
DE69428881T2 (de) 1994-01-12 2002-07-18 Sun Microsystems, Inc. Logisch adressierbarer physikalischer Speicher für ein Rechnersystem mit virtuellem Speicher, das mehrere Seitengrössen unterstützt
US5765022A (en) * 1995-09-29 1998-06-09 International Business Machines Corporation System for transferring data from a source device to a target device in which the address of data movement engine is determined
US5734881A (en) * 1995-12-15 1998-03-31 Cyrix Corporation Detecting short branches in a prefetch buffer using target location information in a branch target cache
JP2000010863A (ja) * 1998-06-24 2000-01-14 Sony Computer Entertainment Inc 情報処理装置および方法、並びに提供媒体
US7363474B2 (en) 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
US7340582B2 (en) 2004-09-30 2008-03-04 Intel Corporation Fault processing for direct memory access address translation
US7334107B2 (en) 2004-09-30 2008-02-19 Intel Corporation Caching support for direct memory access address translation
US20060174066A1 (en) * 2005-02-03 2006-08-03 Bridges Jeffrey T Fractional-word writable architected register for direct accumulation of misaligned data
US7366869B2 (en) * 2005-03-17 2008-04-29 Qualcomm Incorporated Method and system for optimizing translation lookaside buffer entries
US20060248279A1 (en) * 2005-05-02 2006-11-02 Al-Sukhni Hassan F Prefetching across a page boundary
US7404042B2 (en) * 2005-05-18 2008-07-22 Qualcomm Incorporated Handling cache miss in an instruction crossing a cache line boundary

Patent Citations (2)

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CN1369808A (zh) * 2001-07-18 2002-09-18 智权第一公司 储存存储器型式数据的转译旁视缓冲器
CN1632741A (zh) * 2003-12-23 2005-06-29 凌阳科技股份有限公司 处理器中读取未对齐资料的方法与装置

Also Published As

Publication number Publication date
CA2675702A1 (en) 2008-08-14
EP2118753A1 (en) 2009-11-18
BRPI0806994A2 (pt) 2014-04-08
KR20090117798A (ko) 2009-11-12
KR101057526B1 (ko) 2011-08-17
JP2010518519A (ja) 2010-05-27
CN101606134A (zh) 2009-12-16
US8239657B2 (en) 2012-08-07
EP2118753B1 (en) 2013-07-10
WO2008098140A1 (en) 2008-08-14
RU2461870C2 (ru) 2012-09-20
MX2009007982A (es) 2009-08-07
JP5373173B2 (ja) 2013-12-18
IN2014MN01739A (enExample) 2015-07-03
RU2009133295A (ru) 2011-03-20
TWI381275B (zh) 2013-01-01
US20080189506A1 (en) 2008-08-07
TW200842580A (en) 2008-11-01
JP2013065325A (ja) 2013-04-11

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Granted publication date: 20130918

Termination date: 20210207