IN2014MN01739A - - Google Patents

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Publication number
IN2014MN01739A
IN2014MN01739A IN1739MUN2014A IN2014MN01739A IN 2014MN01739 A IN2014MN01739 A IN 2014MN01739A IN 1739MUN2014 A IN1739MUN2014 A IN 1739MUN2014A IN 2014MN01739 A IN2014MN01739 A IN 2014MN01739A
Authority
IN
India
Prior art keywords
address translation
memory
information associated
pages
processor
Prior art date
Application number
Inventor
Brian Joseph Kopec
Victor Roberts Augsburg
James Norris Dieffenderfer
Thomas Andrew Sartorius
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014MN01739A publication Critical patent/IN2014MN01739A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.
IN1739MUN2014 2007-02-07 2008-02-07 IN2014MN01739A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/672,066 US8239657B2 (en) 2007-02-07 2007-02-07 Address translation method and apparatus
PCT/US2008/053338 WO2008098140A1 (en) 2007-02-07 2008-02-07 Address translation method and apparatus

Publications (1)

Publication Number Publication Date
IN2014MN01739A true IN2014MN01739A (en) 2015-07-03

Family

ID=39495104

Family Applications (1)

Application Number Title Priority Date Filing Date
IN1739MUN2014 IN2014MN01739A (en) 2007-02-07 2008-02-07

Country Status (12)

Country Link
US (1) US8239657B2 (en)
EP (1) EP2118753B1 (en)
JP (2) JP2010518519A (en)
KR (1) KR101057526B1 (en)
CN (1) CN101606134B (en)
BR (1) BRPI0806994A2 (en)
CA (1) CA2675702A1 (en)
IN (1) IN2014MN01739A (en)
MX (1) MX2009007982A (en)
RU (1) RU2461870C2 (en)
TW (1) TWI381275B (en)
WO (1) WO2008098140A1 (en)

Families Citing this family (18)

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Publication number Priority date Publication date Assignee Title
US8626989B2 (en) * 2011-02-02 2014-01-07 Micron Technology, Inc. Control arrangements and methods for accessing block oriented nonvolatile memory
US10387324B2 (en) * 2011-12-08 2019-08-20 Intel Corporation Method, apparatus, and system for efficiently handling multiple virtual address mappings during transactional execution canceling the transactional execution upon conflict between physical addresses of transactional accesses within the transactional execution
US9460018B2 (en) 2012-05-09 2016-10-04 Qualcomm Incorporated Method and apparatus for tracking extra data permissions in an instruction cache
RU2504000C1 (en) * 2012-07-20 2014-01-10 Открытое акционерное общество "КОНСТРУКТОРСКОЕ БЮРО "КОРУНД-М" (ОАО КБ "КОРУНД-М") Method of copying data in cache memory and apparatus for realising said method
US8819342B2 (en) 2012-09-26 2014-08-26 Qualcomm Incorporated Methods and apparatus for managing page crossing instructions with different cacheability
US9355032B2 (en) 2012-10-08 2016-05-31 International Business Machines Corporation Supporting multiple types of guests by a hypervisor
US9348757B2 (en) 2012-10-08 2016-05-24 International Business Machines Corporation System supporting multiple partitions with differing translation formats
US9600419B2 (en) 2012-10-08 2017-03-21 International Business Machines Corporation Selectable address translation mechanisms
US9280488B2 (en) 2012-10-08 2016-03-08 International Business Machines Corporation Asymmetric co-existent address translation structure formats
US9355040B2 (en) 2012-10-08 2016-05-31 International Business Machines Corporation Adjunct component to provide full virtualization using paravirtualized hypervisors
US9740624B2 (en) 2012-10-08 2017-08-22 International Business Machines Corporation Selectable address translation mechanisms within a partition
US9804969B2 (en) * 2012-12-20 2017-10-31 Qualcomm Incorporated Speculative addressing using a virtual address-to-physical address page crossing buffer
KR102002900B1 (en) 2013-01-07 2019-07-23 삼성전자 주식회사 System on chip including memory management unit and memory address translation method thereof
US20140310500A1 (en) * 2013-04-11 2014-10-16 Advanced Micro Devices, Inc. Page cross misalign buffer
US9632948B2 (en) * 2014-09-23 2017-04-25 Intel Corporation Multi-source address translation service (ATS) with a single ATS resource
US11442760B2 (en) 2016-07-01 2022-09-13 Intel Corporation Aperture access processors, methods, systems, and instructions
US11106596B2 (en) * 2016-12-23 2021-08-31 Advanced Micro Devices, Inc. Configurable skewed associativity in a translation lookaside buffer
US20190163642A1 (en) 2017-11-27 2019-05-30 Intel Corporation Management of the untranslated to translated code steering logic in a dynamic binary translation based processor

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US5060137A (en) * 1985-06-28 1991-10-22 Hewlett-Packard Company Explicit instructions for control of translation lookaside buffers
US5768575A (en) * 1989-02-24 1998-06-16 Advanced Micro Devices, Inc. Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions
JPH05298186A (en) * 1992-04-20 1993-11-12 Nec Corp Information processor
DE69428881T2 (en) 1994-01-12 2002-07-18 Sun Microsystems Inc Logically addressable physical memory for a computer system with virtual memory that supports multiple page sizes
US5765022A (en) * 1995-09-29 1998-06-09 International Business Machines Corporation System for transferring data from a source device to a target device in which the address of data movement engine is determined
US5734881A (en) * 1995-12-15 1998-03-31 Cyrix Corporation Detecting short branches in a prefetch buffer using target location information in a branch target cache
JP2000010863A (en) * 1998-06-24 2000-01-14 Sony Computer Entertainment Inc Device and method for information processing, and provision medium
US6681311B2 (en) * 2001-07-18 2004-01-20 Ip-First, Llc Translation lookaside buffer that caches memory type information
US7363474B2 (en) 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
CN100495319C (en) * 2003-12-23 2009-06-03 凌阳科技股份有限公司 Method and device for reading misaligned data in processor
US7334107B2 (en) 2004-09-30 2008-02-19 Intel Corporation Caching support for direct memory access address translation
US7340582B2 (en) 2004-09-30 2008-03-04 Intel Corporation Fault processing for direct memory access address translation
US20060174066A1 (en) * 2005-02-03 2006-08-03 Bridges Jeffrey T Fractional-word writable architected register for direct accumulation of misaligned data
US7366869B2 (en) * 2005-03-17 2008-04-29 Qualcomm Incorporated Method and system for optimizing translation lookaside buffer entries
US20060248279A1 (en) * 2005-05-02 2006-11-02 Al-Sukhni Hassan F Prefetching across a page boundary
US7404042B2 (en) * 2005-05-18 2008-07-22 Qualcomm Incorporated Handling cache miss in an instruction crossing a cache line boundary

Also Published As

Publication number Publication date
TW200842580A (en) 2008-11-01
KR101057526B1 (en) 2011-08-17
RU2009133295A (en) 2011-03-20
US8239657B2 (en) 2012-08-07
CN101606134A (en) 2009-12-16
EP2118753A1 (en) 2009-11-18
JP5373173B2 (en) 2013-12-18
JP2010518519A (en) 2010-05-27
CN101606134B (en) 2013-09-18
MX2009007982A (en) 2009-08-07
EP2118753B1 (en) 2013-07-10
CA2675702A1 (en) 2008-08-14
US20080189506A1 (en) 2008-08-07
WO2008098140A1 (en) 2008-08-14
TWI381275B (en) 2013-01-01
BRPI0806994A2 (en) 2014-04-08
KR20090117798A (en) 2009-11-12
RU2461870C2 (en) 2012-09-20
JP2013065325A (en) 2013-04-11

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