CN101593711A - Reduce method and respective pad formation method that chip bonding pad district lattice defect forms - Google Patents
Reduce method and respective pad formation method that chip bonding pad district lattice defect forms Download PDFInfo
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- CN101593711A CN101593711A CNA2008100383836A CN200810038383A CN101593711A CN 101593711 A CN101593711 A CN 101593711A CN A2008100383836 A CNA2008100383836 A CN A2008100383836A CN 200810038383 A CN200810038383 A CN 200810038383A CN 101593711 A CN101593711 A CN 101593711A
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- conductive layer
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Abstract
The present invention has disclosed a kind of method and respective pad formation method that chip bonding pad district lattice defect forms that reduce, it utilizes the argon plasma sputter to remove a fluorine-containing thin layer that forms in this conductive layer surface in the conductive layer composition process, thereby avoided the formation of the lattice defect due to the effusion of fluorine ion in this fluorine-containing thin layer, improved the conductivity and the reliability of pad.
Description
Technical field
The present invention relates to the formation method of a kind of chip bonding pad (PAD), particularly relate to and reduce the method that the pad area lattice defect forms in a kind of chip bonding pad etching process.
Background technology
In the chip processing procedure, the member that often needs to form in each rete links together to constitute a complete semiconductor device, maybe needs semiconductor device and other electronic components are coupled together to constitute required electronic circuit module; Finish these and connect, we can say that pad is a connecting elements important in the chip processing procedure with regard to needing the many pads (PAD) of formation.For this reason, pad has higher requirement on conductivity and reliability.So often adopt aluminum or aluminum alloy to make up its conductive layer.
Yet, existing pad forms in the technology, owing to used fluorine-containing etching gas to realize the composition of pad conductive layer, so the fluorine ion of overflowing can cause the appearance of pad area lattice defect with the reactive aluminum of conductive layer, and lattice defect can cause negative effect to the conductivity and the reliability of pad.For this reason, the lattice defect that prevents and remove pad area seems particularly important.
The prior art often mode of employing time control prevents the appearance of lattice defect, however the method in this control time and unreliable; So more be after lattice defect occurs, to utilize modes such as organic solvent cleaning and plasma sputtering that it is removed in the prior art.So, all effectively do not prevent the appearance of lattice defect.
Summary of the invention
The object of the present invention is to provide a kind of method that chip bonding pad district lattice defect forms that reduces,, improve the conductivity and the reliability of pad in the pad forming process, effectively to prevent the appearance of lattice defect.
Another object of the present invention is to provide a kind of formation method of chip bonding pad,, improve the conductivity and the reliability of pad effectively to prevent the appearance of lattice defect.
For this reason, the invention provides a kind of method that chip bonding pad district lattice defect forms that reduces, it utilizes the argon plasma sputter to remove a fluorine-containing thin layer that forms in this conductive layer surface in the pad conductive layer composition process.
Further, the technological parameter of above-mentioned argon plasma sputter is as follows:
Pressure: 98mT;
Top crown power: 300W;
Bottom crown power: 100W;
Gas ratio: argon gas 300sccm, oxygen 20sccm,
Wherein mT is a millitorr, and sccm is the standard ml/min.
Further, utilize the control of the helium realization chip temperature of 15 holders in the above-mentioned argon plasma sputter procedure.
Further, above-mentioned conductive layer is aluminium lamination or aluminium alloy layer.
The present invention provides a kind of formation method of chip bonding pad in addition, and it comprises: deposit conductive layer on a chip substrate; On above-mentioned conductive layer, apply photoresist; Photoresist is carried out exposure imaging to define this chip bonding pad figure; Under the protection of the photoresist of exposure imaging, the above-mentioned conductive layer of plasma etching, and finish the composition of conductive layer; Utilize the argon plasma sputter to remove a fluorine-containing thin layer that forms in this conductive layer surface in the above-mentioned conductive layer composition process; Remove photoresist; On above-mentioned conductive layer, form protective layer.
Further, the technological parameter of above-mentioned argon plasma sputter is as follows:
Pressure: 98mT;
Top crown power: 300W;
Bottom crown power: 100W;
Gas ratio: argon gas 300sccm, oxygen 20sccm, wherein sccm is the standard ml/min.
Further, utilize the control of the helium realization chip temperature of 15 holders in the above-mentioned argon plasma sputter procedure.
Further, above-mentioned conductive layer is aluminium lamination or aluminium alloy layer.
In sum, the present invention utilizes the argon plasma sputter to remove a fluorine-containing thin layer that forms in this conductive layer surface in the above-mentioned conductive layer composition process, thereby avoided the formation of the lattice defect due to the effusion of fluorine ion in this fluorine-containing thin layer, improved the conductivity and the reliability of pad.
Description of drawings
Fig. 1 is the schematic flow sheet of the formation method of the chip bonding pad that one embodiment of the invention provided;
Fig. 2 is not for adding the pad area constituent analysis figure of argon plasma sputter step gained;
Fig. 3 is the pad area constituent analysis figure of gained after the adding argon plasma sputter step.
Embodiment
For purpose of the present invention, feature are become apparent, the specific embodiment of the present invention is further described below in conjunction with accompanying drawing.
Please refer to Fig. 1, it is the schematic flow sheet of the formation method of the chip bonding pad that one embodiment of the invention provided.As shown in the figure, this method has increased the argon gas sputter step and has removed the fluorine-containing thin layer that forms in this conductive layer surface in the conductive layer composition process in pad forms technology, avoids the formation of the lattice defect due to the effusion of fluorine ion in this fluorine-containing thin layer.It specifically comprises the steps:
S1: deposit conductive layer on chip substrate,
Wherein this conductive layer is generally aluminium lamination or aluminium alloy layer;
S2: on conductive layer, apply photoresist;
S3: photoresist is carried out exposure imaging with definition chip bonding pad figure;
S4: under the protection of the photoresist of exposure imaging, the plasma etching conductive layer, and finish the composition of conductive layer;
S5: utilize the argon plasma sputter to remove a fluorine-containing thin layer that forms in this conductive layer surface in the conductive layer composition process;
S6: remove photoresist;
S7: on conductive layer, form protective layer.
Wherein the technological parameter of step S5 is as follows:
98mT/300H/100L/300Ar/20O2/15THe，
Wherein 98mT represents that the indoor pressure of gas reaction is 98mT (millitorr); 300H represents that the power of top crown is 300W; 100L represents that the power of bottom crown is 100W; 300Ar represents that plasma etching gas comprises the argon gas of 300sccm (standard ml/min); 20O2 represents that plasma etching gas comprises the oxygen of 20sccm (standard ml/min); 15T He represents to utilize the helium of 15 holders to realize etching process chips temperature controlling.
And the technological parameter of the composition process of conductive layer is as follows among the step S4:
98mT/300H/100L/300Ar/20O2/15T?He
140mT/1700H/500L/300Ar/25SF6/40CF4/25CHF3/15T?He
80mT/1600H/800L/150Ar/15C4F8/15O2/15THe
180mT/600H/400L/500Ar/8O2/10CF4/20CHF3/15T?He
180mT/600H/300L/400Ar/3O2/9CHF3/90N2/27CF4/15T?He
Because it is a known technology, no longer explained at this, can see by this parameter, in the composition process of plasma etching realization to conductive layer, employed etching gas comprises fluoro-gas, therefore can form fluorine-containing material in etching process, be piled up in the aluminium surface and form a fluorine-containing thin layer, it is the main cause that causes the later stage lattice defect to occur.For this reason, the present invention utilizes the argon plasma sputter that it is removed, to prevent the appearance of lattice defect.
Inspect after utilize carving that (After Etch Inspection, AEI) technology detects and analyzes pad area, can obtain pad area constituent analysis figure.As Fig. 2 and shown in Figure 3, the pad area constituent analysis figure of gained after it is respectively and does not add the argon plasma sputter step and add this step.As seen from the figure, after the step of fluorine-containing thin layer is removed in the sputter of adding argon plasma, do not have tangible fluorine peak in the component-part diagram of pad area, as seen, fluorine-containing material is eliminated substantially, has avoided the formation of later stage lattice defect.
, be not that the scope that the present invention protected is when being as the criterion with claims in order to qualification the present invention below only for for example.
Claims (8)
1. one kind is reduced the method that chip bonding pad district lattice defect forms, and it is characterized in that, utilizes the argon plasma sputter to remove a fluorine-containing thin layer that forms in this conductive layer surface in the pad conductive layer composition process.
2. the method that minimizing chip bonding pad according to claim 1 district lattice defect forms is characterized in that the technological parameter of wherein above-mentioned argon plasma sputter is as follows:
Pressure: 98mT;
Top crown power: 300W;
Bottom crown power: 100W;
Gas ratio: argon gas 300sccm, oxygen 20sccm,
Wherein mT is a millitorr, and sccm is the standard ml/min.
3. the method that minimizing chip bonding pad according to claim 2 district lattice defect forms is characterized in that, utilizes the control of the helium realization chip temperature of 15 holders in the wherein above-mentioned argon plasma sputter procedure.
4. the method that minimizing chip bonding pad according to claim 1 district lattice defect forms is characterized in that wherein above-mentioned conductive layer is aluminium lamination or aluminium alloy layer.
5. the formation method of a chip bonding pad is characterized in that, comprising:
Deposit conductive layer on a chip substrate;
On above-mentioned conductive layer, apply photoresist;
Photoresist is carried out exposure imaging to define this chip bonding pad figure;
Under the protection of the photoresist of exposure imaging, the above-mentioned conductive layer of plasma etching, and finish the composition of conductive layer;
Utilize the argon plasma sputter to remove a fluorine-containing thin layer that forms in this conductive layer surface in the above-mentioned conductive layer composition process;
Remove photoresist;
On above-mentioned conductive layer, form protective layer.
6. the formation method of chip bonding pad according to claim 5 is characterized in that, the technological parameter of wherein above-mentioned argon plasma sputter is as follows:
Pressure: 98mT;
Top crown power: 300W;
Bottom crown power: 100W;
Gas ratio: argon gas 300sccm, oxygen 20sccm, wherein sccm is the standard ml/min.
7. the formation method of chip bonding pad according to claim 6 is characterized in that, utilizes the control of the helium realization chip temperature of 15 holders in the wherein above-mentioned argon plasma sputter procedure.
8. the formation method of chip bonding pad according to claim 5 is characterized in that, wherein above-mentioned conductive layer is aluminium lamination or aluminium alloy layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100383836A CN101593711B (en) | 2008-05-30 | 2008-05-30 | Method for reducing formation of crystal lattice defect of chip welding disk area and corresponding welding disk forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100383836A CN101593711B (en) | 2008-05-30 | 2008-05-30 | Method for reducing formation of crystal lattice defect of chip welding disk area and corresponding welding disk forming method |
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| Publication Number | Publication Date |
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| CN101593711A true CN101593711A (en) | 2009-12-02 |
| CN101593711B CN101593711B (en) | 2012-05-09 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103545163A (en) * | 2012-07-10 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Method for treating semiconductor structures with residual fluorine or residual chlorine |
| CN104282534A (en) * | 2014-09-24 | 2015-01-14 | 武汉新芯集成电路制造有限公司 | Method for processing metal surface defects |
| CN105762086A (en) * | 2014-12-16 | 2016-07-13 | 中芯国际集成电路制造(上海)有限公司 | Bonding pad structure manufacturing method, bonding structure manufacturing method, and bonding structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010021278A (en) * | 1999-08-12 | 2001-03-15 | 조셉 제이. 스위니 | Backside cooling gas used with self-sputtering |
| CN100362638C (en) * | 2004-07-22 | 2008-01-16 | 中芯国际集成电路制造(上海)有限公司 | Method for removing lattice defect in pad area of semiconductor device |
| CN1332429C (en) * | 2004-07-22 | 2007-08-15 | 中芯国际集成电路制造(上海)有限公司 | Method for removing lattice defect in pad area of semiconductor device |
-
2008
- 2008-05-30 CN CN2008100383836A patent/CN101593711B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103545163A (en) * | 2012-07-10 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Method for treating semiconductor structures with residual fluorine or residual chlorine |
| CN104282534A (en) * | 2014-09-24 | 2015-01-14 | 武汉新芯集成电路制造有限公司 | Method for processing metal surface defects |
| CN104282534B (en) * | 2014-09-24 | 2017-10-24 | 武汉新芯集成电路制造有限公司 | The processing method of cracks of metal surface |
| CN105762086A (en) * | 2014-12-16 | 2016-07-13 | 中芯国际集成电路制造(上海)有限公司 | Bonding pad structure manufacturing method, bonding structure manufacturing method, and bonding structure |
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| CN101593711B (en) | 2012-05-09 |
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