CN101588222A - Communication adapter with error correction processing function and application thereof - Google Patents
Communication adapter with error correction processing function and application thereof Download PDFInfo
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Abstract
A communication adapter with error correction processing function and the application thereof are disclosed. The adapter comprises a DSP and corresponding power source control module, an active crystal oscillator module and a watchdog module; it is characterized in: the serial reception interface and the serial transmission interface of the DSP are respectively connected with a level conversion module and a RS232 interface; the RS 232 interfaces are respectively connected between the communication adapter, and the external transmission terminal and the external reception terminal; the general purpose digital quantity input and output port of the DSP are respectively provided with a reception state indication module, a receiving end baud rate display module, a transmission state indication module, a transmitting end baud rate display module, an error correction processing digit number indication module, and a button module used for setting the baud rate, verification mode and error correction processing digit number of the DSP serial reception interface and the serial transmission interface. The invention can perform the communication between the communication terminals with different communication rates. The invention is used for performing the communication between the communication terminals with different communication rates.
Description
Technical field
The present invention relates to a kind of data transmission device, a kind of communications adapter of more specifically saying so with error correction processing function, can be used for remote, disturb the transfer of data between the different communicating terminal of big, baud rate or check digit.
Background technology
Along with information technology and development of computer, the terminal of various communication apparatus and employing serial communication is very universal, because different terminals collection, transmission data communication speed have nothing in common with each other, this just exists the terminal that how to realize different communication speeds or the communication issue between the communication apparatus.The multifunctional communication adapter has played the function served as bridge between plurality of devices.
In addition along with the develop rapidly of computer and mechanics of communication, the rapid increase of computer network data transport service amount, therefore also just growing to the demand of high-efficiency reliable Digital Transmission and storage system.This demand is along with becoming more urgent in commercial, government and military field towards the appearance of the extensive high-speed data network of exchange, processing and the storage of digital information.In data transmission procedure, because the existence of noise source when transmitting data between two terminals, all may make a mistake in transmission course at every turn.In fact, the situation that the part of message is distorted in the transmission is more much more more perfectly than the situation that the whole information content reaches the destination.The multiple factor that comprises circuit noise all may change or erase the one or more bits in the given data cell.Must there be the mechanism that detects and correct this mistake in a reliable system.How the subject matter that the fusion of the designing requirement Communications And Computer technology of this type systematic, system designer are concerned about be exactly in transmission course control error so that data can reliably be reappeared.
But along with a large amount of uses of various communication apparatus and more and more higher to the requirement of communication function, the weak point of communications adapter also came out gradually in the past, and its subject matter has:
1, transfer of data between two kinds of single different communication speeds can only be solved, freely switching between the multiple different communication speed can not be realized.
2, do not possess error correction processing function, only be applicable to short-range transfer of data.
3, present correction processing method, no matter data length only uses a kind of BCH code of form to carry out error correction, can not select the BCH code of suitable form according to data length, and correction process efficient is low.
Summary of the invention
The present invention is for avoiding above-mentioned existing in prior technology weak point, a kind of communications adapter and application thereof with error correction processing function is provided, be used to finish the communication between the communicating terminal of different communication speeds, utilize the BCH code error correction coding to improve reliability of data transmission, verification mode, baud rate and each correction process figure place are set, the correction process figure place when showing communication speed, the reiving/transmitting state of communicating terminal in real time and utilizing BCH code to carry out error correction at every turn arbitrarily.
Technical solution problem of the present invention adopts following technical scheme.
The communications adapter that the present invention has error correction processing function is to adopt digital signal processor DSP and the power management module of relative set, active crystal oscillator module and watchdog module; Its design feature is that the serial received interface SCIARXD and the serial transmit interface SCIBTXD of described digital signal processor DSP is connected with the RS232 interface by level switch module MAX3221 respectively, and described RS232 interface is connected with outside the transmission between terminal and the outside receiving terminal at communications adapter respectively; Be respectively arranged with accepting state indicating module, receiving terminal baud rate display module, transmit status indicating module, transmitting terminal baud rate display module at the general purpose digital quantity input/output port GPIO of described digital signal processor DSP, be used in reference to the correction process figure place indicating module that is shown in when utilizing BCH code to carry out error correction, and the key-press module that is used to be provided with baud rate, verification mode and the correction process figure place of the serial received interface SCIARXD of described digital signal processor DSP and serial transmit interface SCIBTXD.
The characteristics of data transmission method that the present invention has the communications adapter of error correction processing function are:
Setting the outside baud rate that sends terminal is f1, and the baud rate of outside receiving terminal is f2;
When f1=f2=f, the serial received interface SCIARXD of described digital signal processor DSP receives the outside data that terminal was sent that send with the baud rate of f, and the data that serial received interface SCIARXD is received transmit to outside receiving terminal with the baud rate of f by serial transmit interface SCIBTXD then;
When f1＞f2, the serial received interface SCIARXD of described digital signal processor DSP receives the outside data that terminal was sent that send with the baud rate of f1, the data that serial received interface SCIARXD is received transmit to outside receiving terminal with the baud rate of f2 by serial transmit interface SCIBTXD then, be temporarily stored in the storehouse free time of waiting in the memory among the serial transmit interface SCIBTXD for the data that do not send, send the data that serial received interface SCIARXD is received successively;
When f1＜f2, the serial received interface SCIARXD of described digital signal processor DSP receives the outside data that terminal was sent that send with the baud rate of f1, the data that serial received interface SCIARXD is received transmit to outside receiving terminal with the baud rate of f2 by serial transmit interface SCIBTXD then, perhaps the data that serial received interface SCIARXD is received are temporarily stored in the memory, when storage to can sending to outside receiving terminal with the baud rate of f2, disposablely finish transmission.
The characteristics that the present invention has the application of communications adapter in data communication system of error correction processing function are described communications adapter to be set respectively be encoder that adopts BCH code and the decoder that adopts BCH code;
The coded data processing method of described encoder is:
The received data bits of serial received interface SCIARXD of setting described digital signal processor DSP is I;
When I≤32, received data are encoded by the form of the BCH code of (63,36,5);
When 32＜I≤192, received data are encoded by the form of the BCH code of (255,199,7);
When I＞192, at first the data that the serial received interface SCIARXD of described digital signal processor DSP is received are divided into groups with 192, and for each group, the figure place of setting every group is J then:
When J≤32, encode by the form of the BCH code of (63,36,5);
When 32＜J≤192, encode by the form of the BCH code of (255,199,7);
The decoding data processing method of described decoder is:
The received data bits of serial received interface SCIARXD of setting described digital signal processor DSP is M;
When M=63, press the form of the BCH code of (63,36,5) received data are deciphered;
When M=255, press the form of the BCH code of (255,199,7) received data are deciphered;
When M＞255, at first the data that the serial received interface SCIARXD of described digital signal processor DSP is received are divided into groups with 255, and for each group, the figure place of setting every group is N then:
When N=63, press the form of the BCH code of (63,36,5) and decipher;
When N=255, press the form of the BCH code of (255,199,7) and decipher.
The characteristics that the present invention has the application of communications adapter in data communication system of error correction processing function also are:
When encoding with the form of the BCH code of described (63,36,5), maximum processing figure places of each coding are 36,4 last data word joint numbers that are used to represent each encoding process;
When the form of described BCH code with (255,199,7) was encoded, maximum processing figure places of each coding were 199, last 7 data word joint numbers that are used to represent each encoding process.
Compared with the prior art, beneficial effect of the present invention is embodied in:
Correction process figure place when 1, the present invention can be provided with verification mode, the baud rate of transfer of data arbitrarily and utilize BCH code to carry out error correction at every turn by button, do not need to extend out other module, processing speed is fast, volume is little, safe and reliable, effectively reduce the investment of whole system, tangible economic benefit is arranged.
2, for carrying out communication between the communicating terminal that adopts different baud rates, all can be by the communications adapter with error correction of the present invention, finish baud rate from a high speed to low speed or transfer of data from low speed to high speed.
3, the present invention utilizes the BCH code error correction coding, selects the BCH code of suitable form it is encoded or to decipher according to the figure place that receives data, thereby improves the efficient and the reliability of data transmission of data being carried out correction process.
Description of drawings
Fig. 1 is the hardware principle block diagram with communications adapter of error correction
Fig. 2 is the application of communications adapter in communication
Fig. 3 is general telecommunication system model framework chart
Fig. 4 is for increasing the telecommunication system model framework chart behind the communications adapter with error correction
Fig. 5 is the process of encryption algorithm
Fig. 6 is the coding main program flow chart
Fig. 7 is the process of decoding algorithm
Fig. 8 is the decoding main program flow chart
Below pass through embodiment, and the invention will be further described in conjunction with the accompanying drawings.
Embodiment
Referring to Fig. 1, the hardware of present embodiment formation includes the power management module of digital signal processor DSP and relative set, active crystal oscillator module and watchdog module; The serial received interface SCIARXD of digital signal processor DSP and serial transmit interface SCIBTXD are connected with the RS232 interface by level switch module MAX3221 respectively, and the RS232 interface is connected with outside the transmission between terminal and the outside receiving terminal at communications adapter respectively; Be respectively arranged with accepting state indicating module, receiving terminal baud rate display module, transmit status indicating module, transmitting terminal baud rate display module at the general purpose digital quantity input/output port GPIO of digital signal processor DSP, be used in reference to the correction process figure place indicating module that is shown in when utilizing BCH code to carry out error correction, and the key-press module that is used to be provided with baud rate, verification mode and the correction process figure place of the serial received interface SCIARXD of described digital signal processor DSP and serial transmit interface SCIBTXD.
The accepting state indicating module is made up of the light-emitting diode of a green, and the bright expression of diode lights is receiving data, and the transmit status indicating module is made up of the light-emitting diode of a redness, and the bright expression of diode lights is sending data.Receiving terminal baud rate display module and transmitting terminal baud rate display module are made up of six light-emitting diodes respectively, and they are corresponding one by one with six kinds of baud rate 19200bps, 9600bps, 4800bps, 2400bps, 1200bps, 600bps respectively.Correction process figure place indicating module when at every turn utilizing BCH code to carry out error correction is made up of two light-emitting diodes, the BCH code of representing two kinds of forms respectively: (63,36,5) and (255,199,7), the data bitss of 63 expressions behind BCH code coding wherein, the data bits of 36 expressions before the BCH code coding, the error correcting capability of 5 expression BCH code promptly can be corrected 5 mistakes at most, data bits before the data bits behind 255 presentation codes, 199 presentation codes, the error correcting capability of 7 expression BCH code promptly can be corrected 7 mistakes at most.Button 1 is used to be provided with outside baud rate and the verification mode that sends terminal, and button 2 is used to be provided with the baud rate and the verification mode of outside receiving terminal, and button 3 is used to be provided with the correction process figure place when at every turn utilizing BCH code to carry out error correction.Wherein button 1 and button 2 are made up of five short circuit contact pins respectively, and three short circuit contact pins are used to be provided with baud rate, and all the other two short circuit contact pins are used to be provided with verification mode, plug after short circuit emits, and represent that this data lines is selected, and state is " 1 ", otherwise is " 0 ".Be " 000 " if the state of three data lines of baud rate is set, the expression baud rate is 19200bps; State is " 001 ", and the expression baud rate is 9600bps; State is " 010 ", and the expression baud rate is 4800bps; State is " 011 ", and the expression baud rate is 2400bps; State is " 100 ", and the expression baud rate is 1200bps; State is " 101 ", and the expression baud rate is 600bps.The state that two data lines of verification mode are set is " 00 " or " 01 ", and the expression verification mode is " no parity check "; State is " 10 ", and the expression verification mode is " odd "; State is " 11 ", and the expression verification mode is " even parity check ".Button 3 is made up of two short circuit contact pins, plugs after short circuit emits, and represents that this data lines is selected, and state is " 1 ", otherwise is " 0 ".If state is " 00 ", expression is encoded by the form of the BCH code of (63,36,5) or is deciphered; State is " 01 ", and expression is encoded by the form of the BCH code of (255,199,7) or deciphered; State is " 11 ", and expression is encoded by the form of the BCH code of (63,36,5) or (255,199,7) according to the figure place that receives data or deciphered.
After the outside sends terminal and outside receiving terminal and communications adapter in the present embodiment is connected, power on, communications adapter detects baud rate, the reiving/transmitting state of two communicating terminals automatically, and baud rate indicator light and reiving/transmitting state indicator light are bright accordingly.Setting the outside baud rate that sends terminal is f1, and the baud rate of outside receiving terminal is f2:
When f1=f2=f, the serial received interface SCIARXD of digital signal processor DSP receives the outside data that terminal was sent that send with the baud rate of f, and the data that serial received interface SCIARXD is received transmit to outside receiving terminal with the baud rate of f by serial transmit interface SCIBTXD then;
When f1＞f2, the serial received interface SCIARXD of digital signal processor DSP receives the outside data that terminal was sent that send with the baud rate of f1, the data that serial received interface SCIARXD is received transmit to outside receiving terminal with the baud rate of f2 by serial transmit interface SCIBTXD then, be temporarily stored in the storehouse free time of waiting in the memory among the serial transmit interface SCIBTXD for the data that do not send, send the data that serial received interface SCIARXD is received successively;
When f1＜f2, the serial received interface SCIARXD of digital signal processor DSP receives the outside data that terminal was sent that send with the baud rate of f1, the data that serial received interface SCIARXD is received transmit to outside receiving terminal with the baud rate of f2 by serial transmit interface SCIBTXD then, perhaps the data that serial received interface SCIARXD is received are temporarily stored in the memory, when storage to can sending to outside receiving terminal with the baud rate of f2, disposablely finish transmission.
The application of communications adapter in communication as shown in Figure 2, when terminal 1 is 9600bps with the baud rate to baud rate is the terminal 2 of 1200bps when transmitting data, does not make terminal 2 data of receiving terminal 1 transmission fully because of baud rate matches between terminal 1 and the terminal 2.Be added in the present embodiment communications adapter between terminal 1 and the terminal 2 this moment, and terminal 2 gets final product the data that complete receiving terminal 1 is sent.
For general telecommunication system model as shown in Figure 3, if terminal 1 sends data to terminal 2, so between terminal 1 and terminal 2 across many other parts, as modulator, demodulator etc., and physical channel such as optical fiber, copper cash, wireless, microwave, these channels are subjected to different types of noise and disturb, and as random noise, burst noise etc., mistake appears in the data that make terminal 2 receive.Can be reappeared reliably in terminal 2 for the data that terminal 1 is sent, then on the basis of Fig. 3, be improved, as shown in Figure 4.At this moment, between terminal 1 and modulator, add the communications adapter that has error correction in the present embodiment, and it is set to adopt the encoder of BCH code, between terminal 2 and demodulator, add the communications adapter in the present embodiment, and it is set to adopt the decoder of BCH code with error correction.
Present embodiment adopts process that BCH code carries out the correction process encryption algorithm as shown in Figure 5.At first according to (n, value k) is tabled look-up and is obtained generator polynomial g (x), wherein n for the coding after data bits, k for the coding before data bits; Then the information bit that receives is moved to right (n-k) position obtain M (x), utilize M (x)/g (x) to obtain residue r (x); Utilize formula C (x)=M (x)+r (x) to calculate the code word multinomial C (x) of cyclic code at last.The main program flow chart of encoder as shown in Figure 6.At first finish initialization process, the data bits that is received according to the serial received interface SCIARXD of digital signal processor DSP selects the form of suitable BCH code to encode then, and detailed process is:
The received data bits of serial received interface SCIARXD of setting digital signal processor DSP is I;
When I≤32, by (63,36, the form of BCH code 5) is encoded to received data, when using the BCH code of this kind form to encode, maximum processing figure places of each coding are 36,4 last data word joint numbers that are used to represent each encoding process;
When 32＜I≤192, by (255,199, the form of BCH code 7) is encoded to received data, when using the BCH code of this kind form to encode, maximum processing figure places of each coding are 199, last 7 data word joint numbers that are used to represent each encoding process;
When I＞192, at first the data that the serial received interface SCIARXD of digital signal processor DSP is received are divided into groups with 192, and for each group, the figure place of setting every group is J then:
When J≤32, encode by the form of the BCH code of (63,36,5);
When 32＜J≤192, encode by the form of the BCH code of (255,199,7).
Present embodiment adopts process that BCH code carries out the correction process decoding algorithm as shown in Figure 7.At first calculate syndrome S (x) by receiverd polynomial R (x); Next adopts Berlekamp-Massey iterative algorithm mistake in computation position multinomial delta (x); The root that utilizes the Chien searching algorithm to calculate delta (x) once more obtains errors present; Correct receiverd polynomial at last, needing to obtain the information bit of transmission.The main program flow chart of decoder as shown in Figure 8.At first carry out initialization process, the data bits that is received according to the serial received interface SCIARXD of digital signal processor DSP selects the form of suitable BCH code to decipher then, and detailed process is:
The received data bits of serial received interface SCIARXD of setting digital signal processor DSP is M;
When M=63, press the form of the BCH code of (63,36,5) received data are deciphered;
When M=255, press the form of the BCH code of (255,199,7) received data are deciphered;
When M＞255, at first the data that the serial received interface SCIARXD of digital signal processor DSP is received are divided into groups with 255, and for each group, the figure place of setting every group is N then:
When N=63, press the form of the BCH code of (63,36,5) and decipher;
When N=255, press the form of the BCH code of (255,199,7) and decipher.
Claims (4)
1, a kind of communications adapter with error correction processing function adopts digital signal processor DSP and the power management module of relative set, active crystal oscillator module and watchdog module; The serial received interface SCIARXD and the serial transmit interface SCIBTXD that it is characterized in that described digital signal processor DSP are connected with the RS232 interface by level switch module MAX3221 respectively, and described RS232 interface is connected with outside the transmission between terminal and the outside receiving terminal at communications adapter respectively; Be respectively arranged with accepting state indicating module, receiving terminal baud rate display module, transmit status indicating module, transmitting terminal baud rate display module at the general purpose digital quantity input/output port GPIO of described digital signal processor DSP, be used in reference to the correction process figure place indicating module that is shown in when utilizing BCH code to carry out error correction, and the key-press module that is used to be provided with baud rate, verification mode and the correction process figure place of the serial received interface SCIARXD of described digital signal processor DSP and serial transmit interface SCIBTXD.
2, the described data transmission method with communications adapter of error correction processing function of claim 1 is characterized in that:
Setting the outside baud rate that sends terminal is f1, and the baud rate of outside receiving terminal is f2;
When f1=f2=f, the serial received interface SCIARXD of described digital signal processor DSP receives the outside data that terminal was sent that send with the baud rate of f, and the data that serial received interface SCIARXD is received transmit to outside receiving terminal with the baud rate of f by serial transmit interface SCIBTXD then;
When f1＞f2, the serial received interface SCIARXD of described digital signal processor DSP receives the outside data that terminal was sent that send with the baud rate of f1, the data that serial received interface SCIARXD is received transmit to outside receiving terminal with the baud rate of f2 by serial transmit interface SCIBTXD then, be temporarily stored in the storehouse free time of waiting in the memory among the serial transmit interface SCIBTXD for the data that do not send, send the data that serial received interface SCIARXD is received successively;
When f1＜f2, the serial received interface SCIARXD of described digital signal processor DSP receives the outside data that terminal was sent that send with the baud rate of f1, the data that serial received interface SCIARXD is received transmit to outside receiving terminal with the baud rate of f2 by serial transmit interface SCIBTXD then, perhaps the data that serial received interface SCIARXD is received are temporarily stored in the memory, when storage to can sending to outside receiving terminal with the baud rate of f2, disposablely finish transmission.
3, the described application of communications adapter in data communication system with error correction processing function of claim 1 is characterized in that being provided with respectively described communications adapter and is encoder that adopts BCH code and the decoder that adopts BCH code;
The coded data processing method of described encoder is:
The received data bits of serial received interface SCIARXD of setting described digital signal processor DSP is I;
When I≤32, received data are encoded by the form of the BCH code of (63,36,5);
When 32＜I≤192, received data are encoded by the form of the BCH code of (255,199,7);
When I＞192, at first the data that the serial received interface SCIARXD of described digital signal processor DSP is received are divided into groups with 192, and for each group, the figure place of setting every group is J then:
When J≤32, encode by the form of the BCH code of (63,36,5);
When 32＜J≤192, encode by the form of the BCH code of (255,199,7);
The decoding data processing method of described decoder is:
The received data bits of serial received interface SCIARXD of setting described digital signal processor DSP is M;
When M=63, press the form of the BCH code of (63,36,5) received data are deciphered;
When M=255, press the form of the BCH code of (255,199,7) received data are deciphered;
When M＞255, at first the data that the serial received interface SCIARXD of described digital signal processor DSP is received are divided into groups with 255, and for each group, the figure place of setting every group is N then:
When N=63, press the form of the BCH code of (63,36,5) and decipher;
When N=255, press the form of the BCH code of (255,199,7) and decipher.
4, according to the described application of communications adapter in data communication system of claim 3, it is characterized in that with error correction processing function:
When encoding with the form of the BCH code of described (63,36,5), maximum processing figure places of each coding are 36,4 last data word joint numbers that are used to represent each encoding process;
When the form of described BCH code with (255,199,7) was encoded, maximum processing figure places of each coding were 199, last 7 data word joint numbers that are used to represent each encoding process.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105915314A (en) * | 2016-04-14 | 2016-08-31 | 西安电子科技大学 | Cooperative communication coding/decoding system and cooperative communication coding/decoding method based on Ethernet interface |
| CN107168256A (en) * | 2017-05-23 | 2017-09-15 | 广东省智能制造研究所 | Towards the data collection station of medium-sized and small enterprises Discrete Production Workshop |
| CN113985750A (en) * | 2021-09-30 | 2022-01-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Interface circuit board level integrated circuit board |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1816969A (en) * | 2003-04-30 | 2006-08-09 | 马科尼通讯股份有限公司 | Forward error correction coding |
| CN2641931Y (en) * | 2003-09-24 | 2004-09-15 | 中国电子科技集团公司第五十四研究所 | Multifunctinoal programable asychronous transmission mode source unit interface module |
| CN101330671A (en) * | 2007-06-20 | 2008-12-24 | 北京三星通信技术研究有限公司 | Device and method for transmitting broadcast information |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105915314A (en) * | 2016-04-14 | 2016-08-31 | 西安电子科技大学 | Cooperative communication coding/decoding system and cooperative communication coding/decoding method based on Ethernet interface |
| CN105915314B (en) * | 2016-04-14 | 2019-01-15 | 西安电子科技大学 | A kind of collaboration communication coding/decoding system and method based on Ethernet interface |
| CN107168256A (en) * | 2017-05-23 | 2017-09-15 | 广东省智能制造研究所 | Towards the data collection station of medium-sized and small enterprises Discrete Production Workshop |
| CN113985750A (en) * | 2021-09-30 | 2022-01-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Interface circuit board level integrated circuit board |
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