JP2012199843A - Method and device for error correcting code control in data communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correcting code control method and device that can adapt to communication systems with large error rate variations or fluctuations by means of a single error correcting circuit.SOLUTION: The error correction control device in a communicator (11) having a coder (114) implementing a predetermined error correcting code includes a switching determination section (117) for determining whether or not an estimate of an error rate conceivable as transmission data in the communicator reaches a receiving communicator (13) exceeds a predetermined value, and a dummy bit insertion section (118) for, if the error rate estimate exceeds the predetermined value, inserting a dummy bit in a predetermined bit position depending on an error correcting characteristic of the error correcting code when outputting the transmission data to the coder (114).

Description

  The present invention relates to a data communication system, and more particularly to an error correction code control method and apparatus.

  In data communication via a network such as the Internet and data reading from a storage medium such as a CD-ROM, there is always a possibility that noise affects data being transferred and causes a data error. For this reason, even if a data error occurs, an error correction code that can correct the error is widely used. Frequently used error correction codes include simplest single error correction codes such as Hamming codes, and cyclic suitable for implementation such as BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes. Codes, turbo codes, codes such as LDPC (Low Density Parity Check), but codes with high signal processing load are available. Among them, LDPC is a code having characteristics approaching Shannon's theoretical limit, and has attracted attention in recent years.

  The error correction code is used in the form of forward error correction (FEC) that adds redundant data to the message and transmits the entire codeword, and the redundant data is shared again between the sender and receiver based on the transmitted message. Thus, there is a method for correcting an error in a message (hereinafter referred to as a sharing method). In FEC, before transmitting a message, redundant data is calculated by an encoder and transmitted to a receiver together with the message, and an error in the received data is detected / corrected by a receiver through a decoder. In this way, since FEC does not require data retransmission, high throughput can be obtained, and it is widely used in wireless communication and optical communication. On the other hand, the sharing method is divided into means for sharing data including errors between transmitters and receivers, and means for calculating parity information from the shared data and comparing the transceivers with each other to detect / correct errors. It is used for quantum cryptography key distribution technology and Distributed Source Coding.

  In a general error correction code, M bits of redundant data are added to a k-bit message to form an n (n = k + M) -bit code word. Depending on the number of errors present in a constant k-bit message, the required M-bit redundant data becomes large. Actually, the code length of the n-bit code word is fixed, and the ratio between the message k bits and the redundant data M bits is determined according to the error rate of the code word before error correction. Increasing the ratio of redundant data makes it possible to correct more bit errors, but decreases the data transfer efficiency. In order to correct a codeword with a bit error rate p on a binary symmetric channel, a redundancy greater than Shannon's binary entropy (H (p) =-plog2p- (1-p) log2 (1-p)) It is necessary to secure data, and the higher the bit error rate, the more redundant data is required. Therefore, the coding rate of the error correction code to be used is determined from the target bit error rate.

  Thus, the upper limit of the bit error rate that can be corrected is determined for the error correction code, and this upper limit is determined by the type of code and the coding rate. As an example, FIG. 10 shows a change in error correction performance of an LDPC code with respect to an error rate.

  The horizontal axis of FIG. 10 shows the error rate of the codeword to be subjected to error correction, and the vertical axis shows the error correction efficiency f (p) given by the following equation.

f (p) = {(1-coding rate) / error correction success probability} / H (p)
As the error correction efficiency f (p) is closer to 1.0, the error correction efficiency closer to the Shannon limit is obtained. For example, in Non-Patent Document 1, the error correction efficiency f is represented by a code having a code length of 1 M bits. A characteristic of (p) <1.1 has been reported.

  FIG. 10 shows a result of simulating error correction performance of three code lengths of 8 k bits, 16 k bits, and 130 k bits when the coding rates are 0.70 and 0.75. In the case of an encoding rate of 0.75 and a code length of 16k bits, the error correction efficiency f (p) approaches 1.0 as the error rate increases in an area where the error rate is 3.3% or less. This is because the numerator value of f (p) is constant, whereas the denominator value is increased. On the other hand, when the error rate increases to 3.5%, the error correction efficiency deteriorates rapidly. This is because the number of errors exceeding the error correctable by this code is present in the code word, so that the error correction success probability is lowered and the numerator of f (p) is increased.

  On the other hand, when the code length is set to 130 k bits even at the same coding rate of 0.75, the error correction efficiency f (p) continues to decrease smoothly to an error rate of 3.5%. This is because, by taking a long code length, the error rate fluctuation of the code word is reduced, and the probability of exceeding the number of errors that can be corrected is reduced. The characteristic of the coding rate of 0.70 in the region where the error rate is 3.6% or more shows the same tendency. Therefore, in order to obtain an error correction code with good characteristics, it is necessary to lengthen the code length and use it around the upper limit of the correctable error rate.

D. Elkouss, A. Leverrier, R. AlleauMe and JJ Boutros, “Efficient reconciliation protocol for discrete-variable quantuM key distribution,” (available at http://arxiv.org/PS_cache/arxiv/pdf/0901/0901.2140v1. pdf), Jan. 2009.

  However, the fact that the correction efficiency of a specific error correction code is improved around the upper limit of the correctable error rate means that the range of error rates that can be used efficiently is narrow. Therefore, if error rate variation and fluctuation range are large, efficient error correction cannot be performed. Examples of communication systems with large fluctuations in error rate include wireless communication with large changes in communication path conditions, and PLC (Power Line Communication) that is affected by impedance fluctuations of electrical equipment connected to a power line. Further, examples of the communication system having a large variation in error rate include a passive optical network (PON) having different transmission path conditions for each user and a communication system that processes communication data of a plurality of channels with a single error correction circuit.

  In order to support such a communication system with a wide range of error rate variations and fluctuations, it is sufficient to implement an error correction code corresponding to the worst error rate, but this degrades efficiency when the error rate is low. There is a problem of doing. As another method, it is also possible to perform error correction corresponding to a wide range of error rates by mounting a plurality of error correction circuits. However, mounting a plurality of circuits causes an increase in circuit size and power consumption.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction code control method and apparatus that can cope with a communication system in which error rate variation or fluctuation is large with a single error correction circuit.

  An error correction control apparatus according to the present invention is an error correction control apparatus in a communication device including an encoder mounted with a predetermined error correction code, and is generated before transmission data of the communication device reaches a reception side communication device. Determining means for determining whether or not the estimated value of the error rate exceeds a predetermined value; and when the estimated value of the error rate exceeds the predetermined value, a predetermined value corresponding to an error correction characteristic of the error correcting code in the transmission data And dummy bit insertion means for inserting a dummy bit at a bit position and outputting the dummy bit to the encoder.

  An error correction control method according to the present invention is an error correction control method in a communication device provided with an encoder mounted with a predetermined error correction code, and the determination means reaches the receiving side communication device when transmission data of the communication device reaches It is determined whether or not an estimated value of an error rate that has occurred up to a predetermined value has been exceeded, and when the estimated value of the error rate exceeds the predetermined value, a dummy bit insertion unit A dummy bit is inserted into a predetermined bit position corresponding to the error correction characteristic and output to the encoder.

  According to the present invention, the range of error rates that can be corrected by one error correction circuit is expanded, and it becomes possible to cope with communication systems in which variations or fluctuations in error rates are large.

FIG. 1 is a block diagram showing a communication system according to a first embodiment of the present invention. FIG. 2A is a functional block diagram for explaining the error correction code control apparatus according to the first embodiment, and FIG. 2B is a flowchart showing a dummy bit control operation as an example. FIG. 3 is an explanatory diagram showing a dummy bit insertion method in the first embodiment. FIG. 4 is a graph showing the characteristics of the error correction code used in the first embodiment. FIG. 5 is a sequence diagram showing error correction and decoding operations in the communication system according to the first embodiment. FIG. 6 is a block diagram showing a communication system according to the second embodiment of the present invention. FIG. 7 is a block diagram showing a communication system according to the third embodiment of the present invention. FIG. 8 is a block diagram showing a communication system according to the fourth embodiment of the present invention. FIG. 9 is a block diagram showing a communication system according to the fifth embodiment of the present invention. It is a graph showing the example of a characteristic of a LDPC error correction code.

1. First Embodiment Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS. In a communication system to which the present embodiment is applied, data is temporarily shared between transmitters and receivers, parity information is separately calculated for the shared data, and error correction is performed by sharing between the transmitters and receivers. By using LDPC as an error correction code and disabling a part of the LDPC check matrix H used according to the error rate, as described later, the range of error rates that can be used efficiently is expanded.

1.1) System Configuration As shown in FIG. 1, in the communication system according to the present embodiment, the transmitter 11 is connected to the receiver 13 through the transmission path 12 to transmit messages and redundant data to the receiver 13 and receive them. Data for error rate estimation, other control signals, and the like are transmitted to and received from the receiver 13. The transmission path 12 may be wired / wireless.

  The transmitter 11 includes a message transmitter 111 that transmits a message to the opposite device, a memory 112 that temporarily stores the transmitted message, and an error that calculates an error rate in the message after the transmitted message is received. A rate estimator 113, a code controller 116 that performs control of the calculation circuit of the encoder 114 with reference to the error rate estimated by the error rate estimator 113, and dummy bit insertion control for the message M read from the memory 112; Error correction code is implemented, encoder 114 that calculates a parity value from a transmission message or a message with dummy bits inserted, and parity transmitter 115 that transmits the parity value calculated by encoder 114 to the opposite device, Have.

  The receiver 13 includes a message receiver 131 that receives a message from the opposite device, a memory 132 that temporarily stores the received message, an error rate estimator 133 that calculates an error rate in the received message, A decoding controller 136 that controls the calculation circuit of the decoder 134 and performs dummy bit insertion control for the message M ′ read from the memory 132 with reference to the error rate estimated by the error rate estimator 133, and the same error as the encoder 114 A decoder 134 that executes correction codes and performs error correction with reference to the parity information received from the parity transmitter 115 of the opposite device and the received message or the message with the dummy bits inserted therein.

1.2) Expansion of error correctable range Since the code controller 116 of the transmitter 11 and the decoding controller 136 of the receiver 13 have basically the same functional configuration regarding dummy bit insertion control for the read message, Hereinafter, the code controller 116 will be described with reference to FIGS. 2 and 3. Note that the error correction code implemented in the encoder 114 and the decoder 134 has a characteristic that the error correction effect differs depending on the bit position of the message to be encoded.

  As shown in FIG. 2A, the code controller 116 includes a switching determination unit 117 and a dummy bit insertion unit 118 for dummy bit insertion control at a predetermined bit position. When the error rate estimated by the error rate estimator 113 becomes higher than a predetermined value, the switching determination unit 117 outputs the message M read from the memory 112 to the dummy bit insertion unit 118. The dummy bit insertion unit 118 generates a message M1 by inserting a dummy bit at a bit position where the error correction effect is lower in the code characteristics of the encoder 114, and outputs the message M1 to the encoder 114. If the error rate is equal to or lower than the predetermined value, the switching determination unit 117 outputs the message M to the encoder 114 as it is. As will be described in detail later, it is possible to keep the number of errors within the correctable range by inserting dummy bits at bit positions where the error correction effect is low when the error rate increases, and as a result, error correction is possible. The range of possible error rates is extended.

  When LDPC codes are implemented in encoder 114 and decoder 134, dummy bit insertion section 118 inserts dummy bits into bit positions where the column weight value in LDPC check matrix H is smaller than a predetermined value. The dummy bit insertion control operation of the code controller 116 is as follows.

  2B, the switching determination unit 117 determines whether or not the error rate estimated by the error rate estimator 113 is higher than a predetermined value (step S201). The predetermined value that is a criterion for determining whether or not to insert a dummy bit can be set to the upper limit of the error rate that can be corrected by the error correction code. If the estimated error rate is higher than the predetermined value (YES in step S201), the code controller 116 reads the predetermined amount A0 of information M0 from the transmission message M stored in the memory 112, and the switching determination unit 117 Information M0 is provided to dummy bit insertion unit 118 (step S202). The dummy bit insertion unit 118 generates a predetermined amount A1 of information M1 by inserting a dummy bit at a bit position of column weight = 2 in the LDPC check matrix H, and outputs the information M1 to the encoder 114 (step S203). If the estimated error rate is equal to or less than the predetermined value (NO in step S201), the code controller 116 reads the predetermined amount A1 of information from the transmission message M stored in the memory 112, and the switching determination unit 117 The information is output as it is to the encoder 114 (step S204).

  Next, the dummy bit insertion control will be described in more detail with reference to FIG.

  FIG. 3A shows a part of the LDPC parity check matrix implemented in this embodiment. The weight of the first column is 5, the weight of the second column is 4, the weight of the third column is 6, the weight of the fourth column is 2, and the weight of the fifth column is 3. When the parity check is performed, the error correction effect of the message bit corresponding to the column having the weight of 2 is reduced, so that when the message M1 is generated from the message M0, as shown in FIG. A fixed value “0” is inserted into the fourth bit, which is 2, and the bit numbers are sequentially shifted thereafter. Similarly thereafter, a fixed value “0” is inserted into a message bit position corresponding to a column having a column weight of 2, and the bit numbers are sequentially shifted thereafter.

  When the error rate increases in this way, the number of errors in the codeword is corrected by performing parity calculation using the message M1 in which a dummy bit having a fixed value is assigned to the bit position where the error correction effect is low. It is possible to fit within the possible range, and the error correction possible range can be expanded with one encoder 114.

  Note that the error rate estimator 113, the encoder 114, and the code controller 116 of the transmitter 11 realize equivalent functions by executing a program on a program control processor such as a CPU (Central Processing Unit) of the transmitter 11. can do. Similarly, the error rate estimator 133, the decoder 134, and the decoding controller 136 of the receiver 13 also realize equivalent functions by executing a program on a program control processor such as a CPU (Central Processing Unit) of the receiver 13. can do. Further, the function of the transmitter 11 and the function of the receiver 13 may be provided in one communication device.

1.3) System Operation Hereinafter, the operation of the communication system according to the present embodiment will be described with reference to FIG. 1, FIG. 4, and FIG.

  First, LDPC having a code length of 1 M bits and a coding rate of 0.75 is implemented in the encoder 114 and the decoder 134 in this embodiment, and the degree distribution of the LDPC parity check matrix is shown in Non-Patent Document 1. It is assumed that the distribution has the error correction performance shown in FIG. That is, as shown in FIG. 4, in the region where the error rate is lower than 3.6%, the error correction efficiency f (p) approaches 1.0 as the error rate increases, and the error rate exceeds 3.6%. The number of cases where error correction cannot be completed increases and the correction efficiency f (p) deteriorates. Therefore, in this case, a predetermined value that is a criterion for determining whether or not to insert a dummy bit is set to 3.6 (%) (step S201 in FIG. 2B).

  Referring to FIGS. 1 and 5, transmitter 11 transmits message M to receiver 13 using message transmitter 111 (step S <b> 301), and temporarily stores the transmitted message M in memory 112. The receiver 13 temporarily stores the message M ′ received by the message receiver 131 in the memory 132. The error rate estimators 113 and 133 collate partial information of the messages M and M ′ stored in the respective memories 112 and 132 to estimate the number of errors in the message (step S302). Error rate estimators 113 and 133 output the estimated error rate information to code controller 116 and decoding controller 136, respectively. In the code controller 116 and the decoding controller 136, the dummy bit control described in FIG. 2B is executed (steps S303T and S303R).

  First, if the estimated error rate of the message is 3.6% or less, the code controller 116 and the decoding controller 136 do not change the messages M and M ′ (steps S303T and S303R). The encoder 114 in the transmitter 11 reads information of 750 k bits (predetermined amount A1) from the head of the message M, calculates parity information P for 250 k bits (step S304), and the parity transmitter 115 reads this parity information. P is transmitted to the receiver 13 (step S305).

  In the process of transmitting the parity information P from the transmitter 11 to the receiver 13, an error occurs with the same probability as the message M, and is received as parity information P ′ by the parity receiver 135 of the receiver 13. In the receiver 13, the decoder 134 performs error correction using the information of the first 750 kbit (predetermined amount A1) of the received message M ′ stored in the memory 132 and the received 250 kbit parity information P ′ ( Step S306). The error-corrected information is output as it is because no dummy bit is inserted in this case (step S307). By repeating the above operation, a source message M in which all error corrections have been performed is obtained.

  On the other hand, when the error rate of the message is larger than 3.6% and 4%, the code controller 116 and the decoding controller 136 insert dummy bits into the messages M and M ′ (steps S303T and S303R). The code controller 116 reads information M0 of 650k bits (predetermined amount A0) from the message M, and adds dummy bits to obtain 750k bits of information M1. At this time, “0” is inserted as a dummy bit in a bit position corresponding to a column having a column weight of 2 in the LDPC parity check matrix. Similarly, the decoding controller 136 of the receiver 13 reads information M0 ′ of 650 kbits (predetermined amount A0) from the message M ′ and adds dummy bits to convert the information M1 ′ to 750 kbits. The fixed value is inserted at the same position as the bit position at which the transmitter 11 has inserted the fixed value “0”.

  The encoder 114 in the transmitter 11 calculates parity information P for 250 k bits from the information M1 of 750 k bits (step S304), and transmits this parity information P to the receiver 13 (step S305). As described above, in the process of transmitting the parity information P from the transmitter 11 to the receiver 13, an error occurs with the same probability as the message M and is received as the parity information P 'by the receiver 13. The decoder 134 of the receiver 13 performs error correction using the 750 kbit information M1 ′ generated by the decoding controller 136 and the 250 kbit parity information P ′ received by the parity receiver 135, and the error is corrected. Information is obtained (step S306). After the error correction, the transmitted information M0 is obtained by deleting the inserted dummy bit (step S307). By repeating the above operation, a source message M in which all error corrections have been performed is obtained.

1.4) Effects According to the first embodiment of the present invention described above, the following effects can be obtained.

  The first effect is that efficient error correction can be performed without mounting a plurality of error correction circuits. The reason is that an error correction code with a large coding rate corresponding to a low error rate is implemented, and when the error rate becomes high, dummy bits are inserted so that the number of errors in the code word is within the error correction range. This is because one error correction circuit can cope with a wide range of error rates. If dummy bit control as in this embodiment is not used, it is necessary to implement a code corresponding to the highest error rate in order to support a wide range of error rates with one error correction circuit, and a low error rate. As a result, the performance becomes excessive with respect to this data and the transmission efficiency decreases.

  The second effect is that the transmission efficiency is increased because the number of dummy bits to be inserted can be reduced. The reason is that by assigning a dummy bit to a bit having a low error correction effect, a bit position that is likely to be erroneous when the error rate is high can be preferentially excluded.

2. Second Embodiment In the first embodiment described above, error correction is performed by estimating the error rate and transmitting parity information after sharing the message between the transmitter and the receiver. However, the present invention is not limited to this. It is not something. Hereinafter, a system applied to the forward error correction (FEC) system will be described as a second embodiment of the present invention.

  As shown in FIG. 6, in the communication system according to the present embodiment, the transmitter 41 is connected to the receiver 43 through the transmission path 42. The transmission path 12 may be wired / wireless.

  The transmitter 41 includes a PCS (Physical Coding Sublayer) block 411 that generates a message, a dummy bit controller 412 that performs dummy bit insertion control described in the first embodiment, an encoder 413, and a transmission interface 414. In the present embodiment, the transmitter 41 transmits the entire codeword in which the transmission interface 414 adds redundant data (parity information) to the message.

  The receiver 43 includes a PCS block 431 that receives a message, a dummy bit controller 432 that performs dummy bit deletion control, a decoder 433 that performs error correction on the received message, a reception interface 434 that receives a codeword from the transmitter 41, and And an error rate estimator 435 for inputting the error correction number information in the received message from the decoder 433 and calculating the error rate.

  The error rate estimator 435 estimates the error rate from the error correction number of the received past codeword, returns the estimated error rate information to the dummy bit controller 412 of the transmitter 41, and performs dummy bit control of the own station. Also output to the device 432. The dummy bit controller 412 of the transmitter 41 has the functional configuration shown in FIG. 2 and operates as shown in FIG. The dummy bit controller 432 of the receiver 43 outputs the message from the decoder 433 as it is to the PCS block 431 when the dummy bit is not inserted according to the error rate information, and when the dummy bit is inserted. The dummy bits are deleted from the message from the decoder 433 and then output to the PCS block 431.

  According to this embodiment, it is applicable to forward error correction (FEC) by estimating the error rate from the number of past error corrections. When applied to forward error correction, it cannot cope with rapid error rate fluctuations. However, in a communication system where error rate fluctuations are gradual, the error correction possible range is increased when the error rate rises as in the first embodiment. It can be expanded and error correction can be performed efficiently. In the forward error correction (FEC) system according to the present embodiment, the entire codeword to which redundant data is added is transmitted from the transmitter 41 to the receiver 43, and error rate information is simply returned from the receiver 43 to the transmitter 41. High throughput can be obtained with a small number of communications.

3. Third Embodiment In the second embodiment described above, the FEC system that transmits data from one transmitter to one receiver through the transmission path is exemplified, but the present invention is not limited to this. Absent. Hereinafter, a case where the present invention is applied to a communication system in which a plurality of subscriber devices are connected to a station side device will be described as a third embodiment of the present invention. As such a system, there is a PON system in which a plurality of ONUs (optical network units) are connected to one OLT (optical line terminal).

  In the PON system, the transmission path characteristics between the station side apparatus and each subscriber apparatus may differ greatly. Even in such a case, according to the present embodiment, an error rate is obtained using one encoder. It is possible to maintain good error correction characteristics over a wide range.

  As shown in FIG. 7, in the communication system according to the present embodiment, the station-side device 51 is connected to a plurality of subscriber devices 53 and 54 through a transmission line 52 having a branching unit.

  The station-side device 51 includes a dummy bit controller 511 that performs dummy bit insertion control on the transmission message described in the first embodiment, an encoder / decoder 512, a transmission interface 513, and an error rate estimator 514. Also in the present embodiment, as in the second embodiment described above, the station side device 51 transmits the entire codeword in which redundant data (parity information) is added to the message from the transmission interface 513.

  Further, the error rate estimator 514 has a coding rate setting table prepared in advance in addition to the error rate estimation function as described above, and each subscriber device is associated with the estimated error rate. Coding rate information necessary for communication is stored in advance. The coding rate setting information table may be updated by measuring the transmission loss by the installer when starting the service, or the station apparatus sets the coding rate based on the error rate information generated in the past communication. Information may be updated. By referring to the coding rate setting table, it is possible to set the coding rate using the error rate when communicating in the past. The subscriber units 53 and 54 are encoded by dummy bit controllers 531 and 541 that perform dummy bit deletion control, encoders / decoders 532 and 542 that perform encoding of transmission data and error correction of received messages, and codes from the station side device 51. Communication interfaces 533 and 543 for receiving words are provided.

  The operations of the dummy bit controller 511 and the dummy bit controllers 531 and 541 are as described in the second embodiment. However, the dummy bit controllers 531 and 541 in the subscriber units 53 and 54 receive messages from the encoder / decoders 532 and 542 when dummy bits are not inserted according to the coding rate information from the station side device 51. Is output as it is, and when dummy bits are inserted, the dummy bits are deleted from the messages from the encoders / decoders 532 and 542 and output.

  According to the present embodiment, the transmission line characteristics are stable, and it is most effective for a system in which the error rate deteriorates instantaneously.

4). Fourth Embodiment According to the fourth embodiment of the present invention, in a system in which a transmitter and a receiver are connected by a plurality of transmission lines having different transmission line characteristics, the transmission and reception are shared through these transmission lines. Information error correction can be performed by a single error correction circuit.

4.1) System Configuration As shown in FIG. 8, in the communication system according to the present embodiment, the transmitter 61 is connected to the receiver 63 via the transmission path 62, and transmits transmission data and redundant data to the receiver 63. At the same time, data for error rate estimation and other control signals are transmitted to and received from the receiver 63. The transmission path 62 may be wired / wireless.

The transmitter 61 transmits the random number transmission interfaces (IF) 6101 to 6108 and the random number transmission interfaces 6101 to 6108 for transmitting a plurality of systems (here, 8 systems) of random numbers k _{1 to} k ₈ to the receiver 63, respectively. A memory 6109 for storing random numbers k ₁ -k ₈ , an error rate estimator 6110 for estimating an error rate generated until the random numbers transmitted by the random number transmission interfaces 6101 to 6108 reach the opposite device, and error rate estimation A dummy bit controller 6111 for inserting predetermined dummy bits into the random number read from the memory 6109 based on the error rate estimated by the device 6110, and a random number generator for outputting random number information to the random number transmission interfaces (IF) 6101 to 6108 6112 and a code for newly reading the random number K from the random number generation unit 6112 and performing encoding With a 6113, a calculator 6114 for calculating an exclusive OR of the random number after the random number and the encoding after dummy bit insertion, and a communication interface 6115 to transmit a calculation result of the calculator 6114 to the opposite apparatus.

The receiver 63 stores random number reception interfaces 6301 to 6308 that receive random numbers from the random number transmission interfaces 6101 to 6108 of the transmitter 61 and random number information k ′ ₁ −k ′ ₈ received by the random number reception interfaces 6301 to 6308. Based on the error rate estimated by the error rate estimator 6310 and the error rate estimator 6310 for estimating the error rate of the random number information k ′ ₁ -k ′ ₈ received by the random number reception interfaces 6301 to 6308. Calculation result of a dummy bit controller 6311 for inserting a predetermined dummy bit into a random number read from the memory 6309, a communication interface 6312 for receiving information sent from the communication interface 6115, and a calculator 6114 in the transmitter 61 And exclusive OR of random numbers after dummy bit insertion A calculator 6313 for calculating and a decoder 6314 for correcting an error of the calculation result of the calculator 6313 are provided.

4.2) Operation The transmitter 61 continuously generates random numbers by the random number generation unit 6112, and transmits some random numbers k ₁ -k ₈ to the receiver 63 using the random number transmission interfaces 6101 to 6108. These random numbers k ₁ -k ₈ are stored in the memory 6109. The receiver 63 receives the random number information k ′ ₁ -k ′ ₈ transmitted by the random number receiving interfaces 6301 to 6308 and stores the received information in the memory 6309. The error rate estimator 6110 of the transmitter 61 and the error rate estimator 6310 of the receiver 63 calculate error rates e1, e2,..., E8 by collating some bits of each of the eight systems of random numbers.

  Next, the transmitter 61 takes out a new random number K from the random number generation unit 6112 and performs encoding by the encoder 6113. Here, it is assumed that LDPC having a code length of 1 Mbit and a coding rate of 0.75 is mounted on encoder 6113 and decoder 6314. The encoder 6113 calculates a 250 kbit parity from the 750 kbit random number K, and sends it to the calculator 6114 as a 1 Mbit codeword C. The dummy bit controller 6111 reads a random number having a predetermined number of bits from the random number kn read from the memory 6109 with reference to the error rate en (n = 1, 2,..., 8), as described with reference to FIG. Dummy bits are added in accordance with the error rate en, and a 1-Mbit random number R is sent to the calculator 6114. The calculator 6114 calculates the exclusive OR of C and R, and transmits the calculation result M to the receiver 63 using the communication interface 6115.

  In the receiver 63, the dummy bit controller 6311 reads a random number of a predetermined number of bits from the random number k′n with reference to the error rate en ′, and performs a dummy according to the error rate en ′ as described with reference to FIG. The bits are added and sent to the calculator 6313 as a 1-Mbit random number R ′. The calculator 6313 calculates the exclusive OR of the received calculation result M ′ and the random number R ′ to obtain the calculation result C ′, and sends it to the decoder 6314. The decoder 6314 performs error correction for C ′ and obtains a random number K after the error correction.

  The error correction method as described above is used when the random numbers kn and k′n are encryption keys that contain many errors, and when these encryption keys are used to share an encryption key K that does not contain errors between the transmitter and the receiver. used.

  In this embodiment, a matrix disclosed in a non-patent document (Standard for Information Technology, IEEE Standard 802.16e, 2006) and used in WIMAX or the like is employed as an LDPC parity check matrix. In such a parity check matrix, an area of column weight 2 is arranged on the right side of the matrix, so that a generation matrix is not required at the time of encoding, and necessary parity information can be calculated only from a low density parity check matrix, so that calculation speed is increased. Is possible.

  Also in this embodiment, as in the first embodiment, when the error rate en is 3.6% or less, the dummy bit controllers 6111 and 6311 read 1 Mbit random numbers from the memories 6109 and 6309, respectively. The data is sent to the calculators 6114 and 6313 without being inserted, and as many dummy bits as necessary when the error rate en is larger than 3.6% are inserted. For example, when the error rate en is 4%, the dummy bit controllers 6111 and 6311 read the 900 kbit random numbers kn and k′n from the memories 6109 and 6309, respectively, and add a fixed pattern of 100 kbit to the end of 1M. Bit random numbers R and R ′. Here, the fixed pattern is assumed to be known in advance by both the transmitter and the receiver.

4.3) Effects According to the fourth embodiment of the present invention, the same effects as those of the first embodiment described above can be obtained. In the LDPC check matrix as disclosed in Non-Patent Document 2, an area of column weight 2 that reduces the error correction effect is arranged on the right side of the matrix, and when the error rate rises, the bit corresponding to the corresponding place is given priority. It will be wrong. Therefore, by arranging dummy bits at the bit positions corresponding to the corresponding locations, it becomes possible to keep the number of errors within the correctable range, and as a result, the range of error rates that can be corrected for errors is expanded and efficient. Error correction becomes possible.

  In the present embodiment, an example is shown in which the transmitter 61 performs encoding and the receiver 63 performs decoding, but this may be reversed. The same effect can be obtained even when the receiver 63 encodes the random number K and the transmitter 61 performs decoding. It should be noted that the effect of this embodiment is the highest when the error rate of only one channel is high among the plurality of channels for initial random number sharing and the error rates of the remaining channels are equal.

5. Fifth Embodiment According to the fifth embodiment of the present invention, by measuring the error rate of the transmission path based on the dummy bits inserted into the error correction code according to the error rate, it is possible to correct the error correction code. An error rate estimation error can be avoided.

  As shown in FIG. 9, in the communication system according to the present embodiment, the transmitter 101 is connected to the receiver 103 through the transmission path 102. The transmission path 102 may be wired or wireless.

  The transmitter 101 includes a PCS (Physical Coding Sublayer) block 1011 that generates a message, a dummy bit controller 1012 that performs dummy bit insertion control described in the first embodiment, an encoder 1013, and a transmission interface 1014. In the present embodiment, the transmitter 101 transmits the entire codeword in which the transmission interface 1014 adds redundant data (parity information) to the message.

  The receiver 103 includes a PCS block 1031 that receives a message, a dummy bit controller 1032 that performs dummy bit deletion control, a decoder 1033 that performs error correction on the received message, a reception interface 1034 that receives a codeword from the transmitter 101, reception A dummy bit error rate calculator 1036 that receives a received signal from the interface 1034 and extracts only dummy bits to calculate an error rate, and receives error rate information from the dummy bit error rate calculator 1036 and dummy bit controllers 1012 and 1032 Has an error rate transmitter 1035 that communicates the error rate of the transmission line.

  The dummy bit error rate calculator 1036 receives the signal received by the reception interface 1034 and extracts a dummy bit at a position determined with the transmitter 101 in advance. Here, the dummy bit controlled by the transceiver is a known pattern such as PRBS (Pseudo Random Binary Sequence), and the dummy bit error rate calculator 1036 collates the known pattern held by itself with the known pattern extracted from the received signal. Thus, the error rate of the transmission path is estimated. The dummy bit controller 1032 of the receiver 103 outputs the message from the decoder 1033 as it is to the PCS block 1031 when the dummy bit is not inserted according to the error rate information, and when the dummy bit is inserted. The dummy bits are deleted from the message from the decoder 1033 and output to the PCS block 1031.

  According to the present embodiment, it is possible to effectively use dummy bits inserted according to the error rate of the transmission path. In addition, the error correction code has a drawback that normal error correction and error rate estimation cannot be performed when the correctable error rate range is exceeded. However, the disadvantage can be avoided by using the method of this embodiment. .

5. Additional Notes Part or all of the above-described embodiments may be described as the following additional notes, but are not limited thereto.

(Appendix 1)
An error correction control apparatus in a communication device including an encoder mounted with a predetermined error correction code,
Judgment means for judging whether or not an estimated value of an error rate that occurs until transmission data of the communication device reaches a receiving-side communication device exceeds a predetermined value;
When the estimated value of the error rate exceeds the predetermined value, dummy bit insertion means for inserting a dummy bit at a predetermined bit position according to an error correction characteristic of the error correction code in transmission data and outputting the same to the encoder;
An error correction control device comprising:

(Appendix 2)
The error correction control apparatus according to claim 1, wherein the dummy bit is inserted into a bit position where the error correction effect of the error correction code is low.

(Appendix 3)
The error correction code is an LDPC (Low Density Parity Check) code, and the dummy bit is inserted at a bit position corresponding to a column having a column weight of 2 in the LDPC check matrix. The error correction control device described in 1.

(Appendix 4)
The error correction control apparatus according to any one of appendices 1-3, wherein the error rate is estimated by calculating an error rate after reception of the dummy bits.

(Appendix 5)
An error correction control method in a communication device including an encoder mounted with a predetermined error correction code,
The determination means determines whether or not an estimated value of an error rate that occurs until the transmission data of the communication device reaches the reception-side communication device exceeds a predetermined value,
When the estimated value of the error rate exceeds the predetermined value, the dummy bit insertion means inserts a dummy bit at a predetermined bit position corresponding to the error correction characteristic of the error correction code in the transmission data and outputs the dummy bit to the encoder.
An error correction control method characterized by the above.

(Appendix 6)
The error correction control method according to appendix 4, wherein the dummy bit is inserted at a bit position where the error correction effect of the error correction code is low.

(Appendix 7)
The error correction code is an LDPC (Low Density Parity Check) code, and the dummy bit is inserted at a bit position corresponding to a column having a column weight of 2 in the LDPC check matrix. The error correction control method described in 1.

(Appendix 8)
The error correction control method according to any one of supplementary notes 5-7, wherein the error rate is estimated by calculating an error rate after receiving the dummy bits.

(Appendix 9)
A program for realizing in a program control processor an error correction control function in a communication device including an encoder mounted with a predetermined error correction code,
A function of determining whether or not an estimated value of an error rate generated until transmission data of the communication device reaches the receiving-side communication device exceeds a predetermined value;
A function for inserting a dummy bit at a predetermined bit position corresponding to an error correction characteristic of the error correction code in transmission data and outputting the dummy bit insertion means to the encoder when the estimated value of the error rate exceeds the predetermined value; When,
Is realized by the program control processor.

(Appendix 10)
A transmission device including an encoder mounted with a predetermined error correction code,
Determining means for determining whether or not an estimated value of an error rate that occurs until the transmission data reaches the receiving device exceeds a predetermined value;
Dummy bit insertion means for inserting a dummy bit at a predetermined bit position according to an error correction characteristic of the error correction code in transmission data;
Control means for outputting the data in which dummy bits are inserted by the dummy bit inserting means to the encoder when the estimated value of the error rate exceeds the predetermined value;
A transmission device comprising:

(Appendix 11)
A receiving device including a decoder that implements a predetermined error correction code,
Determining means for determining whether or not the estimated value of the error rate of the received data received from the transmitting device exceeds a predetermined value;
Dummy bit insertion means for inserting a dummy bit at a predetermined bit position according to an error correction characteristic of the error correction code in received data;
Control means for outputting data into which the dummy bits are inserted by the dummy bit inserting means to the decoder when the estimated value of the error rate exceeds the predetermined value;
A receiving apparatus comprising:

(Appendix 12)
A communication system in which a transmission device and a reception device are connected via a transmission path,
The transmitter is
Encoding means implemented with a predetermined error correction code;
First determination means for determining whether or not an estimated value of an error rate generated until transmission data reaches the receiving device exceeds a predetermined value;
First dummy bit insertion means for inserting a dummy bit at a predetermined bit position according to an error correction characteristic of the error correction code in transmission data;
First control means for outputting data in which dummy bits are inserted by the first dummy bit insertion means to the encoding means when the estimated value of the error rate exceeds the predetermined value;
And transmitting the transmission data and the redundant data obtained by the encoding means separately to the receiving device,
The receiving device is:
Decoding means implemented with the predetermined error correction code;
Second determination means for determining whether or not an estimated value of an error rate of received data received from the transmission device exceeds a predetermined value;
Second dummy bit insertion means for inserting a dummy bit at the same predetermined bit position as the first dummy bit insertion means in the received data;
Second control means for outputting data into which the dummy bit is inserted by the second dummy bit inserting means to the decoding means when the estimated value of the error rate exceeds the predetermined value;
Having
A communication system characterized by the above.

(Appendix 13)
The transmitting apparatus transmits a plurality of transmission data to the receiving apparatus through a plurality of transmission paths having different transmission path characteristics, and transmits redundant data obtained by the encoding means for each transmission data separately from the transmission data. The communication system according to supplementary note 10, characterized by:

(Appendix 14)
12. The communication system according to appendix 10 or 11, wherein the decoding unit of the receiving device performs error correction of data in which the dummy bits are inserted using redundant data received from the transmitting device.

(Appendix 15)
A communication system in which a transmission device and a reception device are connected via a transmission path,
The transmitter is
Encoding means implemented with a predetermined error correction code;
First determination means for determining whether or not an estimated value of an error rate generated until transmission data reaches the receiving device exceeds a predetermined value;
First dummy bit insertion means for inserting a dummy bit at a predetermined bit position according to an error correction characteristic of the error correction code in transmission data;
First control means for outputting data in which dummy bits are inserted by the first dummy bit insertion means to the encoding means when the estimated value of the error rate exceeds the predetermined value;
And the encoding means transmits both the data in which the dummy bits are inserted and the redundant data obtained therefrom to the receiving device,
The receiving device is:
Second determination means for determining whether or not an estimated value of an error rate of received data received from the transmission device exceeds a predetermined value;
Decoding means for implementing the predetermined error correction code and decoding the received data;
Second dummy bit insertion means for deleting a dummy bit at the same predetermined bit position as the first dummy bit insertion means from the decoded data;
Having
A communication system characterized by the above.

  The present invention can be used in a communication system in which fluctuations and differences in transmission path characteristics are large and an error rate correction code corresponding to a wide error rate range is required.

11, 41, 61, 101 Transmitter 12, 42, 62, 102 Transmission path 13, 43, 63, 103 Receiver 51 Station side device 53, 54 Subscriber device 111 Message transmitter 112, 132, 6109, 6309 Memory 113 133, 435, 514, 6110, 6310 Error rate estimator 114, 413, 6113, 1013 Encoder 115 Parity transmitter 116 Code controller 117 Switching determination unit 118 Dummy bit insertion unit 136, 412, 432, 511, 6111, 1012, 1032 Dummy bit controller 131 Message receiver 134, 433, 6314, 1033 Decoder 135 Parity receiver 411, 431, 1011, 1031 PCS block 414, 6115, 1014 Transmission interface 434, 6312, 1034 Reception interface Face 512,532,542 encoder / decoder 513,533,543 communication interface 6112 the random number generation unit 6101 to 6,108 random transmission interface 6301-6308 random number received interface 6114,6313 calculator 1036 dummy bit error rate calculator

Claims (10)

An error correction control apparatus in a communication device including an encoder mounted with a predetermined error correction code,
Judgment means for judging whether or not an estimated value of an error rate that occurs until transmission data of the communication device reaches a receiving-side communication device exceeds a predetermined value;
When the estimated value of the error rate exceeds the predetermined value, dummy bit insertion means for inserting a dummy bit at a predetermined bit position according to an error correction characteristic of the error correction code in transmission data and outputting the same to the encoder;
An error correction control device comprising:   2. The error correction control apparatus according to claim 1, wherein the dummy bit is inserted into a bit position where the error correction effect of the error correction code is low.   The error correction code is an LDPC (Low Density Parity Check) code, and the dummy bits are inserted into bit positions corresponding to columns having a column weight of 2 in the LDPC check matrix. 2. The error correction control apparatus according to 2.   The error correction control apparatus according to claim 1, wherein the error rate is estimated by calculating an error rate after receiving the dummy bits. An error correction control method in a communication device including an encoder mounted with a predetermined error correction code,
The determination means determines whether or not an estimated value of an error rate that occurs until the transmission data of the communication device reaches the reception-side communication device exceeds a predetermined value,
When the estimated value of the error rate exceeds the predetermined value, the dummy bit insertion means inserts a dummy bit at a predetermined bit position corresponding to the error correction characteristic of the error correction code in the transmission data and outputs the dummy bit to the encoder.
An error correction control method characterized by the above.   5. The error correction control method according to claim 4, wherein the dummy bit is inserted into a bit position where the error correction effect of the error correction code is low.   The error correction code is an LDPC (Low Density Parity Check) code, and the dummy bits are inserted into bit positions corresponding to columns having a column weight of 2 in the LDPC check matrix. 3. The error correction control method according to 2.   The error correction control method according to claim 5, wherein the error rate is estimated by calculating an error rate after reception of the dummy bits. A transmission device including an encoder mounted with a predetermined error correction code,
Determining means for determining whether or not an estimated value of an error rate that occurs until the transmission data reaches the receiving device exceeds a predetermined value;
Dummy bit insertion means for inserting a dummy bit at a predetermined bit position according to an error correction characteristic of the error correction code in transmission data;
Control means for outputting the data in which dummy bits are inserted by the dummy bit inserting means to the encoder when the estimated value of the error rate exceeds the predetermined value;
A transmission device comprising: A receiving device including a decoder that implements a predetermined error correction code,
Determining means for determining whether or not the estimated value of the error rate of the received data received from the transmitting device exceeds a predetermined value;
Dummy bit insertion means for inserting a dummy bit at a predetermined bit position according to an error correction characteristic of the error correction code in received data;
Control means for outputting data into which the dummy bits are inserted by the dummy bit inserting means to the decoder when the estimated value of the error rate exceeds the predetermined value;
A receiving apparatus comprising:

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