CN101587898A - A semiconductor structure with an integrated circuit component and formation and operation method thereof - Google Patents

Abstract

The invention discloses an integrated circuit component, which comprises a thin-film transistor, a stack array, and adopts band-gap engineering project tunneling layer under NANA with no junction. The integrated circuit element includes a passage area that formed in the semi-conductor main body on the insulation layer; a tunneling dielectric structure which is set on the passage area, and the tunneling dielectric structure comprises a multi-layer structure, and the multi-layer structure comprises at least one positive hole tunneling energy barrier height of layer, and the positive hole tunneling energy barrier height of layer is smaller than positive hole tunneling energy barrier height of the interface between the layer and the passage area; a charge storage layer set on the tunneling dielectric structure; an insulation layer set on the charge storage layer; and a gate electrode that set on the insulation layer. The semiconductor structure with the integrated circuit element and the operation method are described too.

Description

Semiconductor structure and formation and method of operating with integrated circuit component

The reference paper of related application

The present invention is the continuous case of part of No. the 11/831594th, the United States Patent (USP) of on July 31st, 2007 application, it is the continuous case in No. the 11/324581st, the United States Patent (USP) of on January 3rd, 2006 application, it is based on U.S. method U.S.C. § 119 (e) application priority and based on, No. the 60/640229th, the temporary transient application case of United States Patent (USP) of application on January 3rd, 2005; No. the 60/689231st, the temporary transient application case of United States Patent (USP) of application on January 27th, 2005; No. the 60/689231st, the temporary transient application case of United States Patent (USP) of application on June 10th, 2005; And No. the 60/689314th, the temporary transient application case of United States Patent (USP) of on June 10th, 2005 application; Its each complete content is with as cooperating reference at this.

The present invention is the continuous case of part of No. the 11/425959th, United States Patent (USP), and its application priority is based on No. the 60/748911st, the temporary transient application case of United States Patent (USP) of application on December 9th, 2005, and its each complete content is as cooperating reference at this.

The present invention is the continuous case of part for No. the 11/549520th, United States Patent (USP), and its application priority is based on No. the 60/748911st, the temporary transient application case of United States Patent (USP) of application on December 9th, 2005, and its each complete content is as cooperating reference at this.

The present patent application priority is based on No. the 61/018589th, the temporary transient application case of United States Patent (USP) of No. the 60/980788th, the United States Patent (USP) of on October 18th, 2007 application and application on January 2nd, 2008, and its each complete content is as cooperating reference at this.

Technical field

The invention relates to the integrated circuit technique that comprises the integrated circuit memory element that is used to have a new structure, particularly have semiconductor structure and the formation and the method for operating of integrated circuit component.

Background technology

Nonvolatile memory (NVM) is meant under the situation that can be removed in the power supply supply of the element that contains this NVM unit, the semiconductor memory that still stores data sustainably.NVM comprise mask ROM (Mask ROM), programmable formula read-only memory (PROM) but, can wipe program read-only memory (EPROM) but, electrically can wipe program read-only memory (EEPROM) and flash memory.Nonvolatile memory is to be widely used in semiconductor industry and is that a class can prevent the memory that program data is lost.Usually, nonvolatile memory can according to the terminal instructions for use of this element by sequencing, read and/or wipe, and the data of this sequencing can be by long term storage.

Generally speaking, non-volatile memory element may have various design.A kind of example of NVM cell design is the element that for this reason is loosely referred to as silicon-oxide-nitride--oxide-silicon (SONOS), and it can use a tunnel oxide that approaches to allow hole direct Tunneling erase operation.Though this design may have good erasing speed, this data is preserved very poor, partly be because directly tunnelling can just can be brought out under a low intensive electric field, and this low intensive electric field may exist for during preserving attitude at a memory component.

Another NVM design is to be the nitride charge storing memory, and it utilizes a thick tunnel oxide to run off during the preservation attitude to prevent electric charge.Yet a thick tunnel oxide may reduce the passage erasing speed.Therefore, tunnelling hot hole (BTBTHH) method for deleting between band and the band can be used to injected hole with the payment electronics.Yet this BTBTHH method for deleting may bring out some reliability subject under discussion.For example, adopt the characteristic of the nitride charge storing memory element of BTBTHH method for deleting may deterioration after program many times/wipe the Xun ring.

In addition, the technology that lamination number layer memory array listed on the single integrated circuit is developed, to satisfy the demand to high-density nonvolatile memory.

So, preserve performance and speed service speed for can and having the improvement data by multi-pass operation (program/wipe/read), be suitable for and be implemented in the nonvolatile memory designs and the array of membrane structure and stack-up array in addition again, this field is to have suitable demand.

Summary of the invention

The invention relates to be formed at insulating barrier cover silicon substrate and similarly the nothing on the insulation system connect the thin film memory cell of face, and connect the face memory cell about the nothing of lamination.One integrated circuit memory element is to be described, and it comprises the semiconductor main body, and it is formed on the insulating barrier, for example covers on the silicon substrate in insulating barrier; A plurality of grids, its be tandem sequence be formed on this semiconductor body, these a plurality of grids comprise a first grid in this tandem sequence and the most last grid between this tandem sequence, it has insulating component, and this insulating component is separated the interior grid of this tandem sequence interior contiguous grid of tandem sequence therewith; And a charge storing structure is on this semiconductor body, this charge storing structure comprises dielectric charge and catches, it is positioned under two grids of a plurality of grids of this tandem sequence at least, and this charge storing structure comprises one and is placed on tunnelling dielectric structure, on this semiconductor body and is placed on electric charge storage layer and on this tunnelling dielectric structure and is placed on insulating barrier on this electric charge storage layer.Wherein this semiconductor body is included in a continuity, the multiple-grid utmost point passage area under these interior a plurality of grids of this tandem sequence.This multiple-grid utmost point passage area may be n type or p type conduction type.

One embodiment of the invention comprise a plurality of memory cell, and it comprises: semi-conductive substrate has the one source pole zone and the drain region that are positioned under this substrate and are separated by a passage area; One tunnelling dielectric structure, it is placed on this passage area, this tunnelling dielectric structure has a tunneled holes energy barrier height at the interface between the semiconductor body therewith, and is being less than position this tunneled holes energy barrier height on this interface away from this tunneled holes energy barrier height at the interface.One tunnel dielectric layer, it comprises a sandwich construction, and the one deck that comprises semiconductor body contact therewith reaches one deck at least, and it has the tunneled holes energy barrier height of a tunneled holes energy barrier height less than this layer that contacts with this semiconductor body.One electric charge storage layer, it is to be placed on this tunnelling dielectric structure; One insulating barrier, it is to be placed on this electric charge storage layer; And a gate electrode, it is to be placed on this insulating barrier.

Another embodiment of the present invention comprises memory cell, and as connecing the comparison of face embodiment with nothing, it comprises semi-conductive substrate, an one source pole zone and a drain region that this Semiconductor substrate has under the surface that is placed on this substrate and separated by a passage area; One dielectric multilayer tunneling structure, it is placed on this passage area, and this dielectric multilayer tunneling structure comprises one deck at least, and it has the hole energy barrier height of a tunneled holes energy barrier height less than the layer that contacts with this Semiconductor substrate; One electric charge storage layer, it is placed on this dielectric multilayer tunneling structure; One insulating barrier, it is placed on this electric charge storage layer; And a gate electrode, it is placed on this insulating barrier.

In some preferred embodiment, provide the layer of a little tunneled holes energy barrier height may comprise some material, for example a silicon nitride (Si ₃N ₄) or hafnium oxide (HfO ₂).In some preferred embodiment of the present invention, memory cell comprises a tunnelling dielectric structure, and it has multilayer, for example the three-decker of the dielectric oxidation silicon-silicon nitride of a lamination and silica (ONO).This type of tunnelling dielectric structure provides a SONONOS (silicon-oxide-nitride--oxide-nitride thing-oxide-silicon) or superlattice SONONOS design.

In some preferred embodiment of the present invention, this tunnelling dielectric structure can comprise at least two dielectric layers, and it respectively has a thickness that is about 4 nanometers.In addition, in some preferred embodiment of the present invention, this gate electrode comprises a material, and it has a work function value, and it is greater than the work function value of N+ polysilicon.

In some preferred embodiment of the present invention, this tunnelling dielectric structure can comprise one deck, it comprises the material with little tunneled holes energy barrier height, and wherein this material is to occur with a concentration gradient in this layer, and this concentration of material is that a degree of depth is a maximum in this layer.

According to one or embodiment described above, the present invention also comprises non-volatile memory device, and it comprises a plurality of memory cell (that is an array).As using at this, one " a plurality of " are meant more than two or two.According to the present invention, the operating characteristic of memory element has suitable improvement, comprises the erasing speed of increase, and the electric charge of improvement is preserved and bigger operating space.

The present invention also comprises the method for a kind of non-volatile memory cells of operation and array.Comprise by using a self-convergence method to reset of the Vt distribution of this memory component according to method of operation of the present invention with this memory component of limit; Inject with at least one memory component of sequencing by passage+FN; And by applying a voltage to read at least one memory component, wherein this voltage is in an erase status value and a sequencing state value between this memory.As used at this, this words " limit " is meant dwindling that this critical voltage distributes in the many memory cell in an array.Usually, critical voltage distributes by the critical voltage of " limit " many memory cell in a narrow and small scope, so the operation of array is modified and is better than traditional design.For example, in some preferred embodiment, for example at a NAND array, according to one of the present invention or embodiment described above, it comprises memory cell, and it is in the scope of 0.5V that the critical voltage of this various memory cell is represented in the critical voltage distribution of one " limit ".Adopt the array architecture of memory cell at other, according to the present invention, the critical voltage of this " limit " distributes may have the scope that is about 1.0V by the upper limit to lower limit.

Method of operation according to one embodiment of the invention comprises operation an array, its be reset by applying oneself convergence/erasing voltage is to the substrate that will be reset/wipe and in the gate electrode of each memory cell, according to the present invention; The a plurality of at least memory cell of sequencing; And read at least one memory cell, by apply one between an erase status value of memory component and the voltage between the sequencing state value on this memory component.

The present invention also comprises the method that forms a kind of memory cell, and it comprises: a kind of Semiconductor substrate is provided, and it has a source electrode and a drain region, and separate down and by a passage area on its surface that is formed on this substrate; Form a kind of tunnelling dielectric structure on this passage area, wherein form this tunnelling dielectric structure and comprise at least two dielectric layers of formation, wherein one of these at least two dielectric layers has a little tunneled holes energy barrier height, and it is less than the tunneled holes energy barrier height of other dielectric layer; Form an electric charge storage layer on this tunnelling dielectric structure; Form an insulating barrier on this electric charge storage layer; And form a gate electrode on this insulating barrier.

According to there not being an embodiment who connects surface technology, a kind of semiconductor structure comprises a plurality of first semiconductor body zones and covers on the silicon substrate in an insulating barrier, and the feature in a plurality of first semiconductor body zones is for having first concentration of one first doping attitude.One first selection wire and one second selection wire are covered in and generally perpendicular to the first semiconductor body zone.A plurality of first word lines are between first selection wire and second selection wire, and each a plurality of first word line covers a passage area and generally perpendicular to the first semiconductor body zone on each first semiconductor body zone.Wear energy barrier then for one first, one first electric charge storage layer, and one first dielectric layer is at each first word line and in each first semiconductor body zone between the corresponding passage area.At least one first area is to be positioned at each first semiconductor body zone.Contiguous first selection wire in this at least one first area or second selection wire.The feature of this at least one first area is to have the second doping attitude.More than one second area is to be positioned at each first semiconductor body zone, each second area is between two adjacent passage area, the feature of the second area that these are one or more is one second concentration with first doping attitude, and wherein second area is to connect face for nothing.

According to an embodiment of this SOI technology, this semiconductor structure further comprises vicinity and is parallel to a plurality of irrigation canals and ditches structures in the first semiconductor body zone, and each irrigation canals and ditches structure divides the first adjacent semiconductor body zone of next but two.

According to an embodiment of this SOI technology, the first tunnelling energy barrier comprises one deck first oxide layer, one deck nitration case and one deck second oxide layer.

According to an embodiment of this SOI technology, the first tunnelling energy barrier, first electric charge storage layer and first dielectric layer are to be a kind of ONONO structure.

According to an embodiment of this SOI technology, this soi structure comprises an oxide layer on the substrate and under the first semiconductor body zone.

According to an embodiment of this SOI technology, the first area extends under at least one first selection wire and second selection wire.

According to an embodiment of this SOI technology, this semiconductor structure is by lamination and provide the nothing of multilayer to connect the face memory cell, so it further comprises: one second insulating barrier is on first word line.A plurality of second semiconductor body zones, it has one the 3rd concentration of the first doping attitude, is to be covered on second dielectric layer.A plurality of second word lines are that second word line, the 3rd selection wire and the 4th selection wire are to be approximately perpendicular to the second semiconductor body zone between one the 3rd selection wire and one the 4th selection wire.One second tunnelling energy barrier, one deck second electric charge storage layer and one deck second dielectric layer are between second word line and the second semiconductor body zone.This second semiconductor body zone comprises at least one the 3rd zone, its contiguous the 3rd selection wire and the 4th selection wire.The feature in this at least one the 3rd zone is to have the second doping attitude.This second semiconductor body zone also comprises at least one the 4th zone between two second adjacent word lines.This four-range feature is one the 4th concentration with first doping attitude.The size of first area is the size greater than the 3rd zone.

Connect among the face embodiment for the nothing at lamination, specifically, this bottom may be implemented on a SOI substrate, or directly is implemented in a semiconductor substrate region, and none overlapping insulating barrier.

According to another embodiment in the technology of this exposure, a kind of method that is used to form semiconductor structure, it comprises and forms a plurality of first semiconductor body zones, and its one first concentration with first doping attitude is implanted in a substrate.One first selection wire, second selection wire and a plurality of first word line are formation and are approximately perpendicular to the first semiconductor body zone that a plurality of first word lines are to be arranged between first selection wire and second selection wire.One first tunnelling energy barrier, one deck first electric charge storage layer and one deck first dielectric layer are to be formed between first semiconductor body zone and a plurality of first word lines.First dielectric side walls is to be formed on the sidewall of the sidewall of first selection wire and second selection wire, forms first dielectric material between two first adjacent word lines.First source/drain connects face, and it has the second doping attitude, by utilizing first dielectric side walls to plant shielding as a cloth, is to be formed at contiguous first selection wire and second selection wire.A zone is to be formed between two first adjacent word lines.Zone between the first adjacent word line has one second concentration of the first doping attitude, and wherein the zone between two adjacent first word lines is to be roughly not have the face that connects.

According to an embodiment of some application, be to provide a method at this, it is used to operate semiconductor structure.This semiconductor structure comprises: a plurality of semiconductor bodies zone is positioned at a substrate; A plurality of word lines are between one first selection wire and one second selection wire, and this word line comprises word line and a plurality of word line of choosing of not choosing, word line, first selection wire and second selection wire, and it is to be approximately perpendicular to the semiconductor body zone; And tunnelling energy barrier, one deck electric charge storage layer and an one dielectric layer are between word line and semiconductor body zone, wherein the semiconductor body zone comprises at least one first area, it is adjacent to first selection wire and second selection wire, and second area, it is between the word line of two vicinities, wherein the first area has a doping content, and this doping content is higher than the doping content at second area, and wherein at least one second area is to connect face for nothing.The method comprises and applies one first voltage to the first selection wire and second selection wire; Apply one second voltage to word line, first voltage is to be higher than second voltage; And apply a tertiary voltage to the semiconductor body zone to reset semiconductor structure, tertiary voltage is to be higher than second voltage.

As using at this, words " little tunneled holes energy barrier height " is the value of general reference less than the tunneled holes energy barrier height at a silica/silicon interface.In addition, under preferable situation, a little tunneled holes energy barrier height is less than about 4.5eV.Under better situation, a little tunneled holes energy barrier is to be less than or equal to 1.9eV.

Do not have for one of the three-dimensional flash memory that can fold multilayer that to connect face TFT NAND element be to be suggested.This TFTNAND does not have diffused junction (for example N+ mixes and connects face) in this memory array.Diffused junction is only to make outside this array is selected transistor BLT and SLT.

During the space between each word line very little (for example, the space of-75 nanometers), an inversion layer will be brought out by the wordline edge electric field.This nothing connects face TFT enable nand gate and can avoid behind the heat budget that repeats, and it is breakdown that this connects face.Short-channel effect can also be suppressed.So this technology allows the TFT enable nand gate that the lamination of multilayer is arranged, and reaches very high density.

Three-dimensional flash memory has caused widely recently to be noted.The 3-dimensional multi-layered lamination of memory can allow higher density compared with traditional single layer of memory element.

Traditional doping connects face (for example N+ mixes and connects face) and have sizable horizontal proliferation after heat treatment.This horizontal proliferation is very serious for extremely short pass element.Have for the multilayer laminated three-dimensional quickflashing TFT NAND element for one, it is more serious that this short-channel effect will become.Connect the horizontal proliferation of face because bottom is subjected to bigger heat budget and cause serious puncture, it shows serious deterioration short-channel effect.

This nothing described herein connect face NAND allow multilayer laminated and the face that connects only in this array boundary diffusion, it provides bigger heat budget process range to puncture avoiding.

Be that with the traditional element difference this connects face is to be formed at before this sidewall, a kind of being used to made the method that this nothing meets face TFT NAND, is included in sidewall between word line and is formed the back and forms this and connect face.Sidewall between each word line is fully to be filled and non-notch, and it is the therefore little spacing of TFT NAND array.Therefore, meet face IMP and intercepted, and the face that connects is to be formed outside array by of the sidewall in memory array.

An extra mask is to be used in other method, and it is covered in word line and BLT and SLT, and the face IMP of connecing is performed.

Simulation result represents that an inversion layer can be brought out under sidewall, and it is the fringe field because of the high electric field on word line, so do not need to make the n+ doped regions.

Aforementioned described element also comprises p passage TFT NAND, and wherein n type well and P+ connect face and be used.

Description of drawings

Be further to disclose concrete technology contents of the present invention, below in conjunction with embodiment and accompanying drawing describes in detail as after, wherein:

Fig. 1 a and Fig. 1 b are that it is represented a N passage memory cell and represents a P passage memory cell according to one embodiment of the invention respectively according to one embodiment of the invention for cross section summary icon;

Fig. 2 is critical voltage (charge-trapping ability) icons for a tunnelling dielectric structure according to one embodiment of the invention in various program technics.

Fig. 3 is a icon for the critical voltage of an individual SONONOS memory cell according to the embodiment of the present invention when the erasing time.

Fig. 4 is a icon for the critical voltage of a SONONOS memory cell according to the embodiment of the present invention when the holding time.

Fig. 5 a-Fig. 5 e is that energy band diagram for ONO tunnelling dielectric structure is according to the various embodiment of the present invention.

Fig. 6 is for for the tunneled holes electric current of the three kinds of different tunnelling dielectric structures icon to electric field strength.

Fig. 7 a be for a memory cell in the icon of wiping after various types of program according to one embodiment of the invention.

Fig. 7 b is that icon for the critical voltage of a memory cell when wiping with platinum grid is according to one embodiment of the present of invention.

Fig. 7 c and Fig. 7 d are the electric capacity of the memory cell of mentioning for Fig. 7 b icon to voltage.

Fig. 8 be for a memory cell at the icon of the critical voltage after most times programs/wipe the Xun ring under each operational circumstances according to one embodiment of the present of invention.

Fig. 9 is for for the memory cell of the foundation one embodiment of the present of invention icon that concerns at a Xun phase and 1000 cycle after-current-voltages (IV).

Figure 10 be for the memory cell of foundation one embodiment of the present of invention in repeatedly program/the wipe embodiment that Xun encircles the critical voltage under a kind of program and erasure case.

Figure 11 is for quickening to preserve the change of the critical voltage of testing a memory cell in VG according to one embodiment of the present of invention.

Figure 12 a and Figure 12 b be respectively the equivalence circuit diagram and layout, for one virtually memory cell array according to one embodiment of the present of invention.

Figure 13 be by one virtually memory cell array captured it along line 12B-12B and be same as 12b and represent according to one embodiment of the present of invention.

Figure 14 a and Figure 14 b are that the circuit icon for the memory array equivalence comprises memory cell according to one embodiment of the present of invention and describe reseting of being fit to/erasing voltage according to two operation embodiment of the present invention.

Figure 15 a and Figure 15 b are that it comprises memory cell it is described according to a kind of program technic of the present invention according to one embodiment of the present of invention for the circuit diagram of memory array equivalence.

Figure 16 a and Figure 16 b are that it comprises memory cell according to the described a kind of method that reads of one embodiment of the present of invention for memory array.

Figure 17 be for the critical voltage of a memory cell according to one embodiment of the present of invention in various program/wipe Xun ring.

Figure 18 be for the icon of the critical voltage of a memory cell according to one embodiment of the present of invention in repeatedly program/wipe Xun ring.

Figure 19 a and Figure 19 b respectively are described in a logarithm scale and a linear scale according to one embodiment of the present of invention in various grid voltage for the drain electrode in electric current in a memory cell.

Figure 20 is for comprising according to an equivalent circuit diagram of an array of memory cell of the present invention method according to one of the described a kind of program of one embodiment of the present of invention.

Figure 21 a and Figure 21 b be for a layout icon of a virtual ground array and equivalent electric circuit icon according to one embodiment of the present of invention.

Figure 22 a and Figure 22 b be respectively an equivalent circuit diagram and layout for a NAND memory cell array according to one embodiment of the present of invention.

Figure 23 a and Figure 23 b are that the memory cell array for a NAND of cross-sectional icon representation captures from line 22A-22A and 22B-22B represented as being same as Figure 22 b respectively according to one embodiment of the present of invention.

Figure 24 a describes according to a kind of method of operation of the present invention according to one embodiment of the present of invention for the equivalent circuit diagram of a NAND array.

Figure 24 b is that it has different initial threshold voltage for two memory cell according to one embodiment of the present of invention for an icon in the critical voltage of reseting the operating time.

Figure 25 is that it describes a kind of method of operation according to embodiments of the invention for an equivalent circuit diagram.

Figure 26 be icon for the critical voltage of a memory cell according to one embodiment of the present of invention behind various erase status.

Figure 27 describes a kind of method of operation according to embodiments of the invention for an equivalent circuit diagram.

Figure 28 be icon for the critical voltage of a memory cell according to one embodiment of the invention behind various erase status.

Figure 29 a and Figure 29 b are that it is described in a logarithm scale and a linear scale respectively in three kinds of different Xun number of rings in various grid voltage according to one embodiment of the present of invention for the icon in the drain current of a memory cell.

Figure 30 be icon for the critical voltage of memory cell according to one embodiment of the present of invention after being stored in three kinds of different temperature and Xun ring status.

Figure 31 represents that for a cross section NAND array word line is according to one embodiment of the present of invention; And

Figure 32 represents a NAND array word line for a cross section to form technical basis one embodiment of the present of invention.

Figure 33 arranges for several program bias voltages for critical voltage has an ONO tunnel dielectric layer to this nMOSFET of number of a nMOSFET program spike.

Figure 34 is the variation diagram for the time of negative current being pressed for the voltage of an electric capacity with an ONO tunnelling dielectric insulator.

Figure 35 restrains the figure of critical voltage for the erase gate pole tension for the oneself.

Figure 36 is the endurance of an expression memory cell described here, and it utilizes element according to one embodiment of the invention of high-temperature baking.

Figure 37 be shown in smooth change with voltage to the erasing time its for-FN program bias voltage class in a element according to one embodiment of the invention.

Figure 38 be shown in smooth change with voltage to program time its for+FN program bias voltage class in a element according to one embodiment of the invention.

Figure 39 represents the P/E Xun ring endurance of an element according to an embodiment.

Figure 40 represents the preservation survey formula of the acceleration of an element according to an embodiment.

Figure 41 is shown in an element of room temperature and high temperature and preserves in the electric charge of charge-trapping nitrogenize N2.

Figure 42 describes the erasing characteristic according to the element of the different size of embodiment.

Figure 43 describes the erasing characteristic according to the element of the various grid materials of embodiment.

Figure 44 is the part of its expression of a summary top view for an example memory array of film charge capturing memory array.

Figure 45 is that it is captured along the nodel line from Figure 44 for the some of an example array of a thin-film transistor charge capturing memory for its expression of a cross-sectional figure of summary.

Figure 46 A and Figure 46 B represent that for the cross-sectional figure of summary it is the nodel line 3-3 acquisition along Figure 44 for an example semiconductor structure of thin-film transistor charge capturing memory.

Figure 46 C represents that for a cross-sectional figure of summary it plants alloy in the semiconductor body zone in order to cloth for an example technology of thin-film transistor charge capturing memory.

Figure 47 represents some for the laminated construction of an example of a thin-film transistor charge capturing memory for a cross-sectional figure of summary.

Figure 48 be for a cross-sectional figure of summary represent for an example technology of a thin-film transistor charge capturing memory its in order in a semiconductor body zone, to produce an inversion layer.

Figure 49 A-Figure 49 B is the electron concentration that nothing that table emulation is implemented on the example of a thin-film transistor charge capturing memory meets face BE-SONOS NAND.

Figure 50 is the initial IV curve that record of expression for the n pass element of the example of a thin-film transistor charge capturing memory.

Figure 51 represents that a heavier well doping content can increase the Vt that this nothing connects bin spare.

Figure 52 A-Figure 52 B be describe respectively for a thin-film transistor charge capturing memory body+FN ISPP program and-FNISPP wipes.

Figure 53 be example p channel B E-SONOS NAND of expression its have similar this N channel B E-SONOS NAND laminated construction its be to be described in the 50th above-mentioned figure.

Figure 54 A be for critical voltage to the mapping of programm voltage for one-FNISSPP program.

Figure 54 B is expression for the mapping to critical voltage of+erasing time that FN wipes.

Figure 55 is the mapping of expression for the endurance of the example n pass element of a thin-film transistor charge capturing memory.

Figure 56 represents the mapping for the IV curve of the example TFT BE-SONOS element of thin-film transistor charge capturing memory

Figure 57 is expression does not have the analogous diagram that connects bin spare for different scientific and technological nodes of having of a thin-film transistor charge capturing memory (F is half spacing of polycrystalline) and example with identical space (S=20 nanometer).

Aforesaid brief introduction, and following details description of the present invention can use the additional icon that continues with clearer understanding.As describing purposes of the present invention, be in this demonstration at present preferable icon execution mode.Yet should be appreciated that the present invention should not be restricted to the layout of arrangement accurately and indication of this demonstration.

Embodiment

The present invention and at present preferred embodiment be will make details at this description with document for referencial use, its example is to be described at additional icon.Wherein may identical or similar reference number be to be used to this icon and this describes to indicate same or analogous part.What should note non-curve chart partly is for one by the icon after considerably simplifying and be not to have scale accurately.With reference to disclosing at this, only be for facility and succinct, the words of direction, for example be used to indicate the additional icon top, bottom, the left side, the right, top, below, on, under, it descends, reaches thereafter the front portion.This direction words, it is with connecting the description of following icon, should not be understood that it may be set in the additional application range clearly in order to limit scope of the present invention by any way.Though disclose to be meant some described embodiment at this, it should be understood, these embodiment are by in the mode of example but not disclose in the mode of limit.Should be appreciated that and understand processing step described herein and structure and do not cover for the complete technology of making complete integrated circuit.The present invention can be employed and be implemented on various integrated circuit processing techniques, and field is known or be used as the usefulness of development for this reason for it.

According to the present invention, memory cell can overcome the subject under discussion of some reliability of SONOS and nitride charge storing memory element.For example, memory cell structure according to the present invention, can allow FN passage method for deleting fast, simultaneously, still has good electric charge storage configuration.Therefore according to the present invention, the various embodiment of this memory cell also can alleviate the dependence to the BTBTHH method for deleting, avoids element in repeatedly sequencing/wipe Xun ring back deterioration.

In the tunnelling dielectric structure was embodiment for sandwich construction, an example may adopt a ultra-thin tunnel dielectric layer or super thin oxide layer to cooperate little tunneled holes energy barrier height, and it can provide preferable stress to exempt.Behind repeatedly sequencing/wipe Xun ring, can have only slight deterioration according to nonvolatile memory cell of the present invention.

A n passage or a p channels designs be can adopt according to memory cell of the present invention, Fig. 1 a and 1b for example are shown in.According to one embodiment of the invention, Fig. 1 a describes a n passage memory cell 100 1 cross sections diagram.This memory cell comprises a p type substrate 101, and it comprises at least two n doped region 102﹠amp; 104, each doped regions 102﹠amp wherein; 104 effect can be one source pole or drain electrode, looks closely the voltage that applies and decides.As shown in Figure 1a, for the purpose of reference, doped regions 102 can be used as this source electrode and doped regions 104 can be used as this drain electrode.This substrate 101 further comprises a passage area 106 between these two n doped regions.On this passage area 106,, be to be a tunnelling dielectric structure 120 in the surface of this substrate 101.In some preferred embodiment, this tunnelling dielectric structure 120 can comprise one three layers film ONO structure, and one of them little tunneled holes energy barrier height nitration case 124 is to be clipped in a thin suboxides layer 122 and a thin high oxidation layer 126.This memory cell 100 further comprises a charge-trapping (or Charge Storage) layer 130, it is silicon nitride preferably, on this tunnelling dielectric structure 120, and be placed on an insulating barrier 140 on this electric charge capture layer 130, it preferably comprises one and intercepts oxide.One grid 150 is to be placed on this insulating barrier 140.

Fig. 1 b, according to one embodiment of the invention, it describes a drawing in side sectional elevation of a p passage memory cell 200.This memory cell comprises a n type substrate 201, and it comprises at least two p doped regions 202﹠amp; 204, each doped regions 202﹠amp wherein; 204 may do as source electrode or drain electrode.This substrate 201 further comprises a passage area 206 between these two p doped regions.This p passage memory cell 200 also comprises a tunnelling dielectric structure 220, it comprises one three layers thin ONO structure, wherein a little tunneled holes energy barrier height nitration case 224 is to be sandwiched in a thin suboxides layer 222 and a thin high oxidation layer 226, one charge-trapping (or Charge Storage) layer 230, one insulating barrier 240, and a grid 250.

Therefore, for example, as be same as described in Fig. 1 a and Fig. 1 b, can comprise according to memory cell of the present invention: a plural layers tunnelling dielectric structure, comprise one first silicon oxide layer O1, one first silicon nitride layer N1, and one second silicon oxide layer O2; One electric charge storage layer, for example one second silicon nitride layer N2; And an insulating barrier one the 3rd silicon oxide layer O3 for example, on a substrate, semi-conductive substrate (a for example silicon substrate) for example.This tunnelling dielectric structure allows hole when operation is wiped/reseted to one of this memory component, from substrate tunnelling electric charge storage layer so far.Preferably, have a negligible charge-trapping efficient in this tunnelling dielectric structure of a non-volatile memory cells of the present invention, and be more preferably, when memory bank is operated, do not catch electric charge fully.

The material of electric charge storage layer is a silicon nitride layer, HfO for example ₂And Al ₂O ₃The material that also can in a tunnelling dielectric structure, be used as for this reason little tunneled holes energy barrier height layer.In some preferred embodiment of the present invention, an effective charge storage material, for example a silicon nitride can be used as an electric charge storage layer of this memory component.One intercepts oxide, and it prevents charge loss, is to be used as an insulating barrier, for example one the 3rd silicon oxide layer O3.This memory cell also comprises a grid or gate electrode according to the present invention, and a polysilicon gate for example is on this insulating barrier.This tunnelling dielectric structure, electric charge storage layer, insulating barrier and gate pole can be formed on the some of at least one passage area of this substrate, and passage area is by the one source pole zone and a drain region is defined and between wherein.

Comprise a tunnelling dielectric structure according to the memory cell of various embodiment of the present invention, this tunnelling dielectric structure is under a negative gate bias (Vg), and for example a pact-10 can provide the quick FN erasing speed of about 10msec to the Vg of-20V.On the other hand, this electric charge holding capacity still can be kept, and in some example, more is better than many traditional SONOS elements.Memory cell also can avoid bringing to the hot hole erase operation according to the present invention, and it is normally used for nitride charge storing memory element.Avoid bringing to the hot hole erase operation and can eliminate the infringement that hot hole brings out in large quantities, and avoiding of this infringement is to wish to get for us.

Please refer to Fig. 2, it is according to one embodiment of the invention, experimental measurement for the critical voltage of a tunnelling dielectric structure shows that a ultra-thin O1/N1/O2 structure can have a negligible capturing efficiency, and it can be verified by the unaltered critical voltage value under continuous program pulse.The example of being tested in Fig. 2, this O1/N1/O2 layer has thickness 30/30/35 dust respectively.As shown in Figure 2, in the carrying out of using many distinct program methods repeatedly under the situation of sequencing, promptly-the FN sequencing ,+FN sequencing and channel hot electron (CHE) sequencing, what this critical voltage Vt was stable maintains about 1.9 volts.Therefore, this ultra-thin O1/N1/O2 film perhaps can be used as the tunnelling dielectric structure of a band gap engineering, and it is to be for negligible because of charge-trapping has in the structure of 30 dusts or littler nitration case at this.In the result of various electric charge method for implanting, wherein these methods comprise CHE ,+FN and-FN, point out that all negligible hole catches.Manufacture process or component structure can be designed as to have minimized interface and catches, so O1/N1 and the N1/O2 interface is neither activates.

Fig. 3 describes the erasing characteristic of a memory cell, and wherein this memory cell is to have SONONOS design according to one embodiment of the invention.This memory cell in Fig. 3 among this embodiment comprises n-MOSFET design, and it has an ONO tunnelling dielectric structure, and it has the thickness of 15/20/18 dust respectively.This memory cell of the present invention comprise have a thickness be about 70 dusts a silicon nitride electric charge storage layer, have the grid that a thickness is about an insulating oxide silicon of 90 dusts and comprises arbitrary suitable electric conducting material, for example, the polysilicon that n mixes.With reference to figure 3, FN wipes and may be able to reach fast, for example reaches in 10 milliseconds, and may obtain an excellent self-convergent erase characteristic.

Fig. 4 describes the electric charge preservation characteristics according to the SONONOS element of an embodiment of a memory cell, and wherein this memory cell is according to the description of the present invention in Fig. 3.If as shown, this preservation characteristics can be better than traditional SONOS element, and with strength ratio, may be better than a plurality of orders of magnitude.

Fig. 5 a and Fig. 5 b are energy band diagram, and it is described to use and comprises at least one possible effect of a tunnelling dielectric structure with a little tunneled holes energy barrier height layer.This tunnelling dielectric structure is three layers of O1/N1/O2 in this example, energy band diagram be to be shown in Fig. 5 a.Directly tunnelling as herewith the point-like arrow is represented, can be eliminated under low electric field, therefore can provide good electric charge holding capacity when preservation state.On the other hand, energy band diagram is under a high electric field, and is represented as Fig. 5 b, can reduce the energy barrier effect of this N1 and O2, and the direct Tunneling of therefore passing O1 may take place.Tunnelling dielectric structure with at least one little tunneled holes energy barrier height layer can allow effective FN erase operation.

Fig. 5 c and Fig. 5 d are described in another group energy band diagram of an example.In an example, preferable can be with the compensation situation for one, the thickness of this N1 may be greater than O1.The energy band diagram of this valence band is to retouch to be formed on identical electric field E ₀₁=14MV/cm.According to approximate this tunnelling probability of WKB is that the shadow region is relevant therewith.In some example, under the situation for thickness N1=O1, this can also cover the energy barrier of O2 by halves with compensation.On the other hand, for the situation of thickness N1＞O1, this can be with compensation can cover O1 more easily.Therefore, for the situation of thickness N1＞O1, this tunneled holes electric current may be bigger under the identical voltage of O1.

One measures and the experiment of the tunneled holes electric current of emulation, as is same as shown in Figure 6ly, further describes according to the tunneled holes of some embodiment of the present invention and crosses a tunnelling dielectric structure.For example, the flow through tunneled holes electric current of this O1/N1/O2 may fall between the tunneled holes electric current of flow through a ultrathin oxide and a thick oxide.In one embodiment, under a high electric field, the tunneled holes electric current of the O1/N1/O2 that flows through may be similar to the thin oxide layer of flowing through.Yet under a low electric field, this direct Tunneling can be suppressed.As being same as shown in Figure 6ly, the tunneled holes electric current can even be passed a thin oxide layer by detecting when having only the low electric field strength of 1mV/cm.Even at high relatively electric field degree, for example during 11-13mV/cm, the tunneled holes electric current that passes a thick oxide layers also can be left in the basket.Yet it is to approach as same thin oxide layer to this tunneled holes electric current by an ONO tunnelling dielectric structure when high electric field strength.In Fig. 6, because tunneled holes is crossed this big leakage current that a ultrathin oxide brought out and is found in a-quadrant in this figure under low electric field.In Fig. 6, the tunneled holes electric current of the O1/N1/O2 tunnelling of flowing through under high electric field strength dielectric structure is found in B zone in this figure.In Fig. 6, under low electric field, pass the virtual non-existent tunnelling current of an O1/N1/O2 tunnelling dielectric structure and a thick oxide, be found in C zone in this figure.

Design according to memory cell of the present invention may be utilized in various memory form, including but not limited to, NOR and/or NAND type flash memory.

As described above, a tunnel dielectric layer may comprise the layer more than two, and comprises one a little tunneled holes energy barrier height layer may be provided.In an example, this provides the layer of a little tunneled holes energy barrier height may comprise silicon nitride.This layer may be sandwiched in the layer of two silica, therefore if use silicon nitride then to form an O/N/O tunnelling dielectric structure when this middle level.In some preferred embodiment, this bottom can have one and be about 2 nanometers or littler thickness.This middle level and top layer in this tunnelling dielectric structure may have the thickness that is about 1 to 3 nanometer.In an example element, a three-decker may have a bottom, one silica layer for example, and it has the thickness of about 10 to 20 dusts.One middle level, a silicon nitride layer for example, it has the thickness of 10 to 30 dusts, and a top layer, another silicon oxide layer for example, it has the thickness of 10 to 35 dusts.In a certain particular example, an O/N/O three-decker may be used, and wherein this structure has the silica bottom layer of one 15 dusts, one 20 dust silicon nitride middle levels, and one 18 dust silica top layers.In a certain particular example, an O1/N1/O2 three-decker may be used, and wherein this structure has one 13 dust silica bottom layers, one 25 dust silicon nitride middle levels, and one 25 dust silica top layers.

In another example, a thin O/N/O three-decker shows negligible charge-trapping.Theoretical energy band diagram and tunnelling current analysis, for example Fig. 5 a, Fig. 5 b and description shown in Figure 6, can reason out a tunnelling dielectric structure, for example have each layer thickness and be about 3 nanometers or a littler O1/N1/O2 structure, when preservation state, under low electric field, can constrain this hole direct Tunneling.Simultaneously, it also can allow enough tunneled holes under a high electric field.Its reason may be this tunnelling energy barrier that can cover N1 and O2 with compensation effectively.Therefore, the element of this proposition may be able to provide fast tunneled holes wipe, and it does not also have the preservation subject under discussion of traditional SONOS element.Experimental analysis shows excellent endurance and the preservation characteristics of memory cell according to various examples of the present invention.

In some preferred embodiment, this tunnelling dielectric structure comprises at least one middle level and the two adjacent layers on layer both sides hereinto, wherein each middle level and two adjacent layers comprise one first material and one second material, wherein this second material has valence band energy rank, its valence band energy rank and this second material greater than this first material has energy rank, a conduction band, and it is less than the energy rank of the conduction band of this first material.And wherein this second concentration of material of layer is greater than its concentration at this two adjacent layer hereinto, and this first concentration of material of layer is less than its concentration at this two adjacent layer hereinto.Preferably, at a tunnelling dielectric structure of foundation one embodiment of the invention, this first material comprises oxygen and/or oxygenatedchemicals and this second material and comprises nitrogen and/or nitrogen-containing compound.For example, this first material can comprise monoxide, and for example silica, and this second material can comprise mononitride, for example Si ₃N ₄Or Si _xO _yN _z

May comprise three layers or more layer according to the tunnel dielectric layer of the object of the invention, it all can comprise similar element (for example silicon, nitrogen and oxygen), only need have little tunneled holes energy barrier concentration of material, hereinto layer be higher than at it adjacent two-layer.

Some dielectric structure according to previous embodiments of the present invention, this second material can be present in this middle level, wherein this material is to exist with a concentration gradient, this second material hereinto the concentration of layer increase by an adjacent layer/middle bed boundary and so far the degree of depth in the middle level one Cmax is arranged, and begin to be reduced to another adjacent/middle bed boundary by the degree of depth one lower concentration arranged with Cmax.The increase of this concentration and reducing under preferable situation to progressive.

In another embodiment of the present invention, this tunnelling dielectric structure comprises at least one middle level and two adjacent layers in two sides in this middle level, wherein this two adjacent layer comprises one first material and this middle level comprises one second material, wherein this second material has valence band energy rank, it is greater than the valence band energy rank of this first material, and this second material has energy rank, a conduction band, and it is less than the energy rank, conduction band of this first material; And wherein this second material is to be present in this middle level and a concentration gradient is arranged, Ceng second concentration of material is to increase to the degree of depth of a Cmax in this middle level by an adjacent layer/middle bed boundary hereinto, and is reduced to a low concentration in this another adjacent layer/interface, intermediate layer by the degree of depth with Cmax.The increase of this concentration and minimizing are to be progressive generation under preferable situation.Preferably, according to this embodiment of the present invention, in a tunnelling dielectric structure, this first material comprises oxygen and/or monoxide and this second material and comprises nitrogen and/or mononitride.For example, this first material can comprise monoxide, silica for example, and this second material can comprise mononitride, for example Si ₃N ₄Or Si _xO _yN _z

For example, in certain embodiments of the present invention, wherein this tunnel dielectric layer comprises one three layers ONO structure, this bottom oxide and top oxide the layer can comprise silica, and this in the middle of nitride layer can comprise, for example, silicon oxynitride and silicon nitride, wherein the concentration of silicon nitride (that is, having the material of little tunneled holes energy barrier height in the two) is not constant in this layer, is to reach maximum in certain degree of depth between the nitration case with Sanming City smelting structure on the contrary.

Hereinto the layer in this material, it has little tunneled holes energy barrier height, the accurate position that reaches the degree of depth of Cmax does not have decisive influence, only needs it to be positioned at a concentration gradient, and certain degree of depth in this middle level in this tunnel dielectric layer reaches its Cmax.

This concentration of material gradient with little tunneled holes energy barrier height can help promote the various characteristics of non-volatile memory device, especially for the element with a SONONOS or class SONONOS structure.For example, the charge loss of preservation state can be reduced, and the tunneled holes under high electric field can be enhanced, and under possible situation, can be avoided at the charge-trapping of this tunnel dielectric layer.

According to purpose of the present invention, the energy band diagram of one tunnel dielectric layer can be adjusted (band gap engineering), make the valence band energy rank and the conduction band in this middle level not to have a fixed value in rank, but have advantage along with the material concentration that in thickness, changes with little tunneled holes energy rank height by this layer.Referring to Fig. 5 e, according to purpose of the present invention, the ONO three-decker of the tunnel dielectric layer of a band gap engineering is to represent with an energy band diagram.This middle level (the 2nd layer) is to comprise silicon nitride.This skin (the 1st layer and the 3rd layer) is to comprise silicon dioxide.Silicon nitride concentration in the 2nd layer is to float, make valence band can rank and the conduction band can rank, the degree of depth in the 2nd layer when silicon nitride concentration reaches the highest reaches a maximum and minimum value respectively.Three kinds of possible silicon nitride concentration gradients are to be shown in Fig. 5 e, and it is to be represented by dotted lines the variable valence band energy rank and the energy rank, conduction band of being caused by concentration gradient.Shown in Fig. 5 e, represent three kinds of selective silicon nitride concentration maximums in the 2nd layer at the circle on the dotted line, minimum valence band energy rank and the highest conduction band can betide silicon nitride concentration maximum in rank.

According to embodiments of the invention, the tunnelling dielectric structure of multilayer can be made by many diverse ways.For example, a ground floor (silicon dioxide or silicon oxynitride layer) can utilize arbitrary traditional mode of oxidizing to form, including but not limited to, thermal oxidation, free radical (ISSG) oxidation and plasma oxidation/nitrogenize, and chemical vapor deposition method.One middle level, it has the concentration gradient of a SiN, can then be formed, and for example, utilizes chemical vapor deposition method, or, alternatively utilize the pecvd nitride method will be formed at the excessive oxide in this ground floor top or nitrogen oxide is handled.One the 3rd layer, this upper strata oxide layer can then be formed, and for example, utilizes oxidation or chemical vapour deposition (CVD).

One electric charge storage layer can then be formed on this tunnelling dielectric structure.In an example, an electric charge storage layer, it is about 5 to 10 nanometers, can be formed on this tunnelling dielectric structure.In another example, a silicon nitride layer, it is about 7 nanometers or thicker, can be used.This insulating barrier on this electric charge storage layer is about 5 to 12 nanometers.For example, one silica layer, it is about 9 nanometers or thicker, can be used.And this silicon oxide layer can form by a Technology for Heating Processing, and this Technology for Heating Processing is changed the some of a nitration case to form this silicon oxide layer.The multilayer arbitrary known or developed the method that, that it is used to form suitable material described herein can be used to deposition or form tunnel dielectric layer, electric charge storage layer and/or insulating barrier.Suitable method comprises, for example, and hot growing method and chemical gaseous phase depositing process.

In a certain example, a thermal conversion technology may form the interface trap of high density or high concentration, and it can strengthen the capture effect of a memory component.For example, when this grid flow-rate ratio be H ₂: O ₂=1000: during 4000sccm, the thermal conversion of nitride can be brought out when Celsius 1000 spend.

In addition, because silicon nitride has very little (about 1.9eV) hole energy barrier usually, under high electric field, but it is direct Tunneling for the hole.Simultaneously, the gross thickness of a tunnelling dielectric structure, for example an ONO structure may be avoided direct electron tunneling under low electric field.In an example, this asymmetric behavior can provide a memory element, and wherein this memory element not only provides fast tunneled holes to wipe, and the charge loss that reduces or eliminates during preservation also is provided.

One example element can be made by one 0.12 microns nitride charge storing memory technology.Table 1 is shown in the structure and the parameter of element in the example.The tunnelling dielectric structure with a ultra-thin O/N/O that proposes may change the tunneled holes electric current.In an example, the N2 layer of thicker (7 nanometer) may may be as a barrier layer as an electric charge capture layer and an O3 (9 nanometer) layer.N2 and O3 all may be by using the manufacturing of nitride charge storing memory technology.

Table 1

In some embodiment of the present invention, a grid can comprise a material, and the work function of this material is greater than the work function of N+ polysilicon.In some preferred embodiment of the present invention, the grid material of a such high work function can comprise a metal, for example platinum, iridium, tungsten and other noble metal.Under preferable situation, this grid material in this embodiment has the work function more than or equal to about 4.5eV.Under better situation, this grid material comprises a high workfunction metal for example platinum or iridium.In addition, preferable high work function material comprises, but is not limited to, P+ polysilicon, and metal nitride, for example, titanium nitride and tantalum nitride.In the better embodiment of the present invention, this grid material comprises platinum.

In one embodiment of the invention, the example element with a high work function grid material also may be by the manufacturing of 0.12 micron nitride charge storing memory technology.Table 2 is shown in the structure and the parameter of element in the example.The tunnelling dielectric structure with a ultra-thin O/N/O that proposes may change the tunneled holes electric current.In an example, the N2 layer of thicker (7 nanometer) may may be as a barrier layer as an electric charge capture layer and an O3 (9 nanometer) layer.N2 and O3 all may be by using the manufacturing of nitride charge storing memory technology.

Table 2

According to the memory cell with embodiment of high work function grid material of the present invention, with respect to other embodiment, it shows better erasing characteristic.High work function grid material suppressor grid electronics injects catches layer.Among some embodiment in the present invention, wherein memory cell comprises a N+ polysilicon gate, when wiping tunneled holes so far electric charge capture layer be and gate electron injection takes place simultaneously.This self-convergent erase effect causes at erase status higher critical voltage class, but is bad in using for NAND.According to the memory cell of high work function grid material embodiment of the present invention, can be used to various different types of memories and use, for example comprise NOR-and NAND-type memory.Yet this is to be specially adapted to NAND use according to the memory cell of the embodiment of high work function grid material of the present invention, because the lifting critical voltage is bad under the state for wiping/reseting in the NAND application.Memory cell according to the embodiment of high work function grid material of the present invention can be situated between and be wiped by the tunneled holes method, and wherein preferred methods is to be situated between by-FN erase operation.

One example element, it has an ONO tunnelling dielectric structure and a N+ polysilicon gate, can be by traditional SONOS or nitride charge storing memory methodology programs, and can be wiped by passage FN tunneled holes.Fig. 7 a represents the erasing characteristic of an example SONONOS element, and wherein this SONONOS element has an ONO tunnelling dielectric structure in a certain example.With reference to figure 7a, a higher grid voltage causes an erasing speed faster.Because it is also higher that grid injects the dynamic equilibrium point (it determines Vt) that also becomes stronger and cause, it also has a higher saturated Vt.It is shown in the right-hand part of this figure, is about a minimum value of 3 to 5 volts when critical voltage reaches, and wherein minimum value depends on the erase gate pole tension.By variation analysis method at a flash, the curve of its differential map 7a, this tunneled holes electric current of fechtable.The hole current that measurement captured by Fig. 7 a is to be described in above-mentioned Fig. 6.For convenience relatively, the tunneled holes electric current of emulation is to utilize WKB to be similar to describe.This experiment structure be with predict the outcome consistent.By the tunnelling current of this O1/N1/O2 lamination, under high electric field, it is the situation near ultra-thin O1, and closes under low electric field.

Memory cell according to some embodiment of the present invention, it has the high work function grid material, and wherein this high work function grid suppressor grid electronics injects, and the critical voltage of this element is wiped or reseted in one and can become littler under the state, and even be negative value, depend on the erasing time.According to the critical voltage value of the memory component in one embodiment of the invention, wherein grid is to comprise the ONO structure that platinum and tunnel dielectric layer comprise one 15/20/18 dusts, is to be shown in Fig. 7 b.As be same as shown in Fig. 7 b, when one-FN operates, and in a less grid voltage (18V), the smooth energy of this element (it is relevant to critical voltage) with voltage can be set and do to be lower than-3V.The corresponding electric capacity of this element is to be shown in Fig. 7 c to gate voltage values.

Again, the preservation characteristics according to the memory component of the embodiment with high work function grid material of the present invention is to be enhanced.The preservation characteristics of one memory component, wherein this element has a platinum grid, is to be shown in Fig. 7 d, wherein this electric capacity is a function of describing to do grid voltage, wherein this figure be to wipe and sequencing after, each the operation after 30 minutes and 2 hours after the mapping.It is poor to can be observed minimum Times.

Memory cell according to various embodiment of the present invention can be operated under two kinds of different patterns at least.For example CHE sequencing, it has reverse reading (pattern 1), can be used as to realize a 2-position/unit operations.In addition, low-power+FN sequencing (pattern 2) also can be used as a 1-position/unit operations.These two kinds of patterns all can be used identical tunneled holes method for deleting.Pattern 1 can preferably be used as the virtual ground array framework of NOR type flash memory.Pattern 2 can preferably be used as NAND type flash memory.

In an example, Fig. 8 shows that according to the embodiment of the present invention under pattern 1 operation, a virtual ground array framework NOR type flash memory has excellent endurance.This type of has the memory component of a tunnelling dielectric structure and finds no the deterioration of wiping, and is to wipe (Vg=-15V) because of tunneled holes to be uniform passage method for deleting.This corresponding IV curve also is shown in Fig. 9, and it shows that this element still has little deterioration behind P/E Xun ring repeatedly.In an example, it is possible be to exempt characteristic because ultra-thin oxide/nitride layer has good stress.In addition, this memory component is not have the infringement that hot electron brings out.Endurance according to the NAND type flash memory of the embodiment of the present invention under pattern 2 is to be shown in Figure 10.For convergent erase time faster, maybe can use a bigger bias voltage (Vg=-16V).Excellent endurance also can obtain in this example.

Preserving according to the electric charge of the SONONOS element of the example of one embodiment of the invention is to be shown in the 4th figure, and the loss of charge of a 60mV was wherein only arranged after 100 hours.The size that this preservation characteristics improves is to be better than traditional SONOS element to reach a plurality of orders of magnitude.The VG that quickens preserves test and also show that direct tunnelling can be constrained under this low electric field.The VG who quickens that the 11st figure describes for a 10K P/E Xun loop member preserves the example of test.This loss of charge apply 1000 seconds-still very little behind the VG stress, represent that this hole direct Tunneling can be constrained under little electric field.

In view of the above, the design of the SONONOS in the above-mentioned example can provide one fast and the tunneled holes with excellent endurance wipe.As the above, this design can be implemented in NOR and NAND type nitride stores flash memory.In addition, can comprise a plurality of memory components according to a memory array of the present invention with similar or different configuration.

In the various arrays of foundation embodiments of the invention, can be used to traditional nitride charge storing memory or SONOS element in the virtual ground array framework according to memory cell of the present invention.The subject under discussion of this reliability and wipe deterioration is utilized the FN tunneled holes but not hot hole injects, and can be solved or releive.Do not limit this scope of invention under the ad hoc structure of the following stated, according to memory array of the present invention, various methods of operation is to describe the NOR virtual ground array structure of example down below.

CHE or channel hot electron cause injection (CHISEL) sequencing of secondary hot electron and reverse read can be used to 2-position/cell memory array.And this method for deleting or can be a uniform passage FN tunneled holes and wipe.In an example, this array architecture or can be a virtual ground array or a JTOX array.Please refer to Figure 12 a-Figure 20, an O1/N1/O2 three-decker can be used as this tunnelling dielectric structure, have thickness less than the O1 layer of 2 nanometers and have the N1 of about 3 nanometers or littler thickness and the O2 layer so that the direct Tunneling in hole to be provided.With reference to figure 12a-Figure 20, the N2 layer can more be thicker than 5 nanometers so that a high capturing efficiency to be provided.One insulating barrier, O3 can be one silica layer, and it is to form with wet oxidation, and for example a wet type is changed top oxide (silica), so that the big interface of trap density between O3 and N2 to be provided.O3 is about 6 nanometers or thicker in to prevent the loss of charge of silicon oxide layer escape thus.

Figure 12 a and Figure 12 b describe the example of a virtual ground array framework, and it cooperates above-mentioned memory cell, for example has the memory cell of one or three layers of ONO tunnelling dielectric structure.Especially, Figure 12 a describes an equivalent circuit of a storage array part, and Figure 12 b describes the layout of an example of the some of this memory array.

In addition, Figure 13 is described in the cross-sectional figure of summary of many memory cell that cooperatively interact in this array.In an example, bury regional source electrode or the drain region of diffusion (BD) and can be the face that connects that N+ mixes for this memory cell.This substrate can be a p type substrate.In-possible collapse when FN wipes, a thick BDOX (＞50 nanometer) can be used in the example for fear of BDOX (oxide on the BD) zone.

Figure 14 a and Figure 14 b describe the virtual ground array for an example, and its cooperation has 2/element memory cell of aforesaid tunnel dielectric layer design, and possible electronics " is reseted " synoptic diagram.Before carrying out further sequencing/wipe Xun ring, this all elements can " be reseted " through an electronics earlier.One resets process maybe can guarantee the consistency of the Vt of the memory cell in identical array, and promotes the erase status of the Vt of this element to convergence.For example, apply 1 second Vg=-15V, shown in Figure 14 a, can have and inject the effectiveness of some electric charge, to reach the state of a dynamic equilibrium to an electric charge capture layer of silicon nitride.Utilize this to reset, even Chong Dian memory cell anisotropically, for example because the plasma charge effects that is produced during its technology also may make its Vt convergence.Another method that produces a self-converging biasing state is for the bias voltage of grid and underlayer voltage is provided.For example, with reference to figure 14b, maybe can apply Vg=-8 and p type wells=+ 7V.

Figure 15 a and Figure 15 b describe the sequencing synoptic diagram for the virtual ground array of an example, and wherein this array is to cooperate 2/element memory cell with above-mentioned tunnel dielectric layer design.Channel hot electron (CHE) sequencing can be used to this element of program.In the Bit-1 sequencing that 15a figure describes, this electronics is injected the face that the connects edge as for bit line N (BLN) partly.For the Bit-2 sequencing that is shown in Figure 15 b, this electronics is the face that the connects edge that is stored in BLN-1.For the typical sequencing voltage of word line (WL) is to be about 6V to 12V.For the typical sequencing voltage of bit line (BL) is to be about 3 to 7 volts, and this p type well is the situation that can be maintained at ground connection.

Figure 16 a and Figure 16 b describe the synoptic diagram that reads for the virtual ground array of an example, and wherein this array is to cooperate 2/element memory cell with above-mentioned tunnel dielectric layer design.With reference to figure 16a, for reading Bit-1, BLN-1 is applied in the suitable voltage that reads, for example 1.6V.With reference to figure 16b, for reading bit-2, BLN is applied in the suitable voltage that reads, for example 1.6V.In an example, this read voltage can in 1 to 2 volt scope in.Word line and p type well can be maintained under the situation of ground connection.Yet, the mode that reads of other adjustment, for example one promote-Vs reverse read method also can be implemented.For example, one promote-Vs reverse read method maybe can use Vd/Vs=1.8/0.2 reading Bit-2, and Vd/Vs=0.2/1.8 is to read Bit-1.

Figure 14 a and Figure 14 b also describe the block erase icon for the virtual ground battle array example of an example, and wherein this array cooperates and have 2/element memory cell of above-mentioned tunnel dielectric layer design.In an example, utilize the block erase that the passage tunneled holes wipes or can be applicable to wipe in real time this memory cell.In an ONO tunnel dielectric layer of a memory cell, wherein this memory cell has this SONONOS structure, can provide one to wipe fast, and this wipes and can reach and have a self-convergent passage erasing speed about 10 to 50msec.In an example, a block erase operation state can be similar to one " reseting " process.For example, with reference to figure 14a, apply synchronously be about-VG of 15V is in this WL ' s and allow all these BL ' s be all and float and maybe can reach a block erase.And this p type well can keep ground connection.

In addition, with reference to figure 14b, apply pact-8V so far WL ' s and pact+7V so far p type well also can reach a block erase.In some example, one completely block erase operation can be reached in 100msec or in the less time, and do not have any mistake and wipe the memory cell that maybe can't wipe.Above-mentioned element design can be beneficial to provides a passage of the excellent self-convergence property of tool to wipe.

Figure 17 is the erasing characteristic of describing in the example that uses a SONONOS element.The example of one SONONOS element can have the O1/N1/O2/N2/O3 that thickness is about 15/20/18/70/90 dust respectively, and it has a N+ polysilicon gate and thermal conversion top oxide as O3.This erasing speed for various grid voltages is in this demonstration.Has erase operation on the memory cell of O1/N1/O2 tunnel dielectric layer in this, wherein has the multilayer that thickness is about 15/20/18 dust respectively, cause in time less than 50msec, for example in the 10msec, reduce about 2 volts critical voltage, in demonstration-FN erasing voltage in-15 and-17 volts between state under.Higher grid voltage causes an erasing speed faster.

Yet the Vt of this convergence is also higher, is because the grid injection is to become more active under higher grid voltage.Inject in order to reduce grid, the metal gates that P+ polysilicon gate or other have high work function can use as grid material to lower grid injection electronics when wiping replacedly.

Figure 18 is described in the enhancement of the characteristic that use SONONOS element causes in the virtual ground array framework.Be that excellent endurance performance is arranged in some example.This sequencing state is to be Vg/Vd=8.5/4.4V, is 0.1 microsecond and Vg/Vs=8.5/4.6V for Bit-1, is 0.1 microsecond for Bit-2.FN wipe can use about 50msec Vg=-15V to wipe these two synchronously.Because it is to wipe for the oneself restrains uniform channel that FN wipes, can't wipes or cross the memory cell of wiping and can not exist usually.In some example, even the above-mentioned element of carrying shows that excellent endurance is under the situation of not using one sequencing/erasure detection or stage algorithm.

Figure 19 a and Figure 19 b are described in the I-V characteristic of P/E Xun ring in the example.(Figure 19 a) or linear scale (Figure 19 b) is in this expression in log scale for this corresponding I-V curve.In an example, a SONONOS element repeatedly only has very little deterioration performance behind the P/E Xun ring, so subcritical pendulum volt and mutual conductance repeatedly all almost are being equal to behind the Xun ring.This type of SONONOS element has good endurance, and it is better than nitride charge storing memory element.The possible reason of one is that the hot hole injection is not used.In addition, may have better pressure than a thick tunneling oxide as above-mentioned one ultra-thin oxide and exempt characteristic.

Figure 20 describes the CHISEL sequencing summary icon in the example.The method of another this element of sequencing is to use the CHISEL sequencing, and it is to use negative substrate bias to increase hot carrier efficient to strengthen knock-on ionization.The sequencing electric current also can reduce because of body effect.Typical situation is to be described in this figure, wherein substrate be applied in a negative voltage (2V), and this to connect face voltage be to reduce to 3.5V.For traditional nitride charge storing memory element and technology, the CHISEL sequencing because of it may inject more electronics near the channel center zone, and can't be employed.And hot hole is wiped near the electronics the channel center zone that can't remove traditional nitride charge storing memory element effectively.

Figure 21 a and Figure 21 b describe the design of the JTOX virtual ground array in the example.This JTOX virtual ground array is provided at an execution mode that uses the SONONOS memory cell in the memory array.In an example, be to be completely cut off by shallow trench isolation for element in this JTOX structure in the difference of this JTOX structure and a virtual ground ground connection.One typical layout example is to be described in Figure 21 a.Figure 21 b describes a corresponding equivalent electric circuit, and it is the circuit that is equal to a virtual ground array.

As mentioned above, be to be applicable to NOR and NAND type flash memory according to memory cell structure of the present invention.The other example of memory array design and method of operation thereof below will be described.Scope of the present invention is not limited to the ad hoc structure to the following stated, is the example of NAND framework as described below according to the various method of operation of memory array of the present invention.

As mentioned above, n passage SONONOS memory component, it has an ONO tunnel dielectric layer can be used to a memory component.Figure 22 a and Figure 22 b describe the example of a NAND array architecture.Figure 23 a and Figure 23 b describe the cross-sectional figure of the memory array design of model row by two different directions.In some example, the method for operation of a memory array can comprise+the FN sequencing, and-FN wipes, and read method.In addition, circuit operation method also may involved program disturb to avoid taking place in some example.

Outside this single block grid structure design, a grid array that separates, a NAND array for example, it uses the SONONOS element between two transistor gates, and wherein this grid is to place by this regions and source, also can be used.In some example, a gate design possibility minification of separating is to F=30 nanometer or littler.Further, this element can be designed to do to have good reliability, reducing or eliminating this mutual floating grid coupling effect, or is designed to have the advantage of the two.As mentioned above, a SONONOS memory component can provide excellent oneself convergence, or wiping at a high speed, and wherein this wiping at a high speed can help block erase operation and the Vt control that distributes.Further, an erase status that tightens distributes and can be beneficial to multistage application (MLC).

The design that utilizes some to be used for a memory array organization, this effective passage length (Leff) can be increased to reduce or eliminate short-channel effect.Some example can be designed to use no diffused junction, the challenge that provides shallow junction or use sack cloth to plant when therefore avoiding the manufacture process in memory component.

Fig. 1 describes the example of a memory component, and wherein this memory component has SONONOS design.In addition, above-mentioned table 1 description is used in the thickness of different layers and the example of material thereof.In some example, the P+ polysilicon gate can be used to provide low saturated reseting/wipe Vt, and this Vt can inject and be reached by reducing grid.

Figure 22 a and Figure 22 b describe the example of a memory array, a SONONOS-NAND array for example, and it has according to being described in the memory cell of the embodiment of table 1, and has diffused junction.In an example, the element of separation can be by various partition methods, and for example shallow trench isolation (STI) or insulating barrier cover silicon (SOI) technology, by independent separately.With reference to figure 22a, a memory array can comprise a plurality of bit lines, for example BL1 and BL2, and a plurality of word line, for example WL1, WLN-1 and WLN.In addition, this array can comprise source electrode line transistor (or source electrode line is selected transistor or SLTs) and bitline transistor (or bit line selection transistor or BLTs).As the above, this memory cell in this array can be utilized SONONOS design, and this SLT and BLT can comprise n type metal-oxide half field effect transistor (NMOSFETs).

Figure 22 b describes the layout of an example of a memory array, for example a NAND array.With reference to figure 22b, Lg is the passage length for memory cell, and Ls is the distance between the line of each separation of memory component.In addition, W is the channel width for memory cell, and Ws is the bit line of separation or the width of the area of isolation between the regions and source.

Please refer to Figure 22 a and Figure 22 b, this memory component can be connected in series and be formed a NAND array.For example, a string memory component can comprise 16 or 32 memory components, and a string number of 16 or 32 is provided.This BLTs and SLTs can be used as and select transistor to go here and there corresponding NAND to control this.In the Yu Yifan row, can be one silica layer for the gate dielectric of BLTs and SLTs, wherein this silicon oxide layer does not comprise a silicon nitride and catches layer.This type of configuration, though be not essential for various situations, can avoid the contingent Vt skew of BLTs and SLTs this memory array operation under some example.In addition, this BLTs and the SLTs combination that can use the ONONO layer is with as its gate dielectric.

In some model row, this grid voltage that puts on BLTs and SLTs can be less than 10 volts, and wherein this voltage may bring out less grid interference.Gate dielectric in BLTs and SLTs can be recharged or charge-trapping, and extra-Vg wipes the grid that can be applied in BLT or SLT with to its gate dielectric discharge.

With reference to figure 22a, each BLT may be coupled to a bit line (BL).In the Yu Yifan row, a bit line can be a metal wire, its have and STI have identical or roughly the same between distance.Again, each SLT is connected to one source pole line (SL).This source electrode line is to be parallel to this WL and to connect this sensing amplifier that so far is used to read sensing.This source electrode line can be a metal, for example tungsten or polysilicon lines or a N+ diffusing, doping line.

Figure 23 a is a cross-sectional figure, and it describes the memory array of an example, a SONONOS-NAND memory array for example, and this section is the direction along passage length again.Typical Lg and Ls are substantially equal to F, the critical size of F ordinary representation one element (or node).This critical size may change along with technology.For example, the node of 50 nanometers is used in the representative of F=50 nanometer.Figure 23 b describes the cross-sectional figure of an example memory array, and a SONONOS-NAND memory array for example is along the direction of this channel width.With reference to figure 23b, be to approximate or be slightly larger than distance between the channel-length direction greatly in distance between the channel width direction.Therefore, the size of a memory cell is slightly to equal 4F ²/ memory cell.

In the example of making a memory array, for example above-mentioned array, this technology can comprise only uses two main masks or developing process, and for example one is used for polysilicon (word line) and another is used for STI (bit line).Relative, the manufacture method of NAND type floating grid element may need ONO technology between at least two polycrystalline technologies and another polycrystalline.Therefore, the comparable NAND type of the structure of the element that this proposed and technology floating gate memory is simpler.

With reference to figure 23a, in an example, the space (Ls) between word line (WLs) can be formed as having a shallow junction, the shallow junction of N+ doped region for example, and it can be used as the source electrode or the drain region of this memory component.As described in Figure 23 A, extra cloth is planted and/or diffusion technology, and for example an oblique angle sack cloth is planted, and the pocket that can be implemented one or more " pocket " zone to be provided or to connect face extends, and it is contiguous one or more shallow junction zone.In some example, this type of configuration can provide better element characteristic.

Use STI to completely cut off in the example of the memory component that separates at some, can be in the irrigation canals and ditches degree of depth of sti region more greater than the vague and general width in p type well, especially when the face that the connects bias voltage that uses is enhanced.For example, this connects the face bias voltage and may be up to the bit line (bit line of not choosing) that 7V forbids in sequencing when sequencing.In an example, the degree of depth of this sti region can be in the scope that is about 200 to 400 nanometers.

After making a memory array, one resets operation can be implemented earlier to tighten the distribution of Vt.Figure 24 a describes the example of this generic operation.In an example, before other operation beginning, maybe can use VG approximate-7V and VP-well approximate+8V to be to reset this array (pressure drop of VG and VP-Well can distribute so far grid voltage to each WL and p type well).When reseting, BL ' s can be unsteady, or is promoted to the voltage identical with this p type wells.As be same as described in the 24b figure, this resets operation can provide excellent self-convergence property.In an example, even the SONONOS element is to be charged to various Vt values earlier, and this resets operation can " tighten " it to reseting/erase status.In an example, this time of reseting is to be about 100msec.In this example, this memory component can use n passage SONONOS element, and it has the ONONO=15/20/18/70/90 dust, and has a N+ polysilicon of Lg/W=0.22/0.16 micron.

Usually traditional floating grid element is that self-convergent erase can't be provided.What on the contrary, the SONONOS element can be restrained resets/the method for deleting operation.In some example, this operation may become very important, and some technology subject under discussion because initial Vt distributes is for example handled plasma charge effects heterogeneous, be usually one on a large scale in.Oneself's convergence " reseting " of this example has the limit of helping, or the initial Vt distribution of the memory component that narrows.

In the example of a programming operations, this WL that chooses can be applied in a high voltage, and for example one is about+and 16V is to the voltage of+20V, to bring out passage+FN injection.Other can be unlocked to bring out the inversion layer of a string NAND by grid (WL ' s that other does not select).In some example ,+FN sequencing can be a low-power methods.In an example, the bypass procedure method for example has the page programization of 4K Bytes stored parallel unit, can produce the sequencing throughput above 10MB/sec, and total current Xiao Mao can be controlled in the 1mA.In some example, disturb for fear of sequencing at other BLs, one high voltage, for example a voltage that is about 7V can be applied in other BLs, so this reversal potential can be raised to suppress in the pressure drop of the BLs that does not choose (for example memory cell B in Figure 25).

For the example of read operation, this WL that chooses can be promoted to a voltage, and this voltage is between an erase status class (EV) and a sequencing state class (PV).Other WLs can be used as this and " passes through grid ", so its grid voltage can be raised and be higher than PV.In some example, erase operation can aforesaidly be reseted operation, its can allow the oneself converge to identical or roughly the same reset Vt.

Figure 25 describes an example of an operation one memory array.Sequencing may comprise passage+FN electron injection and enter SONONOS nitrogenize seizure layer.Some example may comprise and applies Vg and approximate+WLN-1 that 18V so far chooses, and apply VG and approximate+10V is to other WLs, and this BLT.This SLT can be closed to avoid channel hot electron to be injected to memory cell B.In this example, because all transistors in this string NAND are to be unlocked, this inversion layer is by this string.Further, because BL1 is grounded, has the position standard of null value in this inversion layer of BL1.On the other hand, other BLs is promoted to a high levels, and for example one is about+voltage of 7V, so the inversion layer of other BLs becomes higher.

Especially, for storage unit A, it is a memory cell of doing sequencing for being selected, and this pressure drop is to be about+18V, and it causes+the FN injection.And this Vt can be promoted to PV.For memory cell B, this pressure drop is to be+11V, cause less+FN injection, and the FN injection is quite responsive to Vg.For memory cell C, only be applied in+voltage of 10V, cause and do not have or insignificant+FN injection.In some example, a programming operations is not limited to described technology.That is, other suitable procedureization technology of forbidding also can be applied in.

Figure 24 a, Figure 26 and Figure 27 further describe some example of array processing, and describe the endurance and the preservation characteristics of some example.As described in it, the deterioration of this element after the operation cycle repeatedly can be very little.Figure 24 A describes the erase operation of an example, and it can be similar to one and reset operation.In an example, this erase operation is to be implemented by block or square.As mentioned above, this memory component may have good self-convergent erase speciality.In some example, this wipes saturated Vt may depend on Vg.For example, a higher Vg may cause a higher saturated Vt.As be same as described in Figure 26, this convergence time is about 10 to 100msec.

Figure 27 describes the read operation of an example.In an example, read and can be realized by applying a grid voltage, wherein this grid voltage is between an erase status Vt (EV) and a sequencing state Vt (PV).For example, this grid voltage is about 5 volts.In on the other hand, other WLs and BLT and SLT are applied in a higher grid voltage, and for example one is about+voltage of 9V, to open other all memory cell.In an example, if the Vt of storage unit A is higher than 5V, this reads electric current can be very little (＜0.1uA).If the Vt of storage unit A is less than 5V, this reads electric current can be higher (＞0.1uA).Therefore, this memory state, that is, the information of this storage can be identified.

In some example,, but not too highly disturb to bring out grid for other the passing through grid voltage and should more be higher than this high Vt state or this sequencing state Vt of WLs.In an example, this PASS voltage is in about scope of 7 to 10V.The voltage that applies in BL is about 1V.Though one bigger read voltage and can bring out bigger electric current, this reads interference can become obvious in some example.In some example, this sensing amplifier can be placed on one source pole line (source electrode sensing) or on a bit line (drain sense).

Some example of NAND serial may have 8,16,32 memory components on every string.One bigger NAND string can be saved unnecessary management and increase the efficient of array.Yet in some example, this reads electric current may be littler and interference may become more remarkable.Therefore, should be according to various design, technology, and operation factors is chosen suitable NAND string number.

Figure 28 describes the cycle endurance of some example element.With reference to Figure 28, P/E Xun ring, it has+the FN sequencing and-FN wipes, can be implemented, and this result has good endurance feature.In this example, erase status is to be about in 100msec-16V for Vg.In some example, only need single erasing move, and do not need the checking of state.The scope of memory Vt is good and do not have a situation of deterioration.

Figure 29 a and Figure 29 b are to use different scales to describe the memory component IV feature of this example.Especially, Figure 29 a describes a little deterioration amplitude of oscillation of this element, and Figure 29 b describes a little gm deterioration of this element.Figure 30 describes the preservation feature of the SONONOS element of an example.With reference to Figure 30, a good preservation feature is to be provided and for element operation 10K Xun ring back and after at room temperature placing 200 hours, still to have the loss of charge less than 100mV.

In some example, separated grid design, for example separated grid SONONOS-NAND design can be used as and makes a memory array reach the small size of productive set more.Figure 31 describes the example of this type of design of use.With reference to Figure 31, between each word line, or can be reduced between two these spaces (Ls) adjacent and that share between the memory component of identical bit line.In an example, Ls can be to be reduced to and is about or less than 30 nanometers.As shown in the figure, this memory component, it uses separated grid design can only share an one source pole zone and a drain region along identical bit line.On the other hand, a separated grid SONONOS-NAND array can use no diffusion zone or connect face for some memory component, for example the N+ doped regions.In an example, this design also can reduce or eliminate the demand for " pocket " of shallow junction and vicinity, and wherein pocket may relate to a more complicated technology in some example.More and, in some example, this design is more not influenced by short-channel effect, so passage length increased, is for example risen to Lg=2F-Ls in an example.

Figure 32 describes an example technology of a memory array of using separated grid design.This summary icon is only to be that example is used in a description, and this memory array can be used various method design and manufacturing.With reference to Figure 32, after the material in order to multilayer that this memory component is provided is formed, utilize the silicon monoxide structure to shield firmly as being formed at one on the multilayer, this multilayer can be patterned then.For example, region of silicon oxide can be developed and etching step is defined.In an example, the pattern that is used as definition initial oxidation silicon area can have a width that is about F, and the space between region of silicon oxide is about F, causes one to be about distance between the 2F.After this initial region of silicon oxide was patterned, silicon oxide side wall can then be formed around the zone of patterning, to increase each region of silicon oxide and to dwindle its space.

Please continue with reference to Figure 32, after region of silicon oxide is formed, its can be used as a hard shielding with the layer of definition or its covering of patterning to provide at least one memory component, for example a plurality of NAND strings.In addition, insulating material, for example silicon monoxide can be used to be filled in this space, for example in Ls space shown in Figure 32, between adjacent memory component.

In an example, can be about 15 nanometers to the scope of about 30 nanometers along identical bit line and the Space L s between adjacent memory component.As mentioned above, in this example, this effective passage length can be extended to 2F-Ls.In an example, if F is about 30 nanometers and Ls is about 25 nanometers, Leff is about 45 nanometers.For the operation of these example memory components, grid voltage can be reduced to less than 15V.In addition, the pressure drop of the inside polysilicon between word line can be designed to be not more than 7V, to avoid the sidewall collapse in the Ls space.In an example, it can be reached by having less than the electric field of 5MV/cm between adjacent word line.

For the Leff with diffused junction of traditional NAND floating grid element is to be about half of its grid length.Under the contrast, if F is about 50 nanometers and Leff is about 30 nanometers, in a certain example for the design (this separated grid NAND) of this proposition, Leff is about 80 nanometers.This long Leff can provide preferable element characteristic, because of its reduction or eliminated the impact of short-channel effect.

As mentioned above, separated grid NAND design can further reduce on the same bit lines between adjacent memory unit every the space.Under the contrast, traditional NAND type floating grid element possibly can't provide one little between every because the coupling effect between floating grid may cause the loss of memory permissible range.This inner floating grid coupling be between the interface of adjacent memory unit in the electric capacity between adjacent floating grid when being quite high (be very little in the space of this floating grid cause read interference so the coupling capacitance between adjacent floating grid becomes very high).As mentioned above, this design can be eliminated the demand of making some diffused junction, and if all word lines are when being activated, inversion layer can directly be connected, and therefore, this design can be simplified the technology of memory component.

One is used the multilayer SONOS element of ultra-thin ONO tunnel dielectric layer is to be described.Because of having a n+ polysilicon gate, be about in the example+oneself's convergence forward of 3V wipes critical voltage and reached and be suitable for a NOR framework.Channel hot electron sequencing wherein may be utilized in storing two of every memory cell, can being read and using tunneled holes to wipe by the reverse read method of this standard of use, it is to adopt electric field to assist the FN tunnelling at a grid voltage, for example-15 carries out under volt the situation.Use a p+ polysilicon (or material of other high work function) grid, one depletion-mode element can be obtained, it has minus one and wipes critical voltage and surpass a sequencing critical voltage of 6 volts approximately, and can reach very large memory usable range, applicable to the NAND framework, wherein this framework is to use the FN electron tunneling of electric field assistance to be used as sequencing, and the FN tunneled holes of using electric field assistance is to be used as erase operation, it has a grid voltage when wiping, for example-18 volt.

Figure 33 disturbs bias pulse or wipes the curve chart that disturbs bias pulse a plurality of sequencing for the change of a MOSFET one critical voltage, and wherein this MOSFET has a ultra-thin multilayer tunnel dielectric layer (O1/N1/O2=15/20/18 dust).This figure is shown in insignificant charge-trapping in this ONO tunnel dielectric layer, and though be this have adopt in the example element of multilayer tunnel dielectric layer CHE ,+FN or-the FN injection way.

Figure 34 is the curve chart of the time being done under fixed current stress in a ultra-thin ONO dielectric capacitor grid voltage, and it is highlighted under the negative grid current stress little charge-trapping, and points out excellent stress tolerance.This little capturing efficiency may be because on behalf of passage freely, this electric capacity more be longer than the nitride thickness of about 20 dusts.It also shows that less than 20 dust N1 layers are preferred implementation.In addition, in preferred embodiment, during handling, do not bring out the gap seizure in O1/N1 and N1/O2.

Figure 35 is that oneself's convergence critical voltage Vt is as the function of erase gate pole tension VG for when the erase process of an element, and wherein this element is to have a ultra-thin multilayer tunnel dielectric layer (O1/N1/O2=15/20/18 dust), and has a N+ polycrystalline grid.The grid voltage VG of one greater strength causes the higher saturation value of VT, is to become stronger because of grid injects.A high self-convergent erase is useful for the NOR framework, because of it has avoided the subject under discussion of over-erasure.

Figure 36 is the curve chart of critical voltage to stoving time, element for an example, it has a N+ polycrystalline grid under various P/E Xun number of rings, for the memory cell of erase status and sequencing state, show to have excellent electronics hold capacity for this multilayer tunnel dielectric layer BE-SONOS element.

For the application of NAND, a depletion-mode element (V _T＜0) be useful for erase status.By using a P+ polycrystalline grid, it is can be reduced and element can be erased to depletion-mode that grid injects, as shown in Figure 37.Figure 37 is the curve chart to the time smooth with voltage for a multilayer tunnel dielectric layer memory cell (ONONO=15/20/18/70/90 dust), and it shows that erasing time reduces along with the grid voltage of high strength negative value more.Figure 37 also is described in bigger V _GDown (for example ,-20 volts approximately), grid injects and becomes significantly, causes and wipes saturated being about-1 volt.

Figure 38 be for, for an example element with P+ polycrystalline grid and an ONONO=15/20/18/70/90 dust, equal at VG+19 ,+20, and+21 volts the time+FN sequencing characteristic, its smooth curve chart to the time with voltage.As being same as shown in Figure 38ly, a big usable range (in this Tu Neikeda to about 7 volts) can be obtained in 10msec, and one 3 volts usable range can be obtained in being less than 200 microseconds.

Figure 39 be for, being 20 volts for a sequencing pulse is under 500 microseconds to each Xun ring, and erasing pulse for-20 volts to phase weekly be 10msec down or-18 volts be under the 100msec to phase weekly, smooth can band to sequencing/wipe the curve chart that the Xun number of rings is done, it is described P/E Xun and encircles endurance.In Figure 39, sequencing once and wiping once are to be used in each P/E Xun ring.

Figure 40 is the smooth energy curve chart of counter stress with voltage time, and it is described a VG and quickens to preserve the survey formula, and it is to apply-V at the sequencing state _GAnd apply at erase status+V _GIn example element with a P+ polycrystalline grid.As be same as described in Figure 40, little loss of charge and little electric charge obtain the direct electric charge tunnelling of expression be suppressed under general electric field (＜4MV/cm).

Figure 41 is the smooth energy curve chart that the time is done with voltage, and it is described in according to the electric charge of charge-trapping nitride N2 under room temperature and high temperature with element of a P+ polycrystalline grid of the present invention and preserves.As shown in Figure 41, it at room temperature is to ignore it that loss of charge and electric charge obtain.In addition, even the usable range above 6 volts also can be saved after 500 hours in the bakings of 150 degree Celsius.This is to be extraordinary result for SONOS type element greater than 6 volts of usable ranges and excellent preservation.

Figure 42 is the smooth energy curve chart that the time is done with voltage; it is for the ONONO element at N2 that has 70 and 90 dusts respectively and O3 layer; and this O1, N1, and the O2 layer be to be 15/20/18,15/20/25 and 18/20/18 dust; the erasing speed of BE-SONOS element is described; at thickness with this O1 layer less than 20 dusts; especially 18 dusts under this example or 15 dusts have significant improvement.Really, have the O1 of 15 dusts, this erasing speed has significant improvement, causes erasing speed less than 100 milliseconds be attainable less than 10 milliseconds speed.For the O1 layer of one 15 dusts, in less than 10 milliseconds smooth (its substantial connection is in the change of critical voltage) with voltage have and surpass 3 volts reduction.As being same as shown in Figure 42ly, this erasing speed is the change sensitivity very to O1.As shown in Figure 42, be reduced to 15 dusts at the thickness of O1 by 18 dusts, can cause the minimizing that the erasing time one shows.For the change of O2 thickness, less effect is only arranged for the erasing time usually.It is that therefore the ONO tunnelling is that the O1 layer is leading thus, and the effect of this O2 layer is almost (as Fig. 5 c) or (as Fig. 5 d) crested fully when one wipes biased operation.

Figure 43 wipes bias voltage for an element for one to be-18 volts the figure that is to the time smooth with voltage, and wherein element is to have the BE-SONOS structure, its ONONO=15/20/18/70/90 dust.Figure 43 is the erasing characteristic of the element that compares two examples, and wherein an example element has the P+ polysilicon gate, and another example element has the grid that contains platinum.Platinum has higher work function for the P+ polysilicon, it can cause unsaturated wiping completely, as is same as shown in Figure 43.This high work function grid material for example can use, and a photoresist method of stripping comes patterning.

As described, some above-mentioned example comprises the operation of structural design, array design and memory component, and the array sizes of being wished to get, good reliability, good usefulness or the combination in any of above advantage can be provided.Some above-mentioned example is the non-volatile flash memory that can be used for the scaled size size, for example nand flash memory and be used for the flash memory that data is used.Some example can provide the SONONOS element, and this element has evenly and passage tunneled holes is at a high speed wiped.Some example also can provide the good endurance of memory component and reduce some and blame the subject under discussion of wiping or wiping excessively.Simultaneously, good element characteristic can be provided, and these characteristics are for example for still only having little deterioration and good electric charge to preserve behind P/E Xun ring.Uniformity at the element of a memory array can be provided, and non-persistent position or memory cell are not arranged.Further, some example can, by separated grid NAND design, provide good jitty element characteristic, wherein this design can provide better sensing border when the operation of memory component.

Figure 44 is a summary top view, and it shows the some of an example array, and wherein this array is the thin-film transistor structure that utilizes on a dielectric substrate.Please refer to Figure 44, a memory array 400 partly be to be formed on the dielectric substrate 401.The part of this memory array 400 is included in a plurality of parallel semiconductor body zone 410 on the insulating barrier in the substrate 401, and between a plurality of parallel word line 420c of selection wire 420a and selection wire 420b.This selection wire 420a and selection wire 420b and this word line 420c are approximately perpendicular to and are covered in this semiconductor body zone 410.The quantity of this word line 420c is the quantity that is not limited to be presented at Figure 44.The quantity of this word line 420c may for 8,16,32,64 and 128 or other be fit to be applied to the number of a memory array.

This substrate 401 may for, for example, semi-conductive substrate, one three five family's compound substrate, one silicon-Germanium substrate, a brilliant substrate of heap of stone, an insulating barrier cover silicon (SOI) substrate, a for example liquid crystal display of a display substrate, plasma demonstration, the demonstration of an electron luminescence (EL) fluorescent tube, or a light-emitting diode (LED) substrate.Cover the embodiment of silicon (SOI) for insulating barrier, this substrate 401 comprises at least one insulation dielectric layer, for example is formed at a block material substrate 401, semiconductor chip for example, on a dielectric layer 405 (being shown in Figure 46 A).

Please refer to the embodiment that is shown in Figure 44, each semiconductor body zone 410 comprises at least one connection surface zone, this connection surface zone 412 of for example contiguous this selection wire 420a and selection wire 420b, wherein this selection wire 420a and selection wire 420b connect between two ends of face passage area in a continuous nothing.Selection wire 420a can be made a block selection wire by reference and selection wire 420b can be by reference as the one source pole selection wire.This connection surface zone zone 412 is to be connected to whole bit line or source electrode line by interlayer hole (contact vias) or other (not demonstrating).Selection wire 420a and selection wire 420b be configured to connect one select square or memory cell can bring to this bit line and source electrode line, when voltage is applied to selection wire 420a and selection wire 420b.

In the embodiment that describes, the part of memory array 400 comprises, contiguous this semiconductor body zone 410, and between two adjacent semiconductor body zones 410, a plurality of parallel insulation irrigation canals and ditches structure 430.

Please refer to Figure 44, a size of rectangle 402 expression one memory cell, it is the width sum total that the width that is about two times of word line 420c is multiplied by irrigation canals and ditches 430 and semiconductor body region 410 basically.

Figure 45 is the cross-sectional icon for a summary, and it represents the some of the array of an example, and is that hatching 2-2 in the 44th figure captures a word line 420c, and the perspective view of memory cell array row is crossed in expression one.In Figure 45, this irrigation canals and ditches structure 430 is to be formed between the two adjacent semiconductor body zones 410.One tunneling barrier layer 310, an electric charge storage layer 320, a dielectric layer 330 and a conductive layer 335 laminations and can be roughly along shape in the structure and the irrigation canals and ditches structure 430 in semiconductor body zone 410.It is to be connected in Figure 46 A explanation that the thin portion of tunneling barrier layer 310, electric charge storage layer 320, dielectric layer 330 and conductive layer 335 is described.

Figure 46 A and Figure 46 B are the summary icons for the cross section, and it is presented in the step in the example formation method of an example semiconductor structure, the icon of the line 3-3 acquisition in Figure 44.

Figure 46 A is the drawing in side sectional elevation that captures for the line 3-3 along Figure 44, and it is illustrated in one does not have the single memory cell rows that connects face NAND configuration.As be same as described in the 46A figure, dielectric layer 305 is covered in substrate 401.Semiconductor body zone 410 is to be formed on the dielectric layer 305.Dielectric layer 305 can be, for example, and an oxide layer, a nitration case, a nitrogen oxide layer, other dielectric layer or various above-mentioned combination.In some embodiment, dielectric layer 305 can be referred to as an oxide layer of burying, as is same as an insulating barrier and covers silicon (SOI) structure.Semiconductor body zone 410 can be the layer or the various above combination of a silicon layer, a polysilicon layer, an amorphous silicon layer, a germanium-silicon layer, an epitaxial layer, other semi-conducting material.In order to generating the embodiment in a p N-type semiconductor N zone, semiconductor body zone 410 can have the element of alloy Li such as , gallium, aluminium and/or other three races in some.In some embodiment, semiconductor body zone 410 and dielectric layer 305 can be formed by a SOI technology.In other embodiment, the formation of dielectric layer 305 can be by the CVD technology of a chemical vapor deposition (CVD) technology, high vacuum chemical vapour deposition (UHVCVD) technology, an atomic layer chemical vapor deposition (ALCVD) technology, a metal organic chemical vapor deposition (MOCVD) technology or its change.The formation in semiconductor body zone 410 can by, for example, an epitaxy technology, a CVD technology, a brilliant technology of heap of stone, or the technology of various above combination.In an embodiment, the TFT element has the polysilicon passage of one 60 nanometer thickness on buried oxide.Polysilicon is to be an amorphous silicon (a-Si) layer, and it is by low-pressure chemical vapor deposition (LPCVD) process quilt deposition, follows by a low temperature thermal annealing (600 degree Celsius) to finish crystallization.One multilayer O1/N1/O2 tunnel dielectric layer is to act on to have easy tunneled holes when wiping, and eliminates the loss of charge of tunnel dielectric layer when preserving.Then, SiN seizure layer (N2) and top obstruct oxide (O3) is generated.One severe doped P+polycrystalline grid be used with-constraining this grid when FN wipes injects.This element is to have three grid structures, as shown in figure 45, has three channel surfaces of equivalence, and one and the top in semiconductor body zone 410 are all arranged on each limit.

Top oxide technology has maximum heat budget.The technology that two top oxides (O3) form is representative, comprises a lpcvd oxide (HTO) with rapid thermal annealing, and an original state steam produce (ISSG) oxidation with conversion seizure nitride (N2) partly to oxide.Lower heat budget technology is to be suitable for reducing by selecting grid to connect the alloy diffusion of face.Yet, ISSG technology can cause a better endurance feature, as be same as and be published in InternationalElectron Devices Meeting in December, 2006, the paper of IEDM periodical " A Multi-Layer stackableThin-Flim Transistor (TFT) NAND-TYPE Flash Memory ", invention people be people such as Lai, and this paper is with as a reference usefulness in this proposition.Planarization is then to be implemented, and is for example planted and cmp by HDP oxidation cloth.After forming bottom TFT element.Contact etching for multilayer can be implemented independently to avoid excessive etching.

Please refer to Figure 46 A, semiconductor body zone 410 comprises a continuous nothing and connects face passage area 414 between selection wire 420a, selection wire 420b, and under the word line 420c and between word line 420c.Semiconductor body zone 410 comprise at least one continuous nothing connect the face passage area for example the zone 415 under selection wire 420a, selection wire 420b and word line 420c.

Each selection wire 420a, selection wire 420b comprise a gate insulator 331 and a conductive layer 336.Gate insulator 331 can be an oxide layer, a nitration case, a nitrogen oxide layer, high k value dielectric layer, other dielectric materials layer or above-mentioned various combination.Conductive layer 336 can be, for example, and the layer of a polysilicon layer, an amorphous silicon layer, a metal-containing layer, tungsten silicide layer, a bronze medal layer, an aluminium lamination or other electric conducting material.The formation of conductive layer 336 can by, for example, a CVD technology, a physical vapor deposition (PVD) technology, an electroplating technology with and/or an electrodeless plating technology.

Each word line 420c may comprise tunneling barrier layer 310, electric charge storage layer 320, dielectric layer 330 and conductive layer 335.In certain embodiments, tunneling barrier layer 310, electric charge storage layer 320, dielectric layer 330 and conductive layer 335 can successively be formed on the semiconductor body zone 410.

Tunneling barrier layer 310 can allow electric charge, for example hole or electronics, when an erase operation and/or is reseted operation, by semiconductor body zone 410 tunnellings to electric charge storage layer 320.Tunneling barrier layer 310 can be an oxide layer, a nitration case, a nitrogen oxide layer, other dielectric materials layer or various above combination.In some embodiment, tunneling barrier layer 310 can comprise one first oxide layer (not indicating), a nitration case (not indicating) and one second oxide layer (not indicating), and it is can be with reference to making an ONO structure.In some embodiment, first oxide layer can be to be had thickness and is about 2 nanometers or a littler super thin oxide layer.In another embodiment, first oxide layer can have about 1.5 nanometers or littler thickness.In additional embodiments, first oxide layer can have the thickness between about 0.5 nanometer and about 2 nanometers.Super thin oxide layer can be formed, and for example, produces (ISSG) oxidation technology by an original state steam.Be used to form nitration case technology can, for example, be about under 680 degree Celsius in temperature and use DCS and NH3 as preceding glove.In some embodiment, nitration case can have about 3 nanometers or littler thickness.In other embodiment, nitration case can have the thickness between about 1 to 2 nanometer.The formation of second oxide layer can by, for example, a LPCVD technology.In the embodiment of some, second oxide layer can have about 3.5 nanometers or littler thickness.In another embodiment, second oxide layer can have one and be about 2.5 nanometers or littler thickness.In another embodiment, second oxide layer can have the thickness between about 2.0 to 3.5 nanometers.

But electric charge storage layer 320 is store charge as previously mentioned, for example electronics or hole.Electric charge storage layer 320 can be, and for example, a nitration case, a nitrogen oxide layer, a polysilicon layer or other can be suitable for the layer of the material of store charge.In some embodiment for formation one nitrogenize electric charge storage layer, this technology can be used, and for example, dichlorosilane DCS and NH3 are as preceding glove, and technological temperature is to be about 680 degree Celsius.Be used to form the embodiment of the electric charge storage layer of a nitrogen oxide in another, this technology can be used, and for example, DCS, NH3, N2O are with as preceding glove.In some embodiment, electric charge storage layer 320 can have one and be about 5 nanometers or bigger thickness, for example, and about 7 nanometers.

Dielectric layer 330 can completely cut off conductive layer 335 iunjected charges to electric charge storage layer 320.Dielectric layer 330 can be, for example, and an oxide layer, a nitration case, a nitrogen oxide layer, an alumina layer, other dielectric material or various above combination.In some embodiment, be used to form the electric charge storage layer 320 of the convertible part of technology of dielectric layer 330, a nitration case for example is to form dielectric layer 330.This technology can be a wet conversion process, and it utilizes O in stove ₂And H ₂O gas, and in temperature approximately between 950 to 1000 degree Celsius down.For example, a nitration case, it has a thickness that is about 13 nanometers, can be converted to dielectric layer 330, and dielectric layer 330 is the thickness with about 9 nanometers, and the nitration case that retains, for example, and electric charge storage layer 320, it has the thickness that is about 7 nanometers.This wet type conversion process is the initiation layer that is applied in sub-fraction, and then amass with this layer of balance in Shen, and it is by heat budget technology less for deposition of silica, and for example high-temperature oxydation HTO technology or an original state steam produce (ISSG) oxidation technology.In a further embodiment, dielectric layer 330 is to be formed on the electric charge storage layer 320, and does not use a wet type conversion process.The all thickness of tunneling barrier layer 310, electric charge storage layer 320 and dielectric layer 330 can be used as and form a required structure.

Conductive layer 335 can be, for example, and the layer of the layer of a polysilicon layer, an amorphous silicon layer, a containing metal, tungsten silicide layer, a bronze medal layer, an aluminium lamination or other electric conducting material or the combination of above material.The formation of conductive layer 335 can by, for example, a CVD technology, a physical vapor deposition (PVD) technology, an electroplating technology with and/or an electrodeless plating technology.In some embodiment, conductive layer 335 and 336 can be formed by identical technology.In some embodiment, the structure that comprises tunneling barrier layer 310, electric charge storage layer 320 and dielectric layer 330 can be made engineering band gap SONOS (BE-SONOS) structure by reference.

Please refer to Figure 46 A, dielectric material 339 is to be formed between selection wire 420a, selection wire 420b and the word line 420c, and between between word line 420c.Dielectric material 339 can comprise, for example, and oxide, nitride, nitrogen oxide and/or other dielectric material.The formation of dielectric material 339 can by, for example, a CVD technology.At least one dielectric side walls, for example dielectric side walls 337 can be formed on the sidewall of selection wire 420a and selection wire 420b.Dielectric side walls 337 can comprise, for example, and oxide, nitride, nitrogen oxide and/or other dielectric material.In some example, dielectric side walls son 337 and dielectric material 339 are by identical materials institute's technology and by identical technology made.

Please refer to Figure 46 B, one cloth is planted technology 340 cloth and is planted alloy to semiconductor body zone 410, by using dielectric side walls 337 and/or dielectric material 339 to plant shielding to form for example zone 412 of at least one doped regions, connect face with formation in semiconductor body zone 410 as a cloth.Zone 412 can be by source/drain (S/D) zone of reference as selection wire 420a and selection wire 420b.In some embodiment, cloth is planted technology 340 and be can be an inclination cloth and plant technology, so zone 412 can be formed in this semiconductor body zone 410 rightly.In other embodiment, cloth is planted technology 340 and can be had a cloth and plant direction, and perpendicular to the surface of substrate 401, wherein transistor is to be formed on the substrate 401 to this direction generally.In some for the embodiment that forms the n channel transistor in, cloth is planted the element that technology 340 can be used n type alloy Li such as , arsenic and/or other five family.

Please refer to Figure 46 B, cloth plant technology 340 not cloth plant n type for example alloy to semiconductor body zone 410, a p N-type semiconductor N body region is for example planted technology 340 because of dielectric side walls son 337 and dielectric material 339 intercept cloth.Therefore, cloth is planted technology 340 and is not formed regions and source in the zone 414 between selection wire 420a and selection wire 420b and word line 420c.And note that cloth plants process quilt and implement with the common regions and source in the zone 414 that forms this semiconductor body zone 410 in Figure 46 A.Therefore, the zone 414 in semiconductor body zone 410 is the designs that connect face for nothing.The doping content in zone 414 and zone 415 provides a nothing to connect face so roughly be equal to, and the continuous passage zone is under selection wire 420a, selection wire 420b and word line 420c.

Figure 46 C is the summary icon for a cross section, and it represents the technology of an example, and this technology is to plant alloy in the semiconductor body zone in order to cloth.In Figure 46 C, the screen 350 of a patterning is to be formed on selection wire 420a, selection wire 420b and the word line 420c.The screen 350 of patterning is covered in selection wire 420a, selection wire 420b and word line 420c at least partly.The zone 414 in the screen 350 protection semiconductor body zones 410 of patterning is to avoid being planted alloy in the technology 355 by the cloth planting.The screen 350 of patterning can be, for example, the dielectric layer of the photoresist layer of a patterning, a patterning, the material layer of a patterning, it is to be applicable to an etch shield, and above-mentioned various combinations.After cloth was planted technology 355, the screen 350 of patterning can be removed.This cloth is planted technology 355 and be can be that an inclination cloth is planted technology or a cloth is planted technology, and it has the direction that is approximately perpendicular to substrate 401.

Figure 47 is the summary icon for a cross section, the example stack-up array structure that its expression is a part of.In Figure 47, another array structure layer 357 can be formed on the structure of Figure 46 B.Array structure layer 357 can comprise, for example, a dielectric layer 360, it is to be formed on selection wire 420a, selection wire 420b and the word line 420c.Dielectric layer 360 can be an oxide layer, a nitration case, a nitrogen oxide layer or above-mentioned various combination.The formation of dielectric layer 360 can by, for example, a CVD technology, a glass spin coating proceeding and/or other are suitable for forming the technology of a dielectric layer.

With reference to Figure 47, array structure layer 357 can further comprise at least one semiconductor body zone, for example the semiconductor body zone 365, its inclusion region 367, zone 368, zone 369, selection wire 370a, selection wire 370b, word line 370c, gate insulator 371, tunneling barrier layer 372, electric charge storage layer 374, dielectric layer 376, conductive layer 380, conductive layer 381, dielectric side walls 382, and dielectric material 384, it is to be similar to semiconductor body zone 410, semiconductor body zone 410 inclusion regions 412 wherein, zone 414, zone 415, selection wire 420a, selection wire 420b, word line 420c, gate insulator 331, tunneling barrier layer 310, electric charge storage layer 320, dielectric layer 330, conductive layer 335, conductive layer 336, dielectric side walls 337, and dielectric material 339, Figure 46 B is described as being connected in.Should notice that array structure layer 357 is to be formed on the structure of Figure 46 B.Zone 412 (being shown in Figure 44) are to belong to same hot Xun ring when making, for example, dielectric layer 360, semiconductor body zone 365, selection wire 370a, selection wire 370b, word line 370c, tunneling barrier layer 372, electric charge storage layer 374, dielectric layer 376, conductive layer 380, dielectric side walls 382 and/or dielectric material 384, described as being connected in Figure 47.Zone 412 can be extended to selection wire 420a, selection wire 420b, so form regional 412a.The regional 412a that extends can have a size " a ", and it is the size " b " greater than zone 367.

The case structure that should be noted that Figure 47 does not have identical regions and source, and wherein the zone is to be formed between selection wire 420a, selection wire 420b, the word line 420c and between word line 420c.Even behind a plurality of Xun rings, the face that connects and impure source/drain region that regional 412a may not can extend or be adjacent to other.Therefore, the subject under discussion of short-channel effect reaches and can be avoided rightly in the leakage current of memory array.

Figure 47 only shows the embodiment of an example, and it comprises the array structure of two laminations.The number of this array structure, for example, this array structure layer 357 is not limited to two.Array structure more than two or two can be formed on the interior structure of Figure 47, to reach a suitable memory span.

Figure 48 is the summary icon for a cross-sectional figure, and it shows in order to produce the technology of an example of an inversion layer in the semiconductor body region.With reference to Figure 48, a voltage " V " can be coupled to word line 420c.In some embodiment, the space " S " between two adjacent word lines, wherein word line can for example be word line 420c, 420d or word line 420c, 420e, is about 75 nanometers or littler.Among the embodiment of one example, space S is to be 30 nanometers or littler.Because the space that this is little, put on voltage " V " on the word line 420c can be coupled to and produce an inversion layer in semiconductor body zone 410 411, wherein this 411 is between two adjacent word lines, for example, word line 420c, 420d or word line 420c, 420e, and under word line 420c 411.411,411a can be used as the source/drain terminal and the passage of array transistor.In some embodiment that uses NAND type structure, voltage is to be applied to each word line 420c-420e, and may reverse and/or produce inversion layer in two adjacent word line 420c-420e and selection wire 420a, selection wire 420b.Therefore, array transistor can operate rightly and not need severe ground doping S/D to connect face in semiconductor body zone 410.

Reset

In some embodiment, once reset operation can be implemented with operation in memory array before the distribution of first limit Vt.For example, voltage can be applied to and open selection wire 420a and selection wire 420b.Before operation, be about-voltage of 7V can be applied to word line 420c-420e and and be about+voltage of 8V can be applied in semiconductor body zone 410 shown in Figure 48.The voltage that is applied to selection wire 420a and selection wire 420b is more to be higher than the voltage that is applied to word line 420c-420e.The voltage in word line 420c-420e and semiconductor body zone 410 is distributed to put on each word line and semiconductor body zone rightly.In some embodiment, memory array can various voltage chargings.Reset the memory cell that operation can be reseted memory array rightly.In some embodiment, the time of reseting is to be approximately 100 milliseconds.In some in order to the embodiment that resets memory array in, memory array can comprise the BE-SONOS element that ONONO is about 15/20/18/70/90 dust that has of n passage, and this element has a N+ polysilicon gate, its Lg/W is about the 0.22/0.16 micron.

Sequencing

Be used for the embodiment of the memory cell of programmed memory array in some, a high voltage for example, between the voltage of pact+16V to+20V, can be applied to word line 420c to bring out passage+FN injection.In some embodiment, high voltage is to be about+18V.One voltage for example is about+voltage of 10V, can be applied to other the grid that passes through, that is, 420d that does not choose and 420e go here and there in NAND to bring out inversion layer.Semiconductor body zone 410 is by ground connection roughly.Electric charge, electronics for example can be injected into the electric charge storage layer of word line 420c.In some embodiment ,+FN sequencing can be a low-power sequencing.In some embodiment, the bypass procedure method, a page method for programming for example, it has 4K bytes of memory unit can increase the general output of sequencing rightly to surpassing 10MB/sec.Total current Xiao Mao is about 1 milliampere or littler.In some embodiment, a voltage for example is about the voltage of 7V, and the bit line that can be applied to other disturbs to avoid sequencing.The voltage that is applied to bit line may increase the position standard of inversion layer to suppress in the pressure drop of not choosing bit line.

Wipe

In some embodiment, erase operation can be similar to resets operation.Be about-voltage of 7V can be applied to word line 420c and and be about+and the voltage of 8V can be applied to as being same as semiconductor body zone 410 shown in Figure 48.The voltage in word line 420c and semiconductor body zone 410 is dispensed to rightly puts on each word line and semiconductor body zone.

Read

In some for the embodiment that reads memory array in, the word line of selection can be promoted to a voltage, for example about+5V, it is between a state class (EV) that one of a memory cell is wiped and a sequencing state class (PV).Other unselected word line can be used as " passing through grid ", so its grid voltage can be promoted to a voltage, this voltage is to be higher than PV.In some embodiment, the voltage that puts on by grid is to be about+9V.In some embodiment, one be about+voltage of 1V is to be applied to semiconductor body zone 410.

The structure and the method that are used to form the structure of above-mentioned Figure 44, Figure 45, Figure 46 A-Figure 46 C and Figure 47 may be utilized in arbitrary NAND type flash memory, and it can have the structure of various memory cell, for example a flash memory with poly floating grid.

Exemplary embodiment

It below is the example of describing the BE-SONOS element that does not have the face that connects.In some embodiment, element has and is about a polycrystalline spacing of 0.15 micron.After the hard shielding of this polycrystalline of patterning, an oxidation backing layer can be formed to insert this polycrystalline space, for example, about 70 nanometers or more, then this polycrystalline of etching is to define the space of final polycrystalline.This element can be avoided improper polycrystalline short circuit or circuit collapse.Narrow space (S) between the sidewall of oxidation lining is correctly controlled by the oxide thickness of lining.

The traditional face that connects cloth is planted and can be formed on after the polycrystalline etching.Meet the embodiment of bin spare in nothing, shallow junction and sidewall can be retained.Oxidized sidewalls can be received in the narrow space between word line.One oblique angle cloth plant can be implemented with outside array and contiguous array place form the face that connects.Because thick polycrystalline grid has intercepted cloth and planted, array center is not subjected to that oblique angle cloth is planted and for there not being the face that connects.Technology is to be of value to being compatible with traditional NAND technology.And need not extra shielding.

It below is the description that connects the characteristic electron of bin spare for nothing.Element is to be a 16-WL NAND array.The ONONO structure, for example, O1/N1/O2/N2/O3, its size that has is about 13/20/25/60/60 dust respectively.

Figure 49 A describes the effect that various p type wells mix.The one slight well that mixes provides bigger electron density, causes more electric current.Figure 49 B describes the effectiveness of this space (S).When S increased, electron density was slightly to subtract in the space, caused littler electric current.

Figure 50 be show measure the initial IV curve chart of example n pass element.Nothing connects bin spare and can have the subcritical behavior that the tradition of being similar to connects bin spare.It is found, and not have the drain current connect bin spare be a little less than traditional drain current that connects bin spare.Its space (S) that also is found bigger shows smaller electric current.Figure 51 shows that the well of a height doping content can increase the Vt value that nothing connects bin spare, and it also is fit to the emulation that Figure 49 A shows.

Figure 52 A-Figure 52 B be show respectively+FN ISPP sequencing and-FN wipes.Do not have and to connect bin spare and can have with tradition and connect the similar electronic characteristic of bin spare.Its reason perhaps be because+/-FN injection dominated by the ONONO characteristic of body, and with connect face and have nothing to do.

Figure 53 is the electronic characteristic that shows the P channel B E-SONOS NAND of an example, and this BE-SONOSNAND is the structure with lamination that is similar to the described N channel B of above-mentioned Figure 50 E-SONOS NAND.In Figure 53, it is found not have and connects bin spare and have bigger Vt difference and less current, compared to traditional bin spare that connects.Its reason perhaps is that to connect bin spare be non-required ground optimization and have relatively effect of bigger Vt because of traditional.

For p passage NAND, sequencing/erasing voltage polarity then is opposite for n passage NAND.Figure 54 A-Figure 54 B shows, for the p channel B E-SONOS NAND of an example-the FNISSP sequencing and+FN wipes.By Figure 54 A-Figure 54 B, can find an example p channel B E-SONOS NAND-FN ISPP sequencing and+the FN sequencing wipes and can be implemented.

Figure 55 is the endurance that shows the n pass element of example.In Figure 55, it is the deterioration that does not have a large amount of reliabilities that nothing connects bin spare, and traditional bin spare that connects then has this problem.

Figure 56 is the IV curve that shows the TFT BE-SONOS element of an example.In order to separate the impact of heat budget, this heat budget of emulation under the three-dimensional product for the effects of a back thermal annealing under 20 minutes of 850 degree Celsius.In Figure 56, the TFT element also shows similar characteristic electron behind thermal annealing.This result for good, is quite insensitive because nothing connects bin spare to heat budget for three-dimensional product technology.

Figure 57 shows that the nothing of example connects the emulation of bin spare, and wherein element has various scientific and technological node (F is half of polycrystalline spacing), and has identical space (S is 20 nanometers).In Figure 57, can find that nothing connects bin spare Vt comparison effect and can be controlled rightly.But its attribution is relatively greater than traditional bin spare that connects for the effective channel length in nothing connects bin spare.In Figure 57, the effect of sequencing state is also by emulation.For the element with less F, sequencing Vt drift is to be reduced.Its reason element passage length for this reason is very short so boundary electric field causes the deterioration of grid control ability.It also is found does not have that to connect bin spare be to be applicable to the charge-trapping element.For the embodiment of floating grid element, little space (S) can bring out more FG-FG and disturb.

Aforementioned preferred embodiment of the present invention is the usefulness that is used for describing and illustrating the present invention.Its should painstakingly be used as completely or as limit the present invention for by the accurate form that disclosed.It can be had common operator in this field understands, and is not breaking away under principle of the present invention and the scope, and the above embodiments can be changed or adjust.So should be appreciated that, the present invention is not limited to disclosed certain embodiments, but should be understood the adjustment form that is included under spirit of the present invention and the scope, and spirit of the present invention and scope are defined by claim scope of the present invention.

Claims (34)

1, a kind of integrated circuit component, it comprises:

The semiconductor main body, it is positioned on the dielectric layer;

A plurality of grids, it is positioned on this semiconductor body, be arranged to a grid sequence, described grid is included in a first grid and the most last grid on this grid sequence, has insulating component between this grid sequence to separate each the adjacent grid in this grid sequence; And

One charge storing structure, it comprises under two grids of the described grid of dielectric charge catching position in this grid sequence at least, and this charge storing structure comprises one and places tunnelling dielectric structure, on this semiconductor body to place electric charge storage layer and on this tunnelling dielectric structure to place insulating barrier on this electric charge storage layer;

Wherein this semiconductor body is included in the multiple-grid utmost point passage area under these interior a plurality of grids of this grid sequence.

2, integrated circuit component as claimed in claim 1, wherein this tunnelling dielectric structure and this semiconductor body between an interface on have a tunneled holes energy barrier height, and away from the tunneled holes energy barrier height of this distance at the interface this tunneled holes energy barrier height less than this interface.

3, integrated circuit component as claimed in claim 1, wherein this grid sequence comprises and surpasses two grids, and this charge storing structure is included in the dielectric charge catching position that surpasses in this grid sequence under two grids.

4, integrated circuit component as claimed in claim 1, this insulating component of wherein separating this grid sequence are between adjacent grid and have thickness less than 30 nanometers.

5, integrated circuit component as claimed in claim 1, wherein this charge storing structure is to be used to a dielectric charge catching position that is positioned under the grid of this grid sequence to catch electric charge, to set up a target critical voltage under a high critical condition; And

This tunnelling dielectric structure comprises a bottom dielectric layer, this bottom dielectric layer has a tunneled holes energy barrier height, one intermediate dielectric layer, it has a tunneled holes energy barrier height, this tunneled holes energy barrier height less than this bottom dielectric layer, an and top dielectric, its tunneled holes energy barrier height is greater than the tunneled holes energy barrier height of this intermediate dielectric layer, to isolate this intermediate dielectric layer and this electric charge capture layer, wherein this tunnelling dielectric structure is in order to allowing the FN tunneled holes to this electric charge capture layer, to allow reducing at least 2 volts of this target critical voltages being less than in time of 100 milliseconds.

6, integrated circuit component as claimed in claim 5, wherein this intermediate dielectric layer has a thickness, makes the electric field applied when the FN tunneled holes enough offset this intermediate dielectric layer in this tunnelling dielectric structure and this tunneled holes energy barrier height of this top dielectric.

7, integrated circuit component as claimed in claim 5, wherein this bottom dielectric layer comprises silicon dioxide, and this intermediate dielectric layer comprises silicon nitride, and this top dielectric comprises silicon dioxide, and this electric charge storage layer comprises silicon nitride and this insulating barrier comprises silicon dioxide.

8, integrated circuit component as claimed in claim 1, wherein this tunnelling dielectric structure comprises a bottom dielectric layer, its thickness has one less than the thickness of 2 nanometers and have a tunneled holes energy barrier height, one intermediate dielectric layer is positioned on this bottom dielectric layer, this intermediate dielectric layer has a tunneled holes energy barrier height, it is less than the tunneled holes energy barrier height of this bottom dielectric layer, this intermediate dielectric layer has one 3 nanometers or littler thickness, an and top dielectric, it has a tunneled holes energy barrier height, it is greater than this tunneled holes energy barrier height of this intermediate dielectric layer, this top dielectric have one for or less than the thickness of 3.5 nanometers;

This electric charge storage layer comprises dielectric charge seizure layer and is positioned on this top dielectric of this tunnelling dielectric structure, this dielectric charge is caught layer and is had a tunneled holes energy barrier height, it is less than this tunneled holes energy barrier height of this top dielectric, and has the thickness greater than 5 nanometers; And

This insulating barrier comprises a dielectric barrier on this electric charge storage layer, and it has a tunneled holes energy barrier height, and it catches this tunneled holes energy barrier height of layer greater than this dielectric charge, and has the thickness greater than 5 nanometers.

9, integrated circuit component as claimed in claim 8, wherein this thickness of this bottom dielectric layer is less than or equal to 18 dusts.

10, as claim 5 or 8 described integrated circuit components, wherein this thickness of this intermediate dielectric layer is greater than this thickness of this bottom dielectric layer.

11, integrated circuit component as claimed in claim 10, wherein this bottom dielectric layer comprises silicon dioxide, and this intermediate dielectric layer comprises silicon nitride, and this top dielectric comprises silicon dioxide.

12, integrated circuit component as claimed in claim 10, wherein this dielectric charge catches that layer comprises silicon nitride and this dielectric barrier comprises silicon dioxide.

13, a kind of semiconductor structure, it comprises:

A plurality of first semiconductor body zones are in a substrate, and these a plurality of first semiconductor body zones have one first doping attitude;

One first selection wire and one second selection wire, it is perpendicular to this first semiconductor body zone;

A plurality of first word lines are between this first selection wire and this second selection wire, and each these a plurality of first word line is to cover a passage area in the described first semiconductor body zone and perpendicular to the described first semiconductor body zone;

One first tunnelling energy barrier structure, one first electric charge storage layer reaches one first dielectric layer between each described first word line and corresponding this first semiconductor body zone, and is positioned within this first semiconductor body zone in a corresponding passage area;

At least one face that connects is within each described first semiconductor body zone, and wherein this at least one face that connects is in abutting connection with this first selection wire, and this at least one mask that connects has one second doping attitude; And

Wherein, connect between face and this second selection wire corresponding this semiconductor body zone for there not being the face that connects at this.

14, semiconductor structure as claimed in claim 13, further comprise in abutting connection with and be parallel to a plurality of irrigation canals and ditches structures in the described first semiconductor body zone, each described irrigation canals and ditches structure is the first adjacent semiconductor body zone of branch next but two.

15, semiconductor structure as claimed in claim 13, wherein this first tunnelling energy barrier structure comprises a tunnelling dielectric structure, its with the interregional interface of corresponding this semiconductor body on have a tunneled holes energy barrier height, and away from the tunneled holes energy barrier height of this distance at the interface less than position this tunneled holes energy barrier height at this interface.

16, semiconductor structure as claimed in claim 13, wherein this first tunnelling energy barrier structure, this first electric charge storage layer and this first dielectric layer are to be an ONONO structure.

17, semiconductor structure as claimed in claim 13, wherein this substrate comprises an oxide layer, and wherein this oxide layer is positioned on this substrate and is positioned under this first semiconductor body zone.

18, semiconductor structure as claimed in claim 13, it further comprises:

One second insulating barrier is positioned on described first word line; A plurality of second semiconductor body zones, it has this first doping attitude and covers this second insulating barrier;

A plurality of second word lines are between one the 3rd selection wire and one the 4th selection wire, and the 3rd selection wire and the 4th selection wire are perpendicular to this second semiconductor body zone and on it; And

One second tunnelling energy barrier structure, one second electric charge storage layer, and one second dielectric layer between this second word line and this second semiconductor body zone;

At least one second connects face within each described second semiconductor body zone, and at least one second to connect face be in abutting connection with the 3rd selection wire for this, and this at least one second connects mask one second doping attitude is arranged; And

Wherein, second connect between face and the 4th selection wire corresponding this second semiconductor body zone at this for there not being the face that connects.

19, a kind of method that forms semiconductor structure, it comprises:

Form a plurality of first semiconductor body zones, it utilizes one first doping attitude to be implanted in a substrate;

Form a plurality of first word lines between one first selection wire and one second selection wire, described first word line, this first selection wire and this second selection wire are to cover the described first semiconductor body zone;

Form one first tunnelling energy barrier structure, one first electric charge storage layer and one first dielectric layer are between described first semiconductor body zone and described first word line;

Form first dielectric side walls on a sidewall of a sidewall of this first selection wire and this second selection wire;

Form first source/drain and connect face, it is in abutting connection with this first selection wire and this second selection wire, and it has one second doping attitude; And

Wherein a plurality of zones in the described first semiconductor body zone between two adjacent word lines are not for there being the face that connects.

20, the method for formation semiconductor structure as claimed in claim 19 wherein forms this first dielectric side walls and comprises formation first dielectric material between two first adjacent word lines.

21, the method for formation semiconductor structure as claimed in claim 19 wherein forms this first regions and source and comprises this first dielectric side walls of use to plant shielding as a cloth.

22, the method for formation semiconductor structure as claimed in claim 19 further comprises a plurality of irrigation canals and ditches structures of formation, and it is to be parallel to this first semiconductor body zone.

23, the method for formation semiconductor structure as claimed in claim 19 wherein forms this first source/drain and connects bread and contain:

Form a patterning screen, it is covered at least partly this first and second selection wire and described first word line; And

Cloth is planted the alloy of this first doping attitude to the described first semiconductor body zone, and it is to utilize this patterning screen to plant shielding as a cloth.

24, the method for formation semiconductor structure as claimed in claim 19, wherein form this first tunnelling energy barrier structure and comprise formation one tunnelling dielectric structure, it has multilayer or compound composition, and and this first semiconductor body zone between an interface on have a tunneled holes energy barrier height, and away from the tunneled holes energy barrier height of this distance at the interface this tunneled holes energy barrier height less than this interface.

25, the method for formation semiconductor structure as claimed in claim 19 further comprises formation one oxide layer between this substrate and the described first semiconductor body zone.

26, the method for formation semiconductor structure as claimed in claim 19 further comprises:

Form one second insulating barrier on this first word line;

Form a plurality of second semiconductor body zones, it has this first doping attitude and is positioned on this second insulating barrier;

Form a plurality of second word lines between one the 3rd selection wire and one the 4th selection wire, described second word line, the 3rd selection wire and the 4th selection wire are described second semiconductor body of approximate vertical zones and on it;

Form one second tunnelling energy barrier structure, one second electric charge storage layer and one second dielectric layer are between described second semiconductor regions and described second word line;

Form second dielectric side walls on the sidewall of the 3rd selection wire and on the sidewall of the 4th selection wire; And

Form second regions and source, it is to have this second doping attitude, and adjacent the 3rd selection wire and the 4th selection wire.

27, the method for formation semiconductor structure as claimed in claim 26 wherein forms this second dielectric side walls and comprises and form one second dielectric material between two adjacent second word lines.

28, the method for formation semiconductor structure as claimed in claim 26 wherein forms this second regions and source and comprises this second dielectric side walls of use to plant shielding as a cloth.

29, the method for formation semiconductor structure as claimed in claim 19, wherein forming this first regions and source comprises, utilize this first dielectric material to plant barrier layer as cloth, the alloy that cloth is planted the second doping attitude is to the described first semiconductor body zone, plants this alloy in two adjacent described first word lines in the described first semiconductor body zone so can prevent cloth.

30, the method for formation semiconductor structure as claimed in claim 19, wherein this method does not comprise a cloth that is used to form in this first semiconductor body zone between two adjacent described first word lines, common source/drain region and plants program.

31, a kind of method of operating semiconductor structure, this semiconductor structure comprise a plurality of parallel semiconductor body zones in a substrate; A plurality of word lines are between one first selection wire and one second selection wire, and described word line comprises word line and a plurality of word line of choosing of not choosing, described word line, this first selection wire and this second selection wire, and it is perpendicular to described semiconductor body zone; And a tunnelling energy barrier structure, an electric charge storage layer and a dielectric layer are between described word line and described semiconductor body zone, wherein said semiconductor body zone comprises at least one first area, it is adjacent to this first selection wire and this second selection wire, and second area, they are between two adjacent word lines, and wherein this first area has a doping content, and it is higher than the doping content at this second area, and wherein at least one this second area does not connect face for having, and this method comprises:

Apply one first voltage to this first selection wire and this second selection wire;

Apply one second voltage to described word line, this first voltage is higher than this second voltage; And

Extremely described semiconductor body zone is to reset this semiconductor structure to apply a tertiary voltage, and this tertiary voltage is higher than this second voltage.

32, the method for operation semiconductor structure as claimed in claim 31, it further comprises:

Apply one the 4th voltage to this word line of choosing;

Apply one the 5th voltage to the described word line of not choosing at least one bringing out at least one inversion layer between described word line, the 4th voltage be higher than the 5th voltage with iunjected charge in this electric charge storage layer; And

With a ground connection in described semiconductor body zone, it is to be coupled to this second area contiguous with this word line of choosing.

33, the method for operation semiconductor structure as claimed in claim 32 further comprises:

Apply one the 6th voltage to this word line of choosing, the 6th voltage is less than the 5th voltage;

Apply one the 7th voltage to the described word line of not choosing, the 7th voltage is higher than the 6th voltage; And

Apply one the 8th voltage to the semiconductor body zone of this ground connection to read a state that is stored in this electric charge storage layer, the 8th voltage is lower than the 6th voltage.

34, the method for operation semiconductor structure as claimed in claim 31, it further comprises:

Apply one the 6th voltage to this first selection wire and this second selection wire;

Apply one the 7th voltage to described word line, the 6th voltage is higher than the 7th voltage; And

This semiconductor body zone of suspension joint is to wipe the electric charge that is stored in this electric charge storage layer.

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