CN105990355B - Memory element and its manufacturing method - Google Patents
Memory element and its manufacturing method Download PDFInfo
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- CN105990355B CN105990355B CN201510042552.3A CN201510042552A CN105990355B CN 105990355 B CN105990355 B CN 105990355B CN 201510042552 A CN201510042552 A CN 201510042552A CN 105990355 B CN105990355 B CN 105990355B
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Abstract
The invention discloses a kind of memory element and its manufacturing methods.Memory element includes substrate, multiple semiconductor strip structures, the first doped region, multiple second doped regions, multiple first contact holes and multiple second contact holes.Each semiconductor bar shape structure extends along a first direction.First doped region includes multiple first parts and second part.Each first part is located at the lower part of corresponding semiconductor strip structure.Second part is located at the surface of substrate, and first part is connected with second part.Every one second doped region is located at the top of corresponding semiconductor strip structure.Every one first contact hole is electrically connected the second part of the first doped region.Every one second contact hole is electrically connected the second corresponding doped region.
Description
Technical field
The invention relates to a kind of semiconductor element and its manufacturing methods, and in particular to a kind of common source
Memory element and its manufacturing method.
Background technique
Nonvolatile memory (non-volatile memory) can carry out the behaviour such as deposit, reading, erasing of multiple data
Make, and even if power supply supply discontinuity, stored data will not disappear.Therefore, nonvolatile memory has become many electricity
Prerequisite memory element in sub- product, normal operating when maintaining electric equipment products to be switched on.
However, as the size of semiconductor element is increasingly reduced, conventional flat formula memory element (horizontal
Memory device) short-channel effect (short channel effect) will become more and more serious.This phenomenon will be led
Cause second effect (2nd bit effect) and the evil of programming interference (program disturbance) in memory element
Change.Therefore, in order to avoid the generation of above-mentioned phenomenon, start to develop rectilinear memory element (vertical memory in recent years
Device), so that while size reduction, identical passage length can be still maintained, to avoid short-channel effect and improves the
Two effects and programming are interfered.
In rectilinear memory element, while component structure is toward superimposed layer, relativeness between each element and
The framework of laminated construction also becomes complicated.Therefore, how to simplify the relativeness and lamination knot between rectilinear memory element
The framework of structure, and original operation efficiency is maintained, it is the project of current desired research.
Summary of the invention
The present invention provides a kind of memory element and its manufacturing method, can simplify the relativeness between rectilinear memory element
And the framework of laminated construction, original operation efficiency is maintained, and compatible with prior art.
The present invention provides a kind of memory element comprising substrate, multiple semiconductor strip structures, the first doped region, multiple
Second doped region, multiple wordline, electric charge storage layer, multiple first contact holes, multiple second contact holes, the first conducting wire and multiple
Second conducting wire.Above-mentioned substrate includes multiple first blocks and multiple second blocks.First block is alternateed with the second block.Often
One first block includes two the firstth areas and secondth area, and the secondth area is between above-mentioned two firstth area.It is above-mentioned multiple
Semiconductor strip structure bit is in substrate.Each semiconductor bar shape structure extends along a first direction.Above-mentioned first doped region packet
Include multiple first parts and second part.Each first part is located at the lower part of corresponding semiconductor strip structure.Second
Quartile is in the surface of substrate, and first part is connected with second part.Every one second doped region is located at corresponding semiconductor
The top of strip structure.Above-mentioned multiple wordline are located in the substrate in every one first area.Each wordline extends along second direction, covers
Cover the partial sidewall and atop part of each semiconductor bar shape structure.First direction is different from second direction.Above-mentioned electric charge storage layer
Between semiconductor strip structure and wordline.Above-mentioned multiple first contact holes are located in the second block and the secondth area, and edge
First direction arrangement.Every one first contact hole is electrically connected the second part of the first doped region.Above-mentioned multiple second contact holes
It is located at least in the secondth area.Every one second contact hole is electrically connected the second corresponding doped region.Above-mentioned first conducting wire is located at base
Extend on bottom and along a first direction, and is electrically connected with the first contact hole.Above-mentioned multiple second conducting wires are located in substrate.It is each
Second conducting wire extends along a first direction, and is electrically connected with the second contact hole on corresponding semiconductor strip structure.
In one embodiment of this invention, above-mentioned each semiconductor bar shape structure has matrix area.Matrix area, which is located at, partly leads
The second doped region in body strip structure and between the first part of the first doped region.Also, it in above-mentioned second block, more wraps
Include above-mentioned second contact hole.
In one embodiment of this invention, there is channel in above-mentioned second block, above-mentioned channel prolongs along second direction
It stretches.Also, above-mentioned each semiconductor bar shape structure has matrix area.In the first block, matrix area be located at the second doped region with
Between the first part of first doped region.In the second block, matrix area is located in the first part of the first doped region, and above-mentioned
Channel exposes above-mentioned matrix area.
In one embodiment of this invention, multiple third contact holes and privates are further included.Above-mentioned third contact hole
In the second block, extend along second direction, and is electrically connected the exposed above-mentioned matrix area of above-mentioned channel.Above-mentioned third
Conducting wire is located in substrate, extends along a first direction, and is electrically connected with third contact hole.
In one embodiment of this invention, multiple local conducting wires, the first block positioned at third contact hole two sides are further included
In.Each part conducting wire extends along a first direction, and electrical with the second contact hole on corresponding semiconductor strip structure
Connection.Also, every one second conducting wire is located above the local conducting wire on corresponding semiconductor strip structure and connects across third
Window is touched, is electrically connected via multiple 4th contact holes and corresponding local conducting wire.
The present invention provides a kind of manufacturing method of memory element comprising following steps.Substrate is provided, above-mentioned substrate includes
Multiple first blocks and multiple second blocks.First block is alternateed with the second block.Every one first block includes two the
One area and secondth area, and the secondth area is between above-mentioned two firstth area.In forming multiple semiconductor strip knots in substrate
Structure, wherein each semiconductor bar shape structure extends along a first direction.The first doped region is formed, the first doped region includes multiple
A part and second part.Each first part is located at the lower part of corresponding semiconductor strip structure.Second part is located at base
The surface at bottom, and first part is connected with second part.Multiple second are formed in the top of each semiconductor bar shape structure to mix
Miscellaneous area.In forming multiple wordline in the substrate in every one first area.Each wordline extends along second direction, covers each semiconductor bar
The partial sidewall and atop part of shape structure, first direction are different from second direction.Between semiconductor strip structure and wordline
Form electric charge storage layer.Multiple first contact holes are formed in the second block and the secondth area, are arranged along a first direction, it is each
First contact hole is electrically connected the second part of the first doped region.Multiple second contact holes are formed to being less than in the secondth area.It is each
Second contact hole is electrically connected the second corresponding doped region.In forming the first conducting wire in substrate.First conducting wire is along first party
It is electrically connected to extension, and with the first contact hole.In forming multiple second conducting wires in substrate.Every one second conducting wire is along first party
It is electrically connected to extension, and with the second contact hole on corresponding semiconductor strip structure.
In one embodiment of this invention, wherein formed above-mentioned semiconductor strip structure, above-mentioned first doped region with it is above-mentioned
The method of second doped region includes the following steps.Patterned features substrate, to form semiconductor strip structure.Carry out ion implanting
Admixture is flowed into the top of each semiconductor bar shape structure and the surface of substrate by technique.Hot tempering process is carried out, so that
Above-mentioned admixture forms the first doped region and the second doped region.
In one embodiment of this invention, it further includes: removing the part semiconductor strip structure in above-mentioned second block,
To form channel.Above-mentioned channel extends along second direction, exposes the matrix area of corresponding semiconductor strip structure.
In one embodiment of this invention, following steps are further included.Third contact hole is formed in above-mentioned second block, on
It states third contact hole to extend along second direction, and is electrically connected the exposed matrix area of above-mentioned channel.In forming in substrate
Three wires, above-mentioned privates extend along a first direction, and are electrically connected with third contact hole.
In one embodiment of this invention, following steps are further included.In the first block of above-mentioned third contact hole two sides
Form multiple local conducting wires.It is each part conducting wire extend along a first direction, and on corresponding semiconductor strip structure
Second contact hole is electrically connected.Also, every one second conducting wire is located on the local conducting wire on corresponding semiconductor strip structure
Just and across third contact hole, it is electrically connected via multiple 4th contact holes and corresponding local conducting wire.
The present invention provides a kind of storage array, including above-mentioned memory element.Above-mentioned storage array include multiple storage units,
Multiple bit lines, a plurality of common source line and source electrode line.Said memory cells are arranged in the array of multirow and multiple row, and including doing
The first doped region for source electrode and the second doped region as drain electrode.Each bit line is coupled to the of the storage unit of same a line
Two doped regions.Each common source line is coupled to the first doped region of the storage unit of same row.Above-mentioned source electrode line is coupled to altogether
Source line, and be electrically connected with the first doped region of storage unit.Each wordline is coupled to the grid of the storage unit of same row
Pole.
In one embodiment of this invention, above-mentioned storage array further includes matrix line.It is single that above-mentioned matrix line is coupled to storage
The matrix area of member.
The present invention provides a kind of operating method of storage array comprising following steps.Select an at least storage unit.It applies
Add a wordline corresponding to first voltage to selected storage unit.Apply corresponding to second voltage to selected storage unit
One bit line.Apply the source electrode line of tertiary voltage to storage array.
In one embodiment of this invention, the operating method of above-mentioned storage array further includes following steps.Apply the 4th electricity
It is depressed into the matrix line of storage array corresponding to selected storage unit.
Based on above-mentioned, the first part of the first doped region provided by the invention is connected with second part, therefore each half is led
The first doped region in body strip structure can be connected to each other.Also, since the first contact hole is electrically connected the first doped region
Second part, therefore the first contact hole is electrically connected the first doped region in each semiconductor bar shape structure.In this way, can be substantially
The framework for simplifying the relativeness and laminated construction between rectilinear memory element, maintains original operation efficiency, and with it is existing
There is process compatible.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate institute's accompanying drawings
It is described in detail below.
Detailed description of the invention
Figure 1A to Fig. 1 D is according to the upper depending on showing of the manufacturing method of memory element depicted in the first embodiment of the present invention
It is intended to.
Fig. 2A to Fig. 2 D is respectively the diagrammatic cross-section of the A-A' line along Figure 1A to Fig. 1 D.
Fig. 3 A to Fig. 3 D is respectively the diagrammatic cross-section of the B-B ' line along Figure 1A to Fig. 1 D.
Fig. 4 A to Fig. 4 D is respectively the diagrammatic cross-section of the C-C ' line along Figure 1A to Fig. 1 D.
Fig. 5 A to Fig. 5 D is respectively the diagrammatic cross-section of the D-D ' line along Figure 1A to Fig. 1 D.
Fig. 6 A to Fig. 6 E is according to the upper depending on showing of the manufacturing process of memory element depicted in the second embodiment of the present invention
It is intended to.
Fig. 7 A to Fig. 7 E is respectively the diagrammatic cross-section of the A-A' line along Fig. 6 A to Fig. 6 E.
Fig. 8 A to Fig. 8 E is respectively the diagrammatic cross-section of the B-B ' line along Fig. 6 A to Fig. 6 E.
Fig. 9 A to Fig. 9 E is respectively the diagrammatic cross-section of the C-C ' line along Fig. 6 A to Fig. 6 E.
Figure 10 A to Figure 10 E is respectively the diagrammatic cross-section of the E-E' line along Fig. 6 A to Fig. 6 E.
Figure 11 A is the schematic diagram according to memory array structure depicted in the first embodiment of the present invention.
Figure 11 B is the schematic diagram according to memory array structure depicted in the second embodiment of the present invention.
Figure 12 A to Figure 12 B is according to the memory element for inversely reading (RR) operation depicted in one embodiment of the invention
Schematic diagram.
Figure 13 A to Figure 13 B is that (CHEI) operation is injected according to channel hot electron depicted in one embodiment of the invention
The schematic diagram of memory element.
Figure 14 A to Figure 14 B is according to energy band depicted in one embodiment of the invention to hot hole caused by energy band tunnel
Inject the schematic diagram of the memory element of (BTBT HH) operation.
Figure 15 A to Figure 15 B is according to the memory element of FN electric hole implant operation depicted in one embodiment of the invention
Schematic diagram.
Figure 16 A to Figure 16 B is the memory element operated according to FN electron injection depicted in one embodiment of the invention
Schematic diagram.
[symbol description]
10: substrate
12,16: doped region
12a, 12b: part
12c: doped layer
14: matrix area
14c: base layer
16c: doped layer
18: electric charge storage layer
20,20a: semiconductor strip structure
22: wordline
24: clearance wall
26,30,32: dielectric layer
28: lining
42,44,46,61a, 61b, 61c: contact hole
42a, 44a, 46a, 60a, 60b, 60c: contact window
52,56,72a, 72b, 74a, 74b, 76: conducting wire
54: local conducting wire
100,200: memory element
301,302: memory cell string
B1, B2: block
BdL: matrix line
BdLT: matrix line transistor
BL1~BLn: bit line
BLT1~BLTn: bitline transistor
D1, D2: direction
GBL1、GBL2: global bit line
M1, M2: storage unit
R1, R2: area
S1, S2: top surface
SL: source electrode line
SLT: source electrode line transistor
T: channel
V1、V2、Vn、Vd、Vg、Vs、Vb: voltage
WL1~WL2m: wordline
Specific embodiment
Figure 1A to Fig. 1 D is according to the upper depending on showing of the manufacturing method of memory element depicted in the first embodiment of the present invention
It is intended to.Fig. 2A to Fig. 2 D is respectively the diagrammatic cross-section of the A-A' line along Figure 1A to Fig. 1 D.Fig. 3 A to Fig. 3 D is respectively along Figure 1A
To the diagrammatic cross-section of the B-B ' line of Fig. 1 D.Fig. 4 A to Fig. 4 D is respectively the diagrammatic cross-section of the C-C' line along Figure 1A to Fig. 1 D.
Fig. 5 A to Fig. 5 D is respectively the diagrammatic cross-section of the D-D' line along Figure 1A to Fig. 1 D.
Referring to Figure 1A, Fig. 2A, Fig. 3 A, Fig. 4 A and Fig. 5 A, substrate 10 is provided.Substrate 10 includes multiple firstth areas
Block B1 and multiple second block B2.First block B1 is alternateed with the second block B2.Every one first block B1 includes two the
An one area R1 and second area R2.Second area R2 is between above-mentioned two firstth area R1.Substrate 10 be, for example, semiconductor base,
Semiconducting compound substrate or silicon-on-insulator (silicon on insulator, SOI) substrate.Substrate 10 may include ion note
Enter region, such as is formed by regions and source/drain with p-type or N-type ion injection.Substrate 10 may include single layer structure or more
Layer structure.Substrate 10 is, for example, including shallow trench isolation (shallow trench isolation, STI).In one embodiment,
Substrate 10 is, for example, silicon base or doped polysilicon.
Then, referring to Figure 1A, Fig. 2A, Fig. 3 A, Fig. 4 A and Fig. 5 A, multiple semiconductor bars are formed on the substrate 10
Shape structure 20, and doped region 12, matrix area 14 and doped region 16 are formed in semiconductor strip structure 20.Each semiconductor bar
D1 extends shape structure 20 along a first direction.Doped region 16 is located at the top of each semiconductor bar shape structure 20.Doped region 12 wraps
Include multiple first part 12a and second part 12b.Each first part 12a is located at corresponding semiconductor strip structure 20
Lower part.Second part 12b is located at the surface of substrate 10, and first part 12a is connected with second part 12b.Matrix area 14
Between doped region 16 and the first part 12a of doped region 12.
12/ matrix area of doped region, 14/ doped region 16 is, for example, as source electrode/matrix/drain electrode.Doped region 12 and doped region 16
It can be the first conductive type；Matrix area 14 can be the second conductive type.12/ matrix area of doped region, 14/ doped region 16 is, for example, N+/P/N+
Doped region or P+/N/P+ doped region.Also, doped region 12 can be identical or not identical with the doping concentration of doped region 16；Matrix area
14 can be doped or undoped.In one embodiment, the doping concentration of matrix area 14 is, for example, to be less than doped region 12 and doping
The doping concentration in area 16.In another embodiment, the thickness of matrix area 14 is, for example, the thickness for being greater than doped region 12 Yu doped region 16
Degree.The thickness of matrix area 14 is, for example, 30-500 nanometers.The thickness of doped region 12 and doped region 16 is, for example, 20-200 nanometers.
Significantly, since doped region 12 includes first part 12a and second part 12b, and first part 12a with
Second part 12b is connected.Therefore, the first part 12a of the doped region 12 in each semiconductor bar shape structure 20 can pass through
Two part 12b and be connected with each other.In one embodiment, when doped region 12 is, for example, as source electrode, each semiconductor bar shape knot
Source electrode in structure 20 can be electrically connected to each other.
In one embodiment of this invention, the method for semiconductor strip structure 20, doped region 12 and doped region 16 is formed
E.g. patterned features substrate 10, to form semiconductor strip structure 20.Patterned method is, for example, to carry out to substrate 10
Photoetching and etching technics.Then, admixture is injected in semiconductor strip structure 20 and substrate 10.The method that admixture is injected
Ion implantation technology e.g. is carried out to substrate 10, admixture is flowed into top and the base of each semiconductor bar shape structure 20
The surface at bottom 10.Later, hot tempering process is carried out to doped semiconductor strip structure 20 and substrate 10, so that above-mentioned admixture
Diffuse to form doped region 12 and doped region 16.
Please continue to refer to Figure 1A, Fig. 2A, Fig. 3 A, Fig. 4 A and Fig. 5 A, in formation electric charge storage layer 18 in substrate 10.Charge
Storage layer 18 is conformally formed along the top surface of semiconductor strip structure 20 with side.Since electric charge storage layer 18 is located at semiconductor
The top surface and side of strip structure 20, therefore, electric charge storage layer 18 not only there is charge to store function, also have doped region
12, the effect that the wordline 22 (as shown in Figure 5A) formed in doped region 16 and subsequent technique electrically isolates.In one embodiment, electric
Lotus storage layer 18 is e.g. made of oxide layer/nitration case/oxide layer (Oxide-Nitride-Oxide, ONO) compound
Layer, this composite layer can be three layers or more.The forming method of electric charge storage layer 18 is, for example, chemical vapour deposition technique or hot oxygen
Change method etc..
Then, wordline material layer (not being painted) is formed on electric charge storage layer 18, wordline material layer is along electric charge storage layer
18 top surface and side.The material of wordline is, for example, N+ DOPOS doped polycrystalline silicon, P+ DOPOS doped polycrystalline silicon, metal material or combinations thereof.It connects
, wordline material layer is patterned, to form multiple wordline 22 in the substrate 10 of every one first area R1 (e.g. as control gate
Pole).Each wordline 22 extends along second direction D2, covers the part side of each electric charge storage layer 18 in the first area R1 of substrate 10
Wall and atop part.That is, above-mentioned electric charge storage layer 18 is between semiconductor strip structure 20 and wordline 22.Above-mentioned
One direction D1 is different from second direction D2.In an exemplary embodiment, above-mentioned first direction D1 and second direction D2 substantially hangs down
Directly.
Referring to Figure 1B, Fig. 2 B, Fig. 3 B, Fig. 4 B and Fig. 5 B, in each wordline 22 and each semiconductor bar shape
The side of structure 20 is respectively formed clearance wall 24.It (is not drawn specifically, being conformally formed spacer material layer on the substrate 10
Show), to cover semiconductor strip structure 20.The material of spacer material layer is, for example, silica, silicon nitride or combinations thereof, can
It is formed using chemical vapour deposition technique.Then, anisotropic etching technics is carried out, the portion gap wall material bed of material and part are removed
Electric charge storage layer 18 is respectively formed clearance wall 24 with the side in each wordline 22 and each semiconductor bar shape structure 20.?
In one embodiment, the top surface S1 of the electric charge storage layer 18 in each semiconductor bar shape structure 20 of the exposure of clearance wall 24 is (such as Fig. 4 B institute
Show).In another embodiment, it in order to ensure the spacer material layer on the top surface S1 of electric charge storage layer 18 removes completely, is carving
The mode of over etching (over etching) can be taken during erosion, remove Partial charge storage layer 18.Therefore, between being formed by
Gap wall 24 exposes the top surface S2 (as shown in Figure 2 B) of semiconductor layer 16.
Referring to Fig. 1 C, Fig. 2 C, Fig. 3 C, Fig. 4 C and Fig. 5 C, in formation dielectric layer 26 in substrate 10.Then, sharp
With photoetching and etching technics, part of dielectric layer 26 and Partial charge storage layer 18 are removed, in the second block B2 of substrate 10
With multiple first contact window 42a are formed in the second area R2；And to opening less than forming multiple second contact holes in the second area R2
Mouth 44a.Every one first contact window 42a exposes the second part 12b of doped region 12.Every one second contact window 44a
Expose the doped region 16 of semiconductor strip structure 20.
Later, the first contact hole 42 and are respectively formed in the first contact window 42a and the second contact window 44a
Two contact holes 44.First contact hole 42 is located in the second block B2 and the second area R2, and D1 is arranged along a first direction；
Second contact hole 44 is located at least in the second area R2.In an illustrative embodiments, the first contact hole 42 is located on part of substrate 10
Outermost semiconductor strip structure 20 side the second block B2 and the second area R2 in.Second contact hole 44 is located at the
In two area R2 and the second block B2.Every one first contact hole 42 is electrically connected the second part 12b of doped region 12.Every one second
Contact hole 44 is electrically connected the doped region 16 of corresponding semiconductor strip structure 20.First contact hole 42 and the second contact hole 44
Forming method be, for example, first to form conductor material layer on the substrate 10.Conductor material layer is, for example, aluminium, copper or its alloy.Conductor
The forming method of material layer can be physical vaporous deposition, e.g. sputtering method.And then with chemical mechanical milling method or
The conductor material layer being etched back to other than method removal the first contact window 42a and the second contact window 44a.
Referring to Fig. 1 D, Fig. 2 D, Fig. 3 D, Fig. 4 D and Fig. 5 D, conductor material layer is formed on the substrate 10 and (is not drawn
Show).Then, photoetching and etching technics, patterned conductor material layer, to form the first conducting wire 72a and multiple second conducting wires are utilized
74a.D1 extends first conducting wire 72a along a first direction, and is electrically connected with the first contact hole 42.Second conducting wire 74a is along
One direction D1 extends, and is electrically connected with the second contact hole 44 on corresponding semiconductor strip structure 20.First conducting wire 72a
E.g. as source electrode line；Second conducting wire 74a is, for example, as bit line.The material of conductor material layer be, for example, DOPOS doped polycrystalline silicon,
Un-doped polysilicon or combinations thereof, forming method can use chemical vapour deposition technique to be formed.
Fig. 1 D to 5D is please referred to, in the first embodiment of the present invention, memory element 100 includes substrate 10, multiple partly leads
It is body strip structure 20, doped region 12, multiple matrix areas 14, multiple doped regions 16, multiple wordline 22, electric charge storage layer 18, multiple
First contact hole 42, multiple second contact holes 44, the first conducting wire 72a and multiple second conducting wire 74a.Doped region 12 includes multiple
First part 12a and second part 12b, and first part 12a is connected with second part 12b.Also, the second of doped region 12
Part 12b can be electrically connected by the first contact hole 42 and the first conducting wire 72a.Doped region 16 then passes through the second contact hole 44 and the
Two conducting wires 74aIt is electrically connected.
It is noted that the first part 12a due to doped region 12 is connected with second part 12b, therefore each half is led
The first part 12a of doped region 12 in body strip structure 20 can be connected to each other.That is, when doped region 12 is, for example, to do
For memory element source electrode when, the source electrode in each semiconductor bar shape structure 20 can be connected to each other.Also, due to the first contact
Window 42 is electrically connected the second part 12b of doped region 12, therefore the first conducting wire 72a is, for example, to be electrically connected each semiconductor bar shape knot
Source electrode in structure 20.In this way, which the frame of the relativeness and laminated construction between rectilinear memory element can be significantly simplified
Structure maintains original operation efficiency, and compatible with prior art.
Fig. 6 A to Fig. 6 E is according to the upper depending on showing of the manufacturing process of memory element depicted in the second embodiment of the present invention
It is intended to.Fig. 7 A to Fig. 7 E is respectively the diagrammatic cross-section of the A-A' line along Fig. 6 A to Fig. 6 E.Fig. 8 A to Fig. 8 E is respectively along Fig. 6 A
To the diagrammatic cross-section of the B-B ' line of Fig. 6 E.Fig. 9 A to Fig. 9 E is respectively the diagrammatic cross-section of the C-C' line along Fig. 6 A to Fig. 6 E.
Figure 10 A to Figure 10 E is respectively the diagrammatic cross-section of the E-E' line along Fig. 6 A to Fig. 6 E.
The part manufacturing process of the memory element 200 of the second embodiment of the present invention can be with the memory element of first embodiment
100 is identical.More specifically, the substrate 10 in memory element 200, multiple semiconductor strip structures 20, doped region 12, matrix area
14, the manufacturing process of multiple doped regions 16, multiple wordline 22, electric charge storage layer 18 and clearance wall 24 is, for example, such as above-mentioned storage
Person described in element 100, is not repeated here in this.
Referring to Fig. 6 A, Fig. 7 A, Fig. 8 A, Fig. 9 A and Figure 10 A, in each wordline 22 and each semiconductor bar shape
The side of structure 20 is respectively formed after clearance wall 24, removes the part semiconductor strip knot in the second block B2 of substrate 10
Structure 20, to form channel T (as shown in Fig. 6 A, 7A and 8A).Channel T is, for example, to extend along second direction D2.Channel T is exposed
The matrix area 14 (not being painted) of corresponding semiconductor strip structure 20.In the present embodiment, each semiconductor bar shape structure 20
With matrix area 14.In the first block B1, matrix area 14 is located between doped region 16 and the first part 12a of doped region 12；
In the second block B2, matrix area 14 is located on the first part 12a of doped region 12, and channel T exposes matrix area 14.It connects
, in being conformally formed lining 28 in substrate 10, to cover semiconductor strip structure 20 and wordline 22.The material of lining 28 can be
Silica, silicon oxynitride, silicon nitride or combinations thereof, forming method can utilize chemical vapour deposition technique or physical vapour deposition (PVD)
Method.
Referring to Fig. 6 B, Fig. 7 B, Fig. 8 B, Fig. 9 B and Figure 10 B, in formation dielectric layer 26 in substrate 10.Then, sharp
With photoetching and etching technics, part of dielectric layer 26 and part lining 28 are removed, in the second block B2 of substrate 10 and second
Multiple first contact window 42a are formed in area R2；Multiple second contact window 44a are formed in the second area R2；And in
Third contact window 46a is formed in two block B2.Every one first contact window 42a exposes the second part of doped region 12
12b.Every one second contact window 44a exposes the doped region 16 of semiconductor strip structure 20.Third contact window 46a is naked
Expose multiple matrix areas 14 of multiple semiconductor strip structures 20.
Later, in the first contact window 42a, the second contact window 44a and third contact window 46a respectively
Form the first contact hole 42, the second contact hole 44 and third contact hole 46.First contact hole 42 be located at the second block B2 and
In second area R2, and D1 is arranged along a first direction；Second contact hole 44 is located in the second area R2, and arranges along second direction D2
Column；Third contact hole 46 is located in the second block B2, and extends along second direction D2.In an exemplary embodiment, it first connects
Touching window 42 is located at the second block B2 and the secondth area of the side of the outermost semiconductor strip structure 20 on part of substrate 10
In R2.Every one first contact hole 42 is electrically connected the second part 12b of doped region 12.Every one second contact hole 44 is electrically connected institute
The doped region 16 of corresponding semiconductor strip structure 20.Third contact hole 46 is electrically connected the exposed matrix area 14 of channel T.The
First contact hole 42 of the forming method such as first embodiment of one contact hole 42, the second contact hole 44 and third contact hole 46,
Described in second contact hole, it is not repeated here in this.
Referring to Fig. 6 C, Fig. 7 C, Fig. 8 C, Fig. 9 C and Figure 10 C, conductor material layer is formed on the substrate 10 and (is not drawn
Show).Then, using photoetching and etching technics patterned conductor material layer, with formed privates 52, multiple local conducting wires 54 with
And the 5th conducting wire 56.In one embodiment, local conducting wire 54 is located in the first block B1 of 46 two sides of third contact hole.4th leads
D1 extends line 52 along a first direction, and is electrically connected with the first contact hole 42.Each part D1 along a first direction of conducting wire 54
Extend, and is electrically connected with the second contact hole 44 on corresponding semiconductor strip structure 20.5th conducting wire 56 is along first
Direction D1 extends, and is electrically connected with third contact hole 46.The material and forming method of conductor material layer such as first embodiment institute
It states, is not repeated here in this.Then, in formation dielectric layer 30 in substrate 10.Dielectric layer 30 is respectively by privates 52, part
Conducting wire 54 and the 5th conducting wire 56 electrically isolate each other.Material and the forming method of dielectric layer 30 are it has been observed that no longer in this
It is repeated here.
Referring to Fig. 6 D, Fig. 7 D, Fig. 8 D, Fig. 9 D and Figure 10 D, in formation dielectric layer 32 in substrate 10.Then, sharp
With photoetching and etching technics, part of dielectric layer 32 is removed, to form multiple 4th contact window 60a, multiple in substrate 10
5th contact window 60b and the 6th contact window 60c.4th contact window 60a exposes privates 52, and the 5th connects
Touching window opening 60b exposes local conducting wire 54, and the 6th contact window 60c exposes the 5th conducting wire 56.Later, in the 4th contact
Window, which is open in 60a, forms the 4th contact hole 61a, forms the 5th contact hole 61b in the 5th contact window 60b, connects in the 6th
It touches in window opening 60c and forms the 6th contact hole 61c.
Referring to Fig. 6 E, Fig. 7 E, Fig. 8 E, Fig. 9 E and Figure 10 E, conductor material layer is formed on the substrate 10 and (is not drawn
Show).Then, patterned conductor material layer, to form the first conducting wire 72b, multiple second conducting wire 74b and privates 76.The
D1 extends one conducting wire 72b along a first direction, and electrically via the 4th contact hole 61a and privates 52 and the first contact hole 42
Connection.D1 extends second conducting wire 74b along a first direction, the local conducting wire 54 on corresponding semiconductor strip structure 20
Top.Also, the second conducting wire 74b is across third contact hole 46, via the 5th contact hole 61b and corresponding 54 electricity of local conducting wire
Property connection.D1 extends privates 76 along a first direction, and contacts via the 6th contact hole 61c and the 5th conducting wire 56 with third
Window 46 is electrically connected.First conducting wire 72b, the second conducting wire 74b and privates 76 be, for example, respectively as source electrode line, bit line with
And matrix line.Material and the forming method of conductor material layer in this it has been observed that be not repeated here.
Referring again to Fig. 1 D, Fig. 4 D and Fig. 5 D, the memory element of the first embodiment of the present invention includes: substrate 10, more
It is a semiconductor strip structure 20, the first doped region 12, multiple second doped regions 16, multiple wordline 22, electric charge storage layer 18, multiple
First contact hole 42, multiple second contact holes 44, the first conducting wire 72 and multiple second conducting wires 74.
Fig. 1 D is please referred to, substrate 10 includes two the first block B1 and the second block B2.Second block B2 is located at two the
Between one block B1, every one first block B1 includes multiple firstth area R1 and multiple secondth area R2, and the first area R1 and the secondth area
R2 is alternateed.
D referring to figure 4., multiple semiconductor strip structures 20 are located in substrate 10.Each semiconductor bar shape structure 20 along
First direction D1 extends.First doped region 12 includes multiple first part 12a and second part 12b.Each first part 12a
In the lower part of corresponding semiconductor strip structure 20；Second part 12b is located at the surface of substrate 10, and first part 12a with
Second part 12b is connected.Multiple second doped regions 16 are located at the top of each semiconductor bar shape structure 20.
Fig. 1 D and Fig. 5 D are please referred to, multiple wordline 22 are located in the substrate 10 of every one first area R1.Each 22 edge of wordline
Second direction D2 extend, cover the partial sidewall and atop part of each semiconductor bar shape structure 20.First direction D1 and second
Direction D2 is different.Electric charge storage layer 18 is between semiconductor strip structure 20 and wordline 22.
Fig. 1 D and Fig. 4 D are please referred to, multiple first contact holes 42 are located in the second block B2 and the second area R2, and edge
First direction D1 arrangement.Every one first contact hole 42 is electrically connected the second part 12b of the first doped region 12.Multiple second connect
Touching window 44 is located at least in the second area R2, and every one second contact hole 44 is electrically connected the second corresponding doped region 16.First leads
Line 72a is located in substrate 10 and D1 extends along a first direction, and is electrically connected with the first contact hole 42.Multiple second conducting wires
74a is located in substrate 10, every one second conducting wire 74a along a first direction D1 extend, and with corresponding semiconductor strip structure
The second contact hole 44 on 20 is electrically connected.
It is noted that since doped region 12 includes first part 12a and second part 12b, and first part 12a with
Second part 12b is connected.Therefore, the first part 12a of the doped region 12 in each semiconductor bar shape structure 20 can pass through
Two part 12b and be connected with each other.In one embodiment, when doped region 12 is, for example, as source electrode, each semiconductor bar shape knot
Source electrode in structure 20 can be electrically connected to each other.
Referring again to Fig. 6 A, Fig. 9 A and Figure 10 A, the memory element 200 that the second embodiment of the present invention provides, compared to
The memory element 100 of first embodiment in the second block B2 there is channel T, channel T to extend along second direction, expose
Matrix area 14.In other words, in the first block B1, matrix area 14 be located at doped region 14 and doped region 12 first part 12a it
Between；In the second block B2, matrix area 14 is located on the first part 12a of doped region 12, and channel T exposes matrix area 14.
In addition, the memory element 200 of second embodiment further includes: third contact hole 46, privates 52, multiple parts are led
Line 54, the 5th conducting wire 56, the 4th contact hole 61a, the 5th contact hole 61b, the 6th contact hole 61c and privates 76.
Fig. 6 E and Fig. 9 E is please referred to, third contact hole 46 is located in the second block B2 of substrate 10, and along second party
Extend to D2, and third contact hole 46 is electrically connected the matrix area 14 of part semiconductor bar shape structure 20.Privates 76 is located at
In substrate 10, D1 extends along a first direction, and electrically connects via the 6th contact hole 61c, the 5th conducting wire 56, third contact hole 46
Connect the matrix area 14 of semiconductor strip structure 20.Therefore, when matrix area 14 is, for example, the matrix as memory element, can pass through
Privates 76 applies voltages to matrix, to control the current potential of matrix.In this way, which the current potential of matrix can clearly be learnt, avoid
The current potential of matrix by other biass coupling effect and be floating (floating) state.
Figure 11 A is the schematic diagram according to memory array structure depicted in the first embodiment of the present invention.
Figure 11 A is please referred to, Figure 11 A is painted multiple memory cell strings (cell strings) 301.Memory cell string 301 passes through
By multiple bit lines BL1~BLn(wherein n is greater than 1 integer), source electrode line SL and a plurality of wordline WL1~WL2m(wherein m is big
In 1 integer) concatenation, to be arranged in a storage array (memory array) in column direction and line direction.Every one first area
R1 (the firstth area R1 in such as Fig. 1 D) is formed by multiple 301 arranged in parallel of memory cell string.In one embodiment, each storage is single
Member string 301 may include 32 storage units or more.
Source electrode line SL may be coupled to above-mentioned first conducting wire 72a (as shown in Figure 4 D), to concatenate each storage in storage array
Source electrode (such as the doped region 12 in Fig. 4 D of unit.At this point, doped region 12 is, for example, as common source line).Bit line BL1、
BL2...BLnIt can be respectively coupled to above-mentioned second conducting wire 74a (as shown in Figure 4 D), concatenated in storage array respectively with a line
The drain electrode (such as doped region 16 in Fig. 4 D) of multiple storage units.Wordline WL1、WL2...WL2mStorage array can be concatenated respectively
The grid of multiple storage units of middle same row.In one embodiment, bit line BL1、BL2...BLnIt can be respectively coupled to bit line crystalline substance
Body pipe BLT1、BLT2...BLTn.Bit line BL1With BL3It may be coupled to global bit line (Global bit line) GBL1.Bit line BL2
With BL4It may be coupled to global bit line GBL2.Control voltage V1Via global bit line GBL1Through bitline transistor BLT1With BLT3's
ON/OFF and be applied to bit line BL1With BL3。
In one embodiment of this invention, can via respectively to source electrode corresponding to storage unit M1, drain electrode with grid
Apply different size of voltage, to be read out the operation of (read), programming (program) or erasing (erase).Citing and
Speech, includes: in bitline transistor BLT to the storage unit M1 method being read2Apply 10V voltage to turn it on, by
This to be applied to global bit line GBL2Control voltage V2(such as V2=0V) via bitline transistor BLT2With bit line BL2, mention
It is supplied to the drain electrode of storage unit M1, as drain voltage Vd；Apply 10V voltage in source electrode line transistor SLT to turn it on, so that
The control voltage of 1.6V, the source electrode of storage unit M1 is provided to via source electrode line SL, as source voltage Vs；And with storage
The wordline WL that the grid of unit M1 is connectediThe voltage for applying e.g. 0V to 10V, as grid voltage Vg.Whereby,
It is read out the operation of storage unit M1.It should be understood that the scope of the present invention is not limited to above-mentioned specific voltage.In another implementation
It, can also be via source electrode corresponding to change storage unit M1, drain electrode with the voltage with grid, with what is be programmed or wipe in example
Operation.
Figure 11 B is the schematic diagram according to memory array structure depicted in the second embodiment of the present invention.
Figure 11 B is please referred to, Figure 11 B is painted multiple memory cell strings 302.Multiple memory cell strings 302 are via matrix line
BdL, multiple bit lines BL1~BLn(wherein n is greater than 1 integer), source electrode line SL and a plurality of wordline WL1~WL2m(wherein m is
Integer greater than 1) concatenation, to be arranged in a storage array in column direction and line direction.Such as above-mentioned first embodiment, source electrode
Line SL can concatenate the source electrode of each storage unit in storage array.Bit line BL1、BL3...BLnThe leakage of multiple storage units can be concatenated
Pole.Wordline WL1、WL2...WL2mThe grid of multiple storage units can be concatenated.It is worth noting that, compared to first embodiment, this
The matrix line BdL of embodiment may be coupled to above-mentioned privates 76 (as illustrated in fig. 6e), to concatenate each storage in storage array
The matrix (such as matrix area 14 in Fig. 9 E) of unit.That is, in addition to applying drain voltage Vd, source voltage VsWith with grid
Pole tension VgExcept, the present embodiment more can be in the matrix line transistor BdLT application e.g. control voltage of 0V, via matrix line
BdL is provided to the matrix of storage unit M2, as matrix voltage Vb, to control the current potential of matrix.
Figure 12 A to Figure 12 B is showing according to the memory element of reverse read operation depicted in one embodiment of the invention
It is intended to.Figure 13 A to Figure 13 B is to inject (channel hot according to channel hot electron depicted in one embodiment of the invention
Electron injection, CHEI) operation memory element schematic diagram.Figure 14 A to Figure 14 B is real according to of the invention one
Energy band depicted in example is applied to (the band-to-band tunneling induced hot of hot hole caused by energy band tunnel
Hole, BTBT HH) implant operation memory element schematic diagram.Figure 15 A to Figure 15 B is according to one embodiment of the invention institute
The schematic diagram of the memory element of FN (Fowler-Nordheim) the electric hole implant operation being painted.Figure 16 A to Figure 16 B is according to this
The schematic diagram of the memory element of the operation of FN electron injection depicted in one embodiment of invention.
Storage unit M1, M2 can be programmed or wipe by various methods.For example, storage unit M1, M2 can
It is programmed in such a way that channel hot electron injection or energy band are to hot hole caused by energy band tunnelling.In addition, storage unit M1, M2
The erasing operation of storage unit can be carried out by modes such as BTBT HH, FN electron injection or FN electric hole injections.Table 1 to table 3 arranges
Three kinds of operating conditions that storage unit is read out out, program and is wiped.It should be understood that the scope of the present invention is not limited to institute
The operating method and operation voltage enumerated.
Table 1 is please referred to, the method for being read out, programming and wiping to storage unit in operating condition 1 is, for example, respectively
Reverse reading, channel hot electron injection and energy band inject hot hole caused by energy band tunnel.
Table 1
Figure 12 A is please referred to, the structure of memory element is as shown in earlier figures 1D or 6E.The drain electrode of semiconductor strip structure 20a
It e.g. can be with bit line BL1(as shown in Figure 11 A or Figure 11 B) connection, semiconductor strip structure 20b are, for example, and bit line BL3Even
It connects.By the way that bitline transistor BLT is connected1, to select bit line BL1, so that being applied to global bit line GBL1Voltage be provided to and partly lead
The drain electrode of body strip structure 20a.
Referring to table 1, Figure 12 A, the operating condition for reading position 1 (Bit 1) is, for example, that will read bias to be applied to institute
The source terminal (source voltage Vs=1.6V) of the semiconductor strip structure 20a of selection applies drain voltage V in drain electroded=0V and
Apply grid voltage V in gridg=0-12V, and matrix voltage VbIt can be 0V or floating state；Non-selected semiconductor strip knot
The drain voltage V of structure 20bdFor floating state (F), to sense the charge in drain side junction.Figure 12 B is please referred to, position 2 is read
The operation of (Bit 2) is then that will read bias to be applied to drain electrode end, to sense the charge on source side injection to complete to read
Operation.
Referring to table 1, Figure 13 A, in operating condition 1, storage unit is carried out with channel hot electron injection mode
Programming.The operating condition of program bit 1 is, for example, to apply grid voltage Vg=12V applies intermediate level so that channel conductive
Drain voltage Vd=4V, source voltage Vs=0V and matrix voltage Vb=0V/F, to form the electric field from source electrode to drain electrode.When
When bias between source electrode and drain electrode is quite big, in that will generate excessive thermoelectron on channel, the thermoelectron of part can injection grid
Pole is to be programmed.Conversely, please referring to Figure 13 B, the operating condition of program bit 2 is then the source voltage V for applying intermediate levels=
4V, to form the electric field from drain electrode to source electrode.
Referring to table 1, Figure 14 A, in operating condition 1, with energy band to hot hole injection side caused by energy band tunnel
Formula carries out erasing operation to storage unit.The operating condition for wiping position 1 is, for example, to apply grid voltage Vg=-8V is applied simultaneously
Add drain voltage Vd=5V.Under these bias conditions, hot hole caused by energy band tunnelling is injected by energy band and carries electrification
Stream is injected into electric charge storage layer 18 to wipe position 1.Conversely, please referring to Figure 14 B, the operating condition of erasing position 2 is then application source
Pole tension Vs=5V.
Table 2 is please referred to, in operating condition 2, the method difference for being read out, programming and wiping to storage unit is for example
It is reverse reading, channel hot electron injection and the injection of FN electric hole.
Table 2
In operating condition 2, the operation being programmed in a manner of channel hot electron injection in this as described above, no longer add
To repeat.
Referring to table 2, Figure 15 A and Figure 15 B, in operating condition 2, it can be injected with+FN electric hole or-FN electric hole is infused
The mode entered wipes storage unit.Figure 15 A is please referred to, is, for example, with the operation that+FN electric hole injection mode is wiped
Electric hole is set to be injected into electric charge storage layer 18 from grid 22.Its operating condition is, for example, to apply grid voltage Vg=10V, applies simultaneously
Drain voltage Vd=-10V, source voltage Vs=-10V, matrix voltage Vb=-10V or floating, with source electrode 12 and drain electrode 16 with
Biggish electric field is formed between grid 22, so that the electric hole in grid 22 can enter electric charge storage layer 18 by FN tunneling effect,
And then wipe data.Figure 15 B is please referred to, is, for example, to make electric hole from source with the operation that the injection of-FN electric hole is wiped in contrast
Pole 12, matrix 14 and drain electrode 16 are injected into electric charge storage layer 18.Its operating condition is, for example, to apply grid voltage Vg=-10V,
Apply drain voltage V simultaneouslyd=10V, source voltage Vs=10V, matrix voltage Vb=10V or floating, so that source electrode 12, matrix
14 and drain electrode 16 in electric hole can enter charge storage region 18 by FN tunneling effect, and then wipe data.
Table 3 is please referred to, the method for being read out, programming and wiping to storage unit in operating condition 3 is, for example, respectively
Reverse reading, energy band is injected to hot hole caused by energy band tunnel and FN electron injection, as shown in table 3.
Table 3
In operating condition 3, the operation being programmed in such a way that energy band is to the injection of hot hole caused by energy band tunnel is such as
By the operation of operating condition 1 wiped in such a way that energy band is to the injection of hot hole caused by energy band tunnel, no longer add in this
To repeat.
Referring to table 3, Figure 16 A and Figure 16 B, in operating condition 3, can be infused with+FN electron injection or-FN electronics
The mode entered wipes storage unit.Figure 16 A is please referred to, the operation wiped in a manner of+FN electron injection is, for example,
Electronics is set to be injected into electric charge storage layer 18 from source electrode 12, matrix 14 and drain electrode 16.Its operating condition is, for example, to apply grid electricity
Press Vg=10V, while applying drain voltage Vd=-10V, source voltage Vs=-10V, matrix voltage Vb=-10V or floating, with
Biggish electric field is formed between source electrode 12 and drain electrode 16 and grid 22, so that the electricity in source electrode 12, matrix 14 and drain electrode 16
Son can enter electric charge storage layer 18 by FN tunneling effect, and then wipe data.Figure 16 B is please referred to, in contrast, with-FN electricity
The operation that sub- injection mode is wiped for example makes electronics be injected into electric charge storage layer 18 from grid 22.Its operating condition is, for example,
Apply grid voltage Vg=-10V, while applying drain voltage Vd=10V, source voltage Vs=10V, matrix voltage Vb=10V or
It is floating, so that electronics is injected into electric charge storage layer 18 from grid 22.
In addition, the injection of above-mentioned FN electric hole and the operation of FN electron injection in addition to can be used for wiping memory data it
Outside, before the operation for carrying out above-mentioned programming or erasing to storage unit, as the start voltage (threshold of storage unit
Voltage, Vt) because process variation or other factors are not reached and are taken, it can be adjusted using the method for FN electric hole or electron injection
Start voltage, to meet required target value.In one embodiment, start voltage can be promoted by the method for FN electron injection.
In another embodiment, start voltage can be reduced by the method that FN electric hole is injected.
In conclusion the present invention can be electrically connected the source electrode in each semiconductor bar shape structure by the first contact hole.Such as
This one, the framework of the relativeness and laminated construction between rectilinear memory element can be significantly simplified, maintain original behaviour
Make efficiency, and compatible with prior art.Also, matrix can be applied voltages to by privates, to control the current potential of matrix.Such as
This one, can clearly learn the current potential of matrix, the current potential of matrix is avoided to be floating state by the coupling effect of other biass.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, thus it is of the invention
Protection scope subject to be defined depending on appended claims range.
Claims (11)
1. a kind of memory element, comprising:
One substrate, the substrate include multiple first blocks and multiple second blocks, these first blocks and these the second block phases
Mutually alternately, every one first block includes two the firstth areas and one second area, and secondth area is between described two firstth areas；?
There is a channel, which extends along a second direction in these second blocks；
Multiple semiconductor strip structures are located in the substrate, wherein each semiconductor bar shape structure has a matrix area, each half
Conductor strip structure extends along a first direction, and the first direction is different from the second direction；
One first doped region, including multiple first parts and a second part, each first part are located at corresponding this and partly lead
The lower part of body strip structure, the second part are located at the surface of the substrate, these first parts are connected with the second part；
Multiple second doped regions, every one second doped region are located at the top of the corresponding semiconductor strip structure；
Multiple wordline, in the substrate in every one first area, each wordline extends along the second direction, covering it is each these half
The partial sidewall and atop part of conductor strip structure；
One electric charge storage layer, between these semiconductor strip structures and these wordline；
Multiple first contact holes are located in these second blocks and these secondth areas, arrange along the first direction, and every 1 the
One contact hole is electrically connected the second part of first doped region；
Multiple second contact holes are located at least in these secondth areas, and every one second contact hole is electrically connected corresponding this second
Doped region；
One first conducting wire is located in the substrate, which extends along the first direction, and electric with these first contact holes
Property connection；
Multiple second conducting wires are located in the substrate, and every one second conducting wire extends along the first direction, and with corresponding this half
These second contact holes on conductor strip structure are electrically connected；
Multiple third contact holes are located in these second blocks, which extends along the second direction, and should
Third contact hole is electrically connected these exposed matrix areas of the channel；And
One privates is located in the substrate, extends along the first direction, and is electrically connected with these third contact holes.
2. memory element according to claim 1, in which:
The first part of the matrix area, second doped region in the semiconductor strip structure and first doped region it
Between；And
In these second blocks, these the second contact holes are further included.
3. memory element according to claim 1, in which:
In these first blocks, which is located between second doped region and the first part of first doped region；
And
In these second blocks, which is located in the first part of first doped region, and the channel exposes this
Matrix area.
4. memory element according to claim 1, further includes:
It is multiple part conducting wires, in these first blocks of the third contact hole two sides, it is each part conducting wire along this first
Direction extends, and is electrically connected with these second contact holes on the corresponding semiconductor strip structure, and
Every one second conducting wire, above these local conducting wires on the corresponding semiconductor strip structure and across the third
Contact hole is electrically connected via multiple 4th contact holes and these corresponding local conducting wires.
5. a kind of manufacturing method of memory element, comprising:
A substrate is provided, which includes multiple first blocks and multiple second blocks, these first blocks and these secondth areas
Block alternates, and every one first block includes two the firstth areas and one second area, secondth area be located at described two firstth areas it
Between；
Multiple semiconductor strip structures are formed, in the substrate, wherein each semiconductor bar shape structure is prolonged along a first direction
It stretches；
One first doped region is formed, which includes multiple first parts and a second part, each first part position
In the lower part of the corresponding semiconductor strip structure, which is located at the surface of the substrate, and these first parts with
The second part is connected；
Multiple second doped regions are formed, in the top of each semiconductor bar shape structure；
Form multiple wordline, in the substrate in every one first area, each wordline extends along a second direction, covering it is each these
The partial sidewall and atop part of semiconductor strip structure, the first direction are different from the second direction；
An electric charge storage layer is formed, between these semiconductor strip structures and these wordline；
Multiple first contact holes are formed, in these second blocks and these secondth areas, are arranged along the first direction, it is each
First contact hole is electrically connected the second part of first doped region；
Multiple second contact holes are formed, until less than in these secondth areas, every one second contact hole is electrically connected corresponding this
Two doped regions；
Form one first conducting wire, in the substrate, which extends along the first direction, and with these the first contact holes
It is electrically connected；
Multiple second conducting wires are formed, in the substrate, every one second conducting wire extends along the first direction, and should with corresponding
Second contact hole on semiconductor strip structure is electrically connected；
These semiconductor strip structures of part in these second blocks are removed, to form a channel, along the second direction
Extend, which exposes these matrix areas of these corresponding semiconductor strip structures；
Multiple third contact holes are formed, in these second blocks, each third contact hole extends along the second direction, and every
One third contact hole is electrically connected these exposed matrix areas of the channel；And
A privates is formed, in substrate, which extends along the first direction, and electric with these third contact holes
Property connection.
6. the manufacturing method of memory element according to claim 5, wherein formed these semiconductor strip structures, this first
The method of doped region and these the second doped regions includes:
Patterned features substrate, to form these semiconductor strip structures；
An ion implantation technology is carried out, admixture is flowed into the top of each semiconductor bar shape structure and the table of the substrate
Face；And
A hot tempering process is carried out, so that these admixtures form first doped region and these second doped regions.
7. the manufacturing method of memory element according to claim 5, further includes:
Form multiple local conducting wires, in these first blocks, each part conducting wire extends along the first direction, and with pair
These second contact holes on the semiconductor strip structure answered are electrically connected, and
Every one second conducting wire, above these local conducting wires on the corresponding semiconductor strip structure and across these the
Three contact holes are electrically connected via multiple 4th contact holes and these corresponding local conducting wires.
8. a kind of storage array, including memory element described in any one of Claims 1-4, the storage array include:
Multiple storage units are arranged in the array of multirow and multiple row, these storage units include first doping as source electrode
Area and these second doped regions as drain electrode；
Multiple bit lines, each bit line are coupled to these second doped regions of these storage units of same a line；
A plurality of common source line, each common source line are coupled to first doped region of these storage units of same row；With
And
Source line is coupled to these common source lines, and is electrically connected with first doped region of these storage units,
Wherein each wordline is coupled to multiple grids of these storage units of same row.
9. storage array according to claim 8 further includes a matrix line, it is coupled to multiple matrixes of these storage units
Area.
10. a kind of operating method of the storage array as described in any one of claim 8 to 9, the operating method include:
Select an at least storage unit；
Apply a wordline corresponding to a first voltage to storage unit selected by one；
Apply a bit line corresponding to a second voltage to the selected storage unit；And
Apply the source electrode line of a tertiary voltage to the storage array.
11. a kind of operating method as claimed in claim 10 further includes and applies one the 4th voltage to the selected storage unit
Corresponding matrix line.
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| CN101587898A (en) * | 2008-01-02 | 2009-11-25 | 旺宏电子股份有限公司 | A semiconductor structure with an integrated circuit component and formation and operation method thereof |
| CN101826545A (en) * | 2009-03-03 | 2010-09-08 | 旺宏电子股份有限公司 | Integrated circuit self aligned 3d memory array and manufacturing method |
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| KR100635924B1 (en) * | 2004-11-17 | 2006-10-18 | 삼성전자주식회사 | Method of operating a flash memory device |
| US7511332B2 (en) * | 2005-08-29 | 2009-03-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical flash memory |
| KR20090126077A (en) * | 2008-06-03 | 2009-12-08 | 삼성전자주식회사 | Memory semiconductor apparatus and method for manufacturing with the same |
| US8772848B2 (en) * | 2011-07-26 | 2014-07-08 | Micron Technology, Inc. | Circuit structures, memory circuitry, and methods |
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| CN101826545A (en) * | 2009-03-03 | 2010-09-08 | 旺宏电子股份有限公司 | Integrated circuit self aligned 3d memory array and manufacturing method |
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