CN101221923B

CN101221923B - Gated diode nonvolatile memory process

Info

Publication number: CN101221923B
Application number: CN2007101927749A
Authority: CN
Inventors: 欧天凡; 蔡文哲; 赖二琨; 高瑄苓
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2006-11-20
Filing date: 2007-11-20
Publication date: 2010-06-09
Anticipated expiration: 2027-11-20
Also published as: CN101221810A; CN101388394B; CN101221955B; CN101221923A; CN101388394A; CN101221810B; CN101221955A

Abstract

A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Description

Gated diode nonvolatile memory process

The present patent application case advocates that the name that proposed on November 20th, 2006 is called the temporary transient application case No.60/866 of United States Patent (USP) of " Gated DiodeNonvolatile Memory ", the United States Patent (USP) formal application case No.1 1/619 of " Gated Diode Nonvolatile Memory Process " that on January 2nd, 583 and 2007 proposed, 082 priority, the invention people is Ou Tianfan, Cai Wenzhe, Lai Erkun, high Xuan Siberian cocklebur and Liao Yiying.

Technical field

The present invention relates to the erasable Nonvolatile memory of electrically programmable (EEPROM), further, relate to the bias voltage setting of Charge Storage internal memory, its content in can the charge storing structure of high sensitive ground reading cells.

Background technology

The electrically programmable erasable nonvolatile memory technology that is commonly called as charge storing structures such as EEPROM, flash memory is widely used.EEPROM and flash memory adopt the memory cell structure of some.Along with the integrated circuit size is day by day dwindled, use the charge-trapping dielectric layer just to become and become more and more important, but have micro and make advantages such as simple and easy because of it as the memory cell structure on basis.Industry has adopted the memory cell structure of multiple charge-trapping dielectric layer, for example PHINES, SONOS etc.These memory cell structures utilize charge-trapping dielectric layer seizure electric charges such as silicon nitride, come storage data.If electric charge capture layer captures enough net negative charges, the threshold voltage of memory cell promptly can increase.From electric charge capture layer, remove negative electrical charge or increase positive charge, all can reduce the threshold voltage of memory cell.

Conventional memory cell structure utilizes transistor arrangement, and it has source electrode, drain and gate.Yet the normal transistor structure has source electrode and drain diffusion region, and it utilizes the sag side direction to separate.This side direction separated structures promptly is further to reduce one of reason of Nonvolatile memory size.

Therefore, non-volatile memory cells must be researched and developed new technology, with the reduction size, and has the higher susceptibility that reads.

Summary of the invention

One of purpose of the present invention provides a kind of method of making the non-volatile memory device integrated circuit, and for example this element comprises the diode with first node and Section Point.This diode can be Xiao Jite diode and pn diode in different embodiment.Diverse ways embodiment comprises the following step:

Form on the second layer of second charge type of ground floor in this integrated circuit of first charge type in this integrated circuit, wherein this first charge type is opposite with this second charge type.

Remove the part of this ground floor and this second layer, to form the first diode node and form the second diode node in this ground floor in this second layer, this first diode node of this first charge type is with respect to the second diode node of this second charge type.In different embodiment, this first diode node can be both one of: doped polycrystalline silicon, or the part of the bit line of this element of access; This second diode node can be both one of: the well region in the integrated circuit, or the substrate in the integrated circuit.In addition, this first diode node and the second diode node also can be to be at least one of monocrystalline, polycrystalline or amorphous.This first diode node and the second diode node are separated by knot.In different embodiment, this knot can be one of following: homojunction, heterojunction and gradient heterojunction.In certain embodiments, this knot can be a diffusion obstacle knot.

Form spacer medium district in this integrated circuit to isolate at least a portion and the adjacent elements of this second diode node, so this spacer medium district makes this knot not be capped.In certain embodiments, this step is undertaken by following: utilize this spacer medium district to cover this knot at least, and remove covering this spacer medium zone of this knot at least.

Form charge storing structure and one or more storage medium structure in this integrated circuit, the part that this charge storing structure and one or more storage medium structure cover this knot at least and be adjacent to this first diode node and this second diode node of this knot, therefore these one or more storage medium structures to small part between this charge storing structure and this first and second diode node, and to small part between the gate-voltage source of this charge storing structure and this element.In certain embodiments, this charge storing structure has when reverse biased, by the current measurement of flowing through between this first diode node and this second diode node, the charge storage state that is determined.

Form this grid of this gate-voltage source of supplying with this element.

Another object of the present invention provides a kind of non-volatile memory device in integrated circuit.This element comprises diode, and it has first node and Section Point, and this element utilizes technology described herein to form.

Another purpose of the present invention provides a kind of method of making non-volatile storage element array.Each this element comprises diode, and it has a first node and a Section Point.Diverse ways embodiment comprises the following step:

Remove the part of this ground floor and this second layer, in this ground floor, to form the first diode node and in this second layer, to form the second diode node, it is right to cause each this element to comprise the vicinity that this first diode node and this second diode node form, this first node of each this element and this Section Point are separated by knot.In certain embodiments, this first diode node is a bit line, and the bit line and the word line of the specific non-volatile memory device in this non-volatile storage element array of access.

It is capable of at least a portion of this second diode node of isolating each this element and the adjacent lines of this element to form spacer medium in this integrated circuit, and this knot of each this element is covered by the capable institute of this spacer medium.

Each this element is formed charge storing structure and one or more storage medium structure, the part that this charge storing structure and one or more storage medium structure cover this knot at least and be adjacent to this first diode node and this second diode node of this knot, therefore these one or more storage medium structures to small part between this charge storing structure and this first and second diode node, and to the small part bit between the gate-voltage source of this charge storing structure and this element.

Form the word line of supplying with this gate-voltage source of each this element in this integrated circuit.

The many distortion relevant with each unit are described in herein among other the embodiment.

A further object of the present invention provides a kind of non-volatile storage element array in integrated circuit.Each this element comprises diode, and it has a first node and a Section Point, and this array utilizes technology described herein to form.

Description of drawings

Fig. 1 is the gated diode nonvolatile memory cell schematic diagram of simplifying;

Fig. 2 A, Fig. 2 B, the gated diode nonvolatile memory cell schematic diagram of Fig. 2 C for simplifying show the multiple charge storing structure that utilizes the different materials made;

Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D are the gated diode nonvolatile memory cell schematic diagrames of simplifying, and show the various embodiments of diode structure, for example pn diode and Schottky diode;

Fig. 4 A and Fig. 4 B are the gated diode nonvolatile memory cell schematic diagrames of simplifying, and show the pn diode with homojunction;

Fig. 5 is the gated diode nonvolatile memory cell schematic diagram of simplifying, and shows the pn diode with heterojunction;

Fig. 6 A and Fig. 6 B are the gated diode nonvolatile memory cell schematic diagrames of simplifying, and show to carry out the situation that electrons tunnel is injected;

Fig. 7 A and Fig. 7 B are the gated diode nonvolatile memory cell schematic diagrames of simplifying, and carry out the situation that energy interband hot electron injects in the display unit;

Fig. 8 A and Fig. 8 B are the gated diode nonvolatile memory cell schematic diagrames of simplifying, and carry out the hole in the display unit and wear the situation that tunnel injects;

Fig. 9 A and Fig. 9 B are the gated diode nonvolatile memory cell schematic diagrames of simplifying, and carry out the situation that energy interband hot hole injects in the display unit;

Figure 10 A and Figure 10 B are the gated diode nonvolatile memory cell schematic diagrames of simplifying, and carry out the situation of energy interband sensing in the display unit, wherein have the clean positive charge or the net negative charge of varying number, but the characterization charge storing structure;

Figure 11 A and Figure 11 B are the gated diode nonvolatile memory cell schematic diagrames of simplifying, carry out the situation of energy interband sensing in the display unit, the clean positive charge or the net negative charge that wherein have varying number, but its characterization charge storing structure, but the arrangement of its diode node is different from Figure 10 A and Figure 10 B;

Figure 12 A shows to have the interior neighboring gates diode non-volatile memory cell rough schematic view that is connected Section Point and does not have interior connection Section Point respectively with Figure 12 B;

Figure 13 A shows to have the interior gated diode nonvolatile memory cell array that is connected the Section Point stringer with Figure 13 B, carries out the rough schematic view of energy interband sensing;

Figure 14 A is not have the interior gated diode nonvolatile memory cell array that is connected the Section Point stringer with Figure 14 B, carries out the rough schematic view of energy interband sensing;

Figure 15 A is to have the interior gated diode nonvolatile memory cell array that is connected the Section Point stringer with Figure 15 B, carries out the rough schematic view of energy interband sensing, and wherein the doping arrangement of diode structure is different from Figure 13 A, Figure 13 B, Figure 14 A and Figure 14 B;

Figure 16 A shows do not have the interior gated diode nonvolatile memory cell array that is connected the Section Point stringer with Figure 16 B, carries out the rough schematic view of energy interband sensing, and wherein the doping arrangement of diode structure is different from Figure 13 A, Figure 13 B, Figure 14 A and Figure 14 B;

Figure 17 A, Figure 17 B, Figure 17 C carry out the rough schematic view that electrons tunnel is injected for connecting the neighboring gates diode non-volatile memory cell of Section Point in not having on discrete cell;

Figure 18 A, Figure 18 B, Figure 18 C carry out the rough schematic view that energy interband hot hole injects for connecting the neighboring gates diode non-volatile memory cell of Section Point in not having on discrete cell;

Figure 19 A, Figure 19 B, Figure 19 C are the profile of gated diode nonvolatile memory cell array, and between the wherein different arrays, stringer has different interior the connections with Section Point for word line, first node stringer;

Figure 20 is the integrated circuit rough schematic view with gated diode nonvolatile memory cell array and control circuit;

Figure 21 A, Figure 21 B, Figure 21 C, Figure 21 D, Figure 21 E, Figure 21 F, Figure 21 G, Figure 21 H show a kind of making flow chart example of gated diode nonvolatile storage array;

Figure 22 A shows do not have the interior neighboring gates diode non-volatile memory cell that is connected Section Point with Figure 22 B, carries out the rough schematic view of energy interband sensing therein on the discrete cell;

Figure 23 A, Figure 23 B, Figure 23 C, Figure 23 D, Figure 23 E, Figure 23 F, Figure 23 G, Figure 23 H show a kind of making flow chart example of gated diode nonvolatile storage array;

Figure 24 is the perspective view of gated diode nonvolatile memory cell array, and it is the making flow process made with Figure 23 A, Figure 23 B, Figure 23 C, Figure 23 D, Figure 23 E, Figure 23 F, Figure 23 G and Figure 23 H;

Figure 25 is the gated diode nonvolatile memory cell rough schematic view of similar Fig. 1, but wherein increases diffusion obstacle knot to this diode structure;

Figure 26 A, Figure 26 B, Figure 26 C are the gated diode nonvolatile memory cell rough schematic view that is similar to Fig. 2 A, Fig. 2 B, Fig. 2 C, and it shows the multiple charge storing structure of different materials made, tie to diode structure but wherein increase the diffusion obstacle;

Figure 27 A, Figure 27 B, Figure 27 C, Figure 27 D figure are the gated diode nonvolatile memory cell rough schematic view that is similar to Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D, it shows the embodiment of multiple diode structure, for example pn diode and Schottky diode are tied to this diode structure but wherein increase the diffusion obstacle;

Figure 28 A, Figure 28 B are the gated diode nonvolatile memory cell rough schematic view of similar Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D, and its demonstration has the pn diode embodiment of homojunction, but wherein increase diffusion obstacle knot to this diode structure;

Figure 29 is the gated diode nonvolatile memory cell rough schematic view that is similar to Fig. 5, and its demonstration has the pn diode embodiment of heterojunction, but wherein increases diffusion obstacle knot to this diode structure;

Figure 30 A, Figure 30 B, Figure 30 C, Figure 30 D, Figure 30 E, Figure 30 F are another making flow implementation example of gated diode nonvolatile memory cell array;

Figure 31 A, Figure 31 B, Figure 31 C, Figure 31 D, Figure 31 E, Figure 31 F, Figure 31 G, Figure 31 H, Figure 31 I are the making flow implementation example of gated diode nonvolatile memory cell array, and wherein diode structure has diffusion obstacle knot;

Figure 32 is the perspective view of grid internal memory Nonvolatile storage array, have diffusion obstacle knot in its diode structure, and the making of this knot utilizes the flow process of Figure 31 A, Figure 31 B, Figure 31 C, Figure 31 D, Figure 31 E, Figure 31 F, Figure 31 G, Figure 31 H, Figure 31 I;

Figure 33 A and Figure 33 category-B are similar to Fig. 6 A and Fig. 6 B, for the gated diode nonvolatile memory cell is carried out the rough schematic view that electrons tunnel is injected, tie to diode structure but increase the diffusion obstacle;

Figure 34 A and Figure 34 category-B are similar to Fig. 7 A and Fig. 7 B, carry out the rough schematic view that energy interband hot electron injects for the gated diode nonvolatile memory cell, tie to diode structure but wherein increase the diffusion obstacle;

Figure 35 A and Figure 35 category-B are similar to Fig. 8 A and Fig. 8 B, carry out the hole for the gated diode nonvolatile memory cell and wear the rough schematic view that tunnel injects, and tie to diode structure but wherein increase the diffusion obstacle;

Figure 36 A and Figure 36 category-B are similar to Fig. 9 A and Fig. 9 B, carry out the rough schematic view that energy interband hot hole injects for the gated diode nonvolatile memory cell, tie to diode structure but wherein increase the diffusion obstacle;

Figure 37 A and Figure 37 category-B are similar to Figure 10 A and Figure 10 B, carry out the rough schematic view that energy interband hot hole injects for the gated diode nonvolatile memory cell, tie to diode structure but wherein increase the diffusion obstacle;

Figure 38 A and Figure 38 category-B are similar to Figure 11 A and Figure 11 B, carry out the rough schematic view of energy interband sensing for the gated diode nonvolatile memory cell, it has the clean positive charge or the net negative charge of different total amounts, but characterization charge storing structure, tie to diode structure but wherein increase the diffusion obstacle, its diode node arrangement is different from Figure 37 A and Figure 37 B simultaneously;

Figure 39 A and Figure 39 B figure are similar to Figure 12 A and Figure 12 B, rough schematic view for neighboring gates diode non-volatile memory cell, connect Section Point in it is represented respectively and has and do not have the interior structure that connects Section Point, tie to diode structure but wherein increase the diffusion obstacle;

Figure 40 A and Figure 40 category-B are similar to Figure 17 A and Figure 17 B, be neighboring gates diode non-volatile memory cell, on discrete cell, carry out the rough schematic view that electrons tunnel is injected, do not connect Section Point in it does not have, tie to diode structure but increase the diffusion obstacle;

Figure 41 A, Figure 41 B and Figure 41 C are similar to Figure 18 A, Figure 18 B, Figure 18 C, be neighboring gates diode non-volatile memory cell, on discrete cell, carry out the rough schematic view that energy interband hot hole injects, connect Section Point in wherein neighboring gates diode non-volatile memory cell does not have;

Figure 42 A and Figure 42 category-B are similar to Figure 22 A and Figure 22 B, are neighboring gates diode non-volatile memory cell, carry out the rough schematic view of energy interband sensing on discrete cell, connect Section Point in it does not have, and tie to diode structure but increase the diffusion obstacle;

Figure 43 A and Figure 43 B mix with the diode structure that does not have diffusion obstacle knot and arrange relatively having diffusion obstacle knot;

Figure 44 A and Figure 44 B relatively have diffusion obstacle knot and the diode structure that does not have diffusion obstacle knot, the doping arrangement under different heat budget conditions.

Embodiment

Fig. 1 is the rough schematic view of gated diode nonvolatile memory cell, and

node

102 and 104 is separated to form diode by knot.Combination 106 essence of charge storing structure and dielectric structure are around first node 102.Charge storing structure and dielectric structure combination 106 also part are connected to the second diode node 104.In this profile, the dielectric layer 110 on the second diode node, 104 both sides completely cuts off the second diode node 104 and apparatus adjacent, for example other gated diode nonvolatile memory cell.

Figure 25 is the simplification gated diode nonvolatile memory cell that is similar to Fig. 1, but wherein increases diffusion obstacle knot 2501 to diode structure.

Fig. 2 A, Fig. 2 B, Fig. 2 C are the rough schematic view of gated diode nonvolatile memory cell, and it shows the charge storing structure that adopts different materials.Among Fig. 2 A, charge-trapping material structure 202 regional store charges, it is stored in positive charge near the charge-trapping material of diode junction.Oxidation structure is between charge-trapping material structure 202 and grid structure, simultaneously between charge-trapping material structure 202 and diode structure.The representative material of the dielectric material between charge-trapping material structure 202 and the grid structure comprises silicon dioxide and silicon oxynitride, and its thickness is about the 5-10 nanometer, maybe can adopt other similar high dielectric constant material, for example Al ₂O ₃The representative species of dielectric material comprises silicon dioxide and silicon oxynitride between charge-trapping material structure 202 and diode structure, and its thickness is about the 2-10 nanometer, also can adopt other similar high dielectric constant material.

The representative species of charge storing structure comprises silicon nitride, and its thickness is about the 3-9 nanometer, also can adopt other similar high dielectric constant material, comprises Al ₂O ₃, HfO ₂Deng metal oxide.

Among some embodiment, grid comprises a kind of material, and its work function is greater than the inside work function of N type silicon, or greater than 4.1eV, greater than 4.25eV, or comprises example greater than 5eV in the preferred embodiment.Representational grid material comprises the metal and the material of p type polysilicon, TiN, Pt and other high work function.Other material with relative high work function also can be used as the embodiment of present technique, include but not limited to Ru, Ir, Ni, with metal such as Co, also include but not limited to Ru-Ti, Ni-Ti, metal nitride, RuO ₂, with material such as metal oxide.Compared to the typical n type polysilicon bar utmost point, the grid material of high work function can produce higher injection barrier to electrons tunnel.Have the n type polysilicon bar utmost point of silicon dioxide top medium layer, its injection barrier is about 3.15eV.Therefore, grid that embodiments of the invention adopted and top medium material, its injection barrier all is higher than 3.15eV, and preferred embodiment is higher than 3.4eV, is higher than 4eV in the more preferred embodiment.Have the p type polysilicon bar utmost point of silicon dioxide top medium layer, its injection barrier is about 4.25eV, simultaneously, with respect to the n type polysilicon bar utmost point with silicon dioxide top medium layer, its about 2V that threshold voltage of assembling the unit can be descended.

Fig. 2 B shows the gated diode nonvolatile memory cell of similar Fig. 2 A, but has floating grid 204, and it is made by polysilicon usually.Fig. 2 C shows the gated diode nonvolatile memory cell of similar Fig. 2 A, but has nano particle charge storing structure 206.

Each charge storing structure all can store one or more, for example, if each charge storing structure all stores two, then can form four discontinuous charge storage states in the gated diode nonvolatile memory cell.

In certain embodiments, programming is meant makes how clean positive charge in the charge-trapping structure, for example can be by removing electronics in the charge storing structure or increasing the hole; On the other hand, wipe then to represent and in the charge-trapping structure, make more net negative charges, for example by increasing electronics in the charge storing structure or removing the hole.Yet in certain embodiments, programming is meant the net negative charge that increases in the charge storing structure, and wiping to represent increases clean positive charge in charge storing structure.This step can adopt multiple electric charge mobile mechanism, for example wears tunnel between valence band, comprises that hot carrier is injected, electric field causes and wears tunnel (E-field induced tunneling) and directly wear tunnel by substrate.

Figure 26 A, Figure 26 B, Figure 26 C are similar to the gated diode nonvolatile memory cell shown in the simplified schematic structure of Fig. 2 A, Fig. 2 B, Fig. 2 C, show the multiple charge storing structure that utilizes different materials, but increase diffusion obstacle knot in diode structure.

Fig. 3 A, Fig. 3 B, Fig. 3 C and Fig. 3 D are the rough schematic view of gated diode nonvolatile memory cell, and it shows the various embodiments of diode structure, for example pn diode and Schottky diode.In Fig. 3 A and Fig. 3 B, diode structure is the pn diode.Among Fig. 3 A, the first node 302 that is surrounded by the combination of charge storing structure and dielectric structure is doped to the p type in fact, and 314 of Section Points are doped to the n type.Among Fig. 3 C and Fig. 3 D, diode structure is a Schottky diode.Among Fig. 3 C, the first node 302 that is surrounded by the combination of charge storing structure and dielectric structure is a metal material in fact, and Section Point 324 is a semi-conducting material.The gated diode nonvolatile memory cell of Fig. 3 D is exchanged the gusset material among Fig. 3 C, and therefore the first node 332 that is surrounded by the combination of charge storing structure and dielectric structure in fact is a semi-conducting material, and Section Point 334 then is a metal material.

Figure 27 A, Figure 27 B, Figure 27 C and Figure 27 D are similar to the gated diode nonvolatile memory cell that Fig. 3 A, Fig. 3 B, Fig. 3 C and Fig. 3 D show, wherein show multiple diode structure embodiment, for example pn and polar body and Schottky diode, but wherein increase diffusion obstacle knot 2701 to diode structure.

Fig. 4 A, Fig. 4 B are the rough schematic view of gated diode nonvolatile memory cell, and it has the embodiment of homojunction for the pn diode.Among Fig. 4 A, the first node 402 of diode structure is silicon with the material of Section Point 404.Among Fig. 4 B, the first node 412 of diode structure is germanium with the material of Section Point 414.Because compared to silicon, being with of germanium is less, compared to Fig. 4 A, the gated diode nonvolatile memory cell of Fig. 4 B can produce bigger energy interband electric current.No matter adopt which kind of material in the homojunction diode structure, diode structure all can be monocrystalline or polycrystalline.Polycrystalline design can form higher density of memory cells, because of its deposit multilayer memory cell in vertical direction.

Figure 28 A and Figure 28 category-B are similar to the gated diode nonvolatile memory cell simplified structure of Fig. 4 A and Fig. 4 B, and its demonstration has the pn diode embodiment of homojunction, but add diffusion obstacle knot 2801 in diode structure in addition.

Fig. 5 shows the rough schematic view of gated diode nonvolatile memory cell, wherein shows the pn diode embodiment with heterojunction.As material, and the material of Section Point 504 is a silicon with germanium for the first node that surrounded by the combination of charge storing structure and dielectric structure in fact 502.First node 502 is to tie (gradedtransition layer junction) 506 with the conversion layer of gradient to link with Section Point 504.

Figure 29 is similar to the gated diode nonvolatile memory cell rough schematic view of Fig. 5, and its demonstration has the pn diode embodiment of heterojunction, but wherein increases diffusion obstacle knot 2901 to diode structure.

Fig. 6 A and Fig. 6 B carry out the rough schematic view that electrons tunnel is injected for the gated diode nonvolatile memory cell.Among Fig. 6 A, electrons tunnel is injected mechanism electronics is moved to charge storing structure 606 by the grid structure 608 of bias voltage-10V.The first diode node imposes the 10V bias voltage or floats, and the second diode node 604 imposes the 10V bias voltage.Among Fig. 6 B, electrons tunnel is injected mechanism electronics is moved to charge storing structure 606 by bias voltage-10V or the first unsteady diode node 602.Grid structure 608 imposes the 10V bias voltage, and the second diode node 604 imposes-the 10V bias voltage.

Figure 33 A and Figure 33 category-B are similar to Fig. 6 A and Fig. 6 B, and it is that the gated diode nonvolatile memory cell is carried out the rough schematic view that electrons tunnel is injected, but wherein increase diffusion obstacle knot 3301 to diode structure.

Fig. 7 A and Fig. 7 B carry out the schematic diagram that energy interband hot electron injects for the gated diode nonvolatile memory cell.Among Fig. 7 A, can the injection of interband hot electron electronics be moved to charge storing structure 606 by diode structure.The bias voltage of the n type first diode node 602 is 0V, and the bias voltage of grid structure 608 is 10V, the p+ type Section Point 604 of the hole inflow-5V bias voltage that electron hole pair causes.Among Fig. 7 B, can the injection of interband hot electron electronics be moved to charge storing structure 606 by diode structure.The bias voltage of the n type second diode node 604 is 0V, and the bias voltage of grid structure 608 is 10V, the p+ type first node 602 of the hole inflow-5V bias voltage that electron hole pair causes.

Figure 34 A and Figure 34 category-B are similar to Fig. 7 A and Fig. 7 B, for the gated diode nonvolatile memory cell is carried out the schematic diagram that energy interband hot electron injects, but wherein increase diffusion obstacle knot 3401 to diode structure.

Fig. 8 A and Fig. 8 B carry out the hole for the gated diode nonvolatile memory cell and wear the rough schematic view that tunnel injects.Among Fig. 8 A, tunnel is worn in the hole, and to inject mechanism be that the grid structure 608 of 10V moves to charge storing structure 606 with the hole by bias voltage.The bias voltage of the first diode node is-10V or unsteady that the bias voltage of the second diode node 604 is-10V.Among Fig. 8 B, the hole is worn tunnel and is injected mechanism the hole is moved to charge storing structure 606 by bias voltage for-10V or the first unsteady diode node 602.The bias voltage of grid structure 608 is-10V that the bias voltage of the second diode node 604 is 10V.

Figure 35 A and Figure 35 category-B are similar to Fig. 8 A and Fig. 8 B, carry out the hole for the gated diode nonvolatile memory cell and wear the schematic diagram that tunnel injects, but wherein increase diffusion obstacle knot 3501 to diode structure.

Fig. 9 A and Fig. 9 B carry out the schematic diagram that energy interband hot hole injects for the gated diode nonvolatile memory cell.Among Fig. 9 A, can the injection of interband hot hole the hole be moved to charge storing structure 606 by diode structure.The bias voltage of the p type first diode node 602 is 0V, and the bias voltage of grid structure 608 is 10V, and the electronics in the electron hole that is produced flows into the N+ type Section Point 604 of 5V bias voltage.Among Fig. 9 B, can the injection of interband hot hole electronics be moved to charge storing structure 606 by diode structure.The bias voltage of the p type second diode node 604 is 0V, and the bias voltage of grid structure 608 is-10V that the hole in the electron hole that is produced flows into the n+ type first node 602 of 5V bias voltage.

Flow through diode structure can interband electric current, can utilize vertical electric field to combine with lateral electric fields, determine the change of charge storage state in the charge storing structure very accurately.Bigger vertical and lateral electric fields can cause electric current between stronger valence band.The bias voltage setting puts on a plurality of ends, can make band curvature thus, makes it be enough to cause energy interband electric current enough in the diode structure, but can keep enough low potential differences between the diode node simultaneously, in case the action that produces programming or wipe.

According to the bias voltage setting of an embodiment of the present invention, diode structure is subjected to reverse biased.In addition, the added voltage of grid structure enables band and changes, and being enough to cause in diode structure can the interband tunneling effect.Node in the diode structure has high-dopant concentration, and it can (space charge region) cause high charge density in the space charge region, and the short and small space charge region of causing when utilizing voltage to change, and causes and can be with acutely change.Electronics in the valence band is worn tunnel by the one side of diode structure knot and is crossed and forbid band, enters the conduction band of another side, gos deep in the N type diode structure point along barrier potential (potential hill) drift downwards simultaneously.Similarly, the hole by n type diode structure node away from, upwards drift to barrier potential, shift to p type diode structure node.

The voltage of grid structure utilizes the dielectric structure between diode structure and charge storing structure, the voltage of control diode structure part.When the negative voltage of grid structure improved, the diode structure part negative voltage that this dielectric structure causes also improved simultaneously, causes band curvature more violent in the diode structure.Can increase by the interband electric current, cause (1) to change the electron energy level that can occupy at least with the quilt on the side, with the electron energy level that opposite side is not occupied, the two increase that overlaps; And (2) are by the barrier width attenuating (seeing Sze, Physics of Semiconductor Devices, 1981) between the electron energy level that occupied and the electron energy level that is not occupied.

Be stored in net negative charge or clean positive charge on the charge storing structure, more can influence the degree of band curvature.According to Gauss theorem, when applying negative voltage on the grid structure of diode structure, diode structure is subjected to than highfield in the part near charge storing structure, because of this part has more relatively net negative charge.Similarly, when applying positive voltage on the grid structure of diode structure, diode structure is subjected to than highfield in the part near charge storing structure, because of this part has higher relatively clean positive charge.

The different bias voltage settings of reading, programme and wiping show a kind of careful balance.When reading, the potential difference between the diode structure end should not cause a large amount of electric charge carriers to pass dielectric layer, arrives charge storing structure, and therefore influences charge storage state.On the other hand, with regard to wiping, the potential difference between the diode structure end must be enough to cause that the electric charge carrier of some passes through dielectric layer with regard to programming, and by the hot carrier injection of interband influencing charge storage state.

Figure 36 A and Figure 36 category-B are similar to Fig. 9 A and Fig. 9 B, for the gated diode nonvolatile memory cell is carried out the schematic diagram that energy interband hot hole injects, but wherein increase diffusion obstacle knot 3601 to diode structure.

Figure 10 A and Figure 10 B are grid diode non-volatile memory cells, utilize the clean positive charge and the net negative charge characterization charge storing structure of varying number, to carry out the rough schematic view of energy interband induction.Among Figure 10 A and Figure 10 B, can in diode structure, set up electron hole pair by the interband induction mechanism.The electronics of Shenging flows into the bias voltage N+ type first diode node 602 with 2V therefrom, and the hole then flows into the bias voltage p type second diode node 604 with 0V.The bias voltage of grid structure 608 is-10V.In Figure 10 A, charge storing structure 606 utilizes the diode junction between n+ type first diode node 602 and the p type second diode node 604, stores more relatively net negative charge.In Figure 10 B, charge storing structure 606 utilizes the diode junction between n+ type first diode node 602 and the p type second diode node 604, stores more relatively clean positive charge.Compared to Figure 10 B, the diode structure of Figure 10 A has bigger band curvature, and the energy interband induced current that flows into Figure 10 A simultaneously is also higher.

Figure 37 A and Figure 37 category-B are similar to Figure 10 A and Figure 10 B, be the gated diode nonvolatile memory cell, utilize the clean positive charge and the net negative charge characterization charge storing structure of varying number, carry out the schematic diagram of energy interband induction, but wherein increase diffusion obstacle knot 3701 to diode structure.

Figure 11 A and Figure 11 B are grid secondary body non-volatile memory cells, utilize the clean positive charge and the net negative charge characterization charge storing structure of varying number, with carry out can interband the rough schematic view of induction, but have different diode node arrangements with Figure 10 A and Figure 10 B.Especially, diode structure has p+ type first node 602, is surrounded by the combination institute essence of charge storing structure and dielectric structure, and Section Point 604 then is the n type.Can in diode structure, set up electron hole pair by the interband induction mechanism.The hole of Shenging therefrom flows into the bias voltage p+ type first diode node 602 with-2V, and electronics then flows into the bias voltage n type second diode node 604 with 0V.The bias voltage of grid structure 608 is 10V.In Figure 11 A, charge storing structure 606 utilizes the diode junction between p+ type first diode node 602 and the n type second diode node 604, stores more relatively net negative charge.In Figure 11 B, charge storing structure 606 utilizes the diode junction between p+ type first diode node 602 and the n type second diode node 604, stores more relatively clean positive charge.Compared to Figure 11 A, the diode structure of Figure 11 B has bigger band curvature, and the energy interband induced current that flows into Figure 11 B simultaneously is also higher.

In other embodiments, the Section Point doping content of diode structure is higher, and the first node doping content is lower, but first node is surrounded by the combination of Charge Storage and dielectric structure in fact.

Figure 38 A and Figure 38 category-B are similar to Figure 11 A and Figure 11 B, be the gated diode nonvolatile memory cell, utilize the clean positive charge and the net negative charge characterization charge storing structure of varying number, carry out the schematic diagram of energy interband induction, but wherein increase diffusion obstacle knot 3801 to diode structure, and have different diode node arrangements with Figure 37 A and Figure 37 B.

Figure 12 A and Figure 12 B are the rough schematic view of neighboring gates diode non-volatile memory cell, connect Section Point in showing respectively and do not have interior two kinds of situations that connect Section Point.Among Figure 12 A, neighboring gates diode non-volatile memory cell has

Section Point

1204 and 1205 respectively.The

Section Point

1204 and 1205 of neighboring gates diode non-volatile memory cell all extends and passes through oxide layer, and this oxide layer is separated the upper section of two

Section Points

1204 and 1205; Simultaneously, two nodes all are connected to common node structure 1214.The common node structure is for this two adjacent gated diode nonvolatile memory cell, and effect is promptly as corresponding lines.Among Figure 12 B,

Section Point

1204 and 1205 does not all extend the oxide layer of passing through branch next but two

node.Section Point

1204 and 1205 promptly is considered as other bit line of branch, and two same bit lines of the non-genus of node.

Figure 39 A and Figure 39 category-B are similar to Figure 12 A and Figure 12 B, it is a neighboring gates diode non-volatile memory cell, show respectively to connect Section Point in having and be not connected the structure of Section Point in the tool, but wherein increase

diffusion obstacle knot

3901,3902 to diode structure.

Figure 13 A and Figure 13 B are the rough schematic view of gated diode nonvolatile memory cell array, connect the Section Point stringer in it has, to carry out energy interband sensing.The first node stringer of diode structure is surrounded by charge storing structure and dielectric structure in fact, and it is the n type, and the Section Point stringer of diode structure is the p type.The adjacent Section Point stringer of diode structure is extended and is passed through the oxide of separating different Section Point stringer upper sections, is connected to the common bits line structure simultaneously.Among Figure 13 A, the first node stringer of diode structure is represented with bit line sign DL1 to DL6, and then by bit line sign CL representative, word line is then represented with word line sign WL1 to WL6 in the Section Point stringer.Among Figure 13 B, diode stringer and word line are applied voltage.The bias voltage of first node stringer DL3 is 2V, and the bias voltage of all the other first node stringers then is 0V.The bias voltage of Section Point stringer is 0V.The bias voltage of word line WL5 is-10V that the bias voltage of all the other word lines then is 0V.Energy interband sensing promptly carries out on the gated diode memory cell of word line WL5 and first node stringer DL3 infall thus.Pass through the electric current of first node stringer DL3 or Section Point stringer CL by measurement, can know the charge storage state of gated diode charge storing unit memory structure.

Figure 14 A and Figure 14 B for the gated diode nonvolatile memory cell array carry out can interband the rough schematic view of sensing, wherein the Section Point stringer does not have interior binding.Be connected bit line structure in being different from Figure 13 A and the Section Point stringer shown in Figure 13 B being common, the adjacent Section Point stringer of Figure 14 A and Figure 14 B diode structure is considered as other bit line.Among Figure 14 A, the Section Point stringer of diode structure has bit line sign CL1 to CL6.Among Figure 14 B, the second joint diode stringer and word line are applied voltage.The bias voltage of first node stringer DL3 is 2V, and all the other first node stringers then are 0V.The bias voltage of Section Point stringer is 0V.The bias voltage of word line WL5 is-10V that the bias voltage of all the other word lines is 0V.Can the interband sensing and can be in the gated diode memory cell infall of word line WL5 and first node stringer DL3/ Section Point stringer CL3 carry out.By the flow through electric current of first node stringer DL3 or Section Point stringer CL3 of measurement, can know in the gated diode memory cell charge storage state of charge storing structure.

Figure 15 A and Figure 15 B for the gated diode nonvolatile memory cell array carry out can interband the rough schematic view of sensing, wherein the Section Point stringer has interior binding, wherein the doping arrangement of diode structure is different from Figure 13 A, Figure 13 B, Figure 14 A and Figure 14 B.Among Figure 15 A and Figure 15 B, the first node stringer of diode structure is surrounded by charge storing structure and dielectric structure in fact, and it is the p type, and the Section Point stringer of diode structure is the n type.Be similar to Figure 13 A and Figure 13 B, the adjacent Section Point stringer of diode structure is extended and is passed through the oxide of separating different Section Point stringer upper sections, is connected to the common bits line structure simultaneously.Among Figure 15 A, the first node stringer of diode structure has bit line sign DL1 to DL6, and the Section Point stringer has bit line sign CL.Among Figure 15 B, diode stringer and word line are applied voltage.The bias voltage of first node stringer DL3 is-2V that all the other first node stringers then are 0V.The bias voltage of Section Point stringer is 0V.The bias voltage of word line WL5 is 10V, and the bias voltage of all the other word lines is 0V.Can the interband sensing and can be in the gated diode memory cell infall of word line WL5 and first node stringer DL3 carry out.By the flow through electric current of first node stringer DL3 or Section Point stringer CL of measurement, can know in the gated diode memory cell charge storage state of charge storing structure.

Figure 16 A and Figure 16 B for the gated diode nonvolatile memory cell array carry out can interband the rough schematic view of sensing, wherein the Section Point stringer has interior binding, wherein the doping arrangement of diode structure is different from Figure 13 A, Figure 13 B, Figure 14 A and Figure 14 B.Among Figure 15 A and Figure 15 B, the first node stringer of diode structure is surrounded by charge storing structure and dielectric structure in fact, and it is the p type, and the Section Point stringer of diode structure is the n type.Be similar to Figure 13 A and Figure 13 B, the adjacent Section Point stringer of diode structure is extended and is passed through the oxide of separating different Section Point stringer upper sections, is connected to the common bits line structure simultaneously.Among Figure 15 A, the first node stringer of diode structure has bit line sign DL1 to DL6, and the Section Point stringer has bit line sign CL.Among Figure 15 B, diode stringer and word line are applied voltage.The bias voltage of first node stringer DL3 is-2V that all the other first node stringers then are 0V.The bias voltage of Section Point stringer is 0V.The bias voltage of word line WL5 is 10V, and the bias voltage of all the other word lines is 0V.Can the interband sensing and can be in the gated diode memory cell infall of word line WL5 and first node stringer DL3 carry out.By the flow through electric current of first node stringer DL3 or Section Point stringer CL of measurement, can know in the gated diode memory cell charge storage state of charge storing structure.

The array of Figure 13 A to Figure 16 B has the embodiment that comprises diffusion obstacle knot and do not contain diffusion obstacle knot respectively.

Figure 17 A, Figure 17 B and Figure 17 C are neighboring gates diode non-volatile memory cell, and its Section Point does not link together, and carry out the rough schematic view as the injection of Fig. 6 A electrons tunnel, but only carry out on discrete cell.Among Figure 17 A, electrons tunnel is injected mechanism, and the grid structure 608 of electronics by utilization-10V bias voltage moved in charge storing structure 606 and 607.The first diode node 602 and 603 has bias voltage 10V or for floating, the second diode node 604 and 605 has bias voltage 10V.Among Figure 17 B, the first diode node 602 has bias voltage 10V or is to float, but 603 of the first diode nodes have bias voltage-10V.Among Figure 17 C, the first diode node 602 has bias voltage 10V or floats, and 603 bias voltage is 0V, and the second diode node 604 and 605 bias voltage then are respectively 10V and 0V.Electrons tunnel is injected mechanism optionally, electronics moved in the charge storing structure 606 by the grid structure 608 with-10V bias voltage, but non-moving to charge storing structure 607.In other embodiments, electrons tunnel is injected mechanism shown in Fig. 6 B, with electronics by the first diode node motion to charge storing structure, but occur over just on the discrete cell.Among other embodiment, the hole is worn tunnel and is injected mechanism shown in Fig. 8 A, the hole is moved in the charge storing structure by grid structure, but occur over just on the discrete cell.Among other embodiment, the hole is worn tunnel and is injected mechanism shown in Fig. 8 B, with the hole by the first diode node motion to charge storing structure, but occur over just on the discrete cell.

Figure 40 A and Figure 40 category-B are similar to Figure 17 A and Figure 17 B, for connecting the neighboring gates diode non-volatile memory cell of Section Point in the tool not, on discrete cell, carry out the schematic diagram that electrons tunnel is injected, but wherein increase diffusion obstacle knot 4001,4002 to diode structure.

Figure 18 A, Figure 18 B and Figure 18 C be for being connected the neighboring gates diode non-volatile memory cell of Section Point in the tool not, wherein take place on the discrete cell shown in Fig. 9 B can the injection of interband hot hole schematic diagram, but only on discrete cell, carry out.Among Figure 18 A, can interband hot hole inject mechanism the hole moved among the charge storing structure 606 by diode structure.P type second diode node 604 and 605 bias voltage are 0V, and the bias voltage of grid structure 608 is-10V, and the electronics that electron hole pair produced flows into the n+ type first node 602 and 603 by the 5V bias voltage.Among Figure 18 B, the bias voltage of first node 602 is 5V, but the bias voltage of first node 603 is 0V.Can interband hot hole injection mechanism optionally the hole be moved to charge storing structure 606 by diode structure, but it can not moved to charge storing structure 607.Figure 18 C also shows first node 602 and Section Point 604 formed diode structures, carry out the schematic diagram that energy interband hot hole injects, as being same as shown in Figure 18 B, the first diode node 603 and the second diode node, 605 formed diode structures then do not have this phenomenon yet.Yet among Figure 18 C, the first diode node 603 is subjected to the bias voltage of 5V, and the second diode node 605 is subjected to the 5V bias voltage.Because the first diode node 603 and the second diode node, 605 formed diode structures still do not have enough reverses biased, so can't take place in this diode structure and can inject mechanism by the interband hot hole.In other embodiments, can interband the hot hole implanter on discrete cell, optionally with the hole by diode structure with the p type first diode node and n+ type second diode node, move in the charge storing structure shown in Fig. 9 A.In other embodiments, can interband the hot hole implanter on discrete cell, optionally with electronics by diode structure with the p+ type first diode node and n type second diode node, move in the charge storing structure shown in Fig. 7 B.In other embodiments, can interband the hot electron implanter on discrete cell, optionally with electronics by diode structure with the n type first diode node and p+ type second diode node, move in the charge storing structure shown in Fig. 7 A.

Figure 41 A, Figure 41 B and Figure 41 C are similar to Figure 18 A, Figure 18 B and Figure 18 C, for connecting the neighboring gates diode non-volatile memory cell of Section Point in the tool not, on discrete cell, carry out the schematic diagram of energy interband sensing, but wherein increase

diffusion obstacle knot

4101,4102 to diode structure.

Figure 22 A is not connected Section Point neighboring gates diode non-volatile memory cell with Figure 22 B for tool is interior, wherein carries out the schematic diagram of the energy interband sensing shown in Figure 10 A and Figure 10 B on the discrete cell.Among Figure 22 A, can interband hot hole sensing mechanism set up electron hole pair in diode structure, this diode structure is formed with the second diode node 604 with 0V bias voltage by the n+ type first diode node 602 with 2V bias voltage.This energy interband current sensor is meant total positive charge or total negative electrical charge of characterization charge storing structure 606.The bias voltage of grid structure 608 is-10V.The bias voltage that forms the n+ type first diode node 603 of diode structure is 0V, and the p type second diode node 605 be 0V, with the energy interband current sensor of total charge dosage characterization charge storing structure 607, does not exist in default of enough anti-phase bias voltages.Figure 22 B shows the first diode node 602 and the second diode node 604 simultaneously, optionally on diode structure, produce the schematic diagram of energy interband current sensor, but this electric current results from the first diode node 602 and the second diode node, the 604 formed diode structures as Figure 22 A.Yet among Figure 22 B, the bias voltage of the first diode node 603 is 2V, and the bias voltage of the second diode node 605 is 2V.Owing to lack enough reverses biased between the first diode node 603 and the second diode node, the 605 formed diode structures, therefore can't produce can interband sensing mechanism.In other embodiments, can interband sensing mechanism shown in Figure 11 A and Figure 11 B, selectivity flows in p type first diode node and the n+ type second diode node in the formed diode structure.

Figure 42 A and Figure 42 category-B are similar to Figure 22 A and Figure 22 B, for connecting the neighboring gates diode non-volatile memory cell of Section Point in the tool not, on discrete cell, carry out the schematic diagram of energy interband sensing, but wherein increase

diffusion obstacle knot

4201,4202 to diode structure.

Figure 19 A, Figure 19 B and Figure 19 C are the decomposing schematic representation of gated diode nonvolatile memory cell poly array, between the wherein different arrays, have different word lines, first node stringer and the interior of Section Point stringer and are connected.Vertical arrangement between each array is promptly as Figure 16 A and Figure 16 B those shown.Vertical many arrays of separating though utilize insulation oxide 1904 all belong to the part of identical integrated circuit, but still show many arrays with is olation, show all word lines and bit line sign in the above-mentioned array.

Among Figure 19 A, different arrays 1900 have interior the connection with 1902.The word line of the word line of array 1900 and array 1902 is all with WL1 to WL6 mark.Yet the first node stringer of different arrays and Section Point stringer are independent separately.The first node stringer of array 1900 is marked as DL1 to DL6, and the first node stringer of array 1902 is marked as DL7 to DL12.The Section Point stringer of array 1900 is marked as CL1 to CL6, and the Section Point stringer of array 1902 is marked as CL7 to CL12.

Among Figure 19 B,

different arrays

1910 and 1912 are independent separately.The word line of array 1910 is labeled as WL1 to WL6, and the word line of array 1912 is labeled as WL7 to WL12.Yet different arrays 1910 have interior the connection with 1912 first node stringer with the Section Point stringer.Array 1910 all is labeled as DL1 to DL6 with first stringer of array 1912, and its second stringer all is labeled as CL1 to CL6.

Among Figure 19 C,

different arrays

1920 and 1922 word line and its first node stringer and Section Point stringer are all independent separately.The word line of array 1920 is labeled as WL1 to WL6, and the word line of array 1922 is labeled as WL7 to WL12.The first node stringer of array 1920 is labeled as DL1 to DL6, and the first node stringer of array 1922 is labeled as DL7 to DL12.The Section Point stringer of array 1920 is labeled as CL1 to CL6, and the Section Point stringer of array 1922 is labeled as CL7 to CL12.

In other embodiments, the Section Point stringer of many arrays has interior connection, and the specific array in many thus arrays can have the common bits line structure, and is used for the Section Point stringer of array, or supplies the usefulness of all arrays.In other embodiments, the first node stringer is the n type, and the Section Point stringer is the p type.The array of Figure 19 A, Figure 19 B and Figure 19 C shows the embodiment that has diffusion obstacle knot and do not have diffusion obstacle knot respectively.

Figure 20 shows the rough schematic view of integrated circuit, wherein has the array of gated diode nonvolatile memory cell and control circuit.Integrated circuit 2050 is included on the Semiconductor substrate, the storage array 2000 that utilizes the gated diode nonvolatile memory cell to finish.Gated diode memory cell array 2000 may be individual unit, interior connection array or the many arrays of interior connection.Column decoder 2001 and a plurality of word lines 2002, the line in storage array 2000 is coupled.Row decoder 2003 and a plurality of bit lines 2004, the file in storage array 2000 is coupled.The address offers row decoder 2003 and column decoder 2001 by bus 2005.Sensing amplifier in the square 2006 and data input structure are via data/address bus 2007 and row decoder 2003 couplings.Data are provided to Data In-Line 2011 by the input/output end port on the integrated circuit 2050, perhaps by the data source of other integrated circuit 2050 inner/outer, input to the data input structure in the square 2006.Data, are provided to integrated circuit 2050 via DOL Data Output Line 2015 by the sensing amplifier in the square 2006, or provide to other data terminal of integrated circuit 2050 inner/outer.Bias voltage is provided with the running that state machine 2009 control bias voltages are provided with supply voltage 2008, for example erase verification voltage and program verification voltage, and utilize all if can the interband electric current, arrange to programme, wipe and reading cells.The integrated circuit of Figure 20 comprises the embodiment that has diffusion obstacle knot and do not have diffusion obstacle knot.

Figure 21 A shows the making schematic flow sheet of the many arrays of gated diode nonvolatile memory cell to Figure 21 H.Figure 21 A shows on the silicon substrate 2102 to have oxide skin(coating) 2104, and the p type polysilicon layer 2112 on the oxide skin(coating) 2104.Among Figure 21 B, form sacrificial oxide layer 2116 and nitride 2118.Carry out then shallow trench isolation from, to form a plurality of p type polysilicon structures 2113.In Figure 21 C, sacrificial oxide layer 2116 and nitride 2118 are removed.These a plurality of p type polysilicon structures 2113 are carrying out the ion injection, form the p type Section Point 2114 and n+ type first node 2121 of gated diode nonvolatile memory cell.In Figure 21 D, form the combination 2123 and grid polycrystalline silicon 2132 of charge storing structure and dielectric structure, to finish first array of gated diode nonvolatile memory cell.Among Figure 21 E, form another layer oxide 2104 and another layer p type polysilicon 2112.Among Figure 21 F to Figure 21 H, be actually the step of repetition Figure 21 B,, it vertically be placed on the first previous array to form another gated diode nonvolatile array to Figure 21 D.

Figure 23 A shows the making flow process example of many arrays gated diode nonvolatile memory cell to Figure 23 H.Figure 23 A shows the substrate 10 with photoresist pattern 12, and its definable shallow trench is so that the adjacent elements insulation.Substrate can be p type or n type.Figure 23 B is presented on the substrate 10, and shallow trench 14 is subjected to etched situation between photoresist pattern 12.Photoresist pattern 12 is removed.Figure 23 C demonstration insulation oxide 16 is inserted shallow trench 14, with the situation of isolated adjacent elements.Figure 23 D shows that ion injects 18.Ion injects 18 and has different ions, can set up deep trap 8 in substrate 10, sets up shallow well 6 simultaneously in deep trap 8.For example, if substrate 10 is the p type, 8 of deep traps are the n type, and shallow well 6 is the p type; Comparatively speaking, if substrate 10 is the n type, 8 of deep traps are the p type, and shallow well 6 is the n type.Be to simplify the following drawings, the combination of above-mentioned deep trap, shallow well and substrate will no longer present, and be interpreted as element and can be formed in the trap or on the substrate.Figure 23 E shows the diffusion position lines 20 that utilize ion injection 18 to form equally between isolation oxide layer 16.Diffusion position line 20 forms with injection method, the charge type of its alloy and shallow well 6 opposite (or opposite with substrate 10).Figure 23 F shows the step of removing SI semi-insulation oxide 16.Utilize back and soak (dip back) or etchback step, part that can be removed insulation oxide 16 forms shallow-layer insulation oxide 22.The surface of shallow-layer insulation oxide 22 is lower than the pn knot between diffusion position line 20 and the shallow well 6.Figure 23 G shows the formation of oxidation-nitrogenize-thin oxide layer 30, wherein has upper strata oxide 24, nitride 26 and lower floor's oxide 28.In other embodiments, nitride structure is floating grid or nanocrystal.Because the surface of shallow-layer insulation oxide 22 is lower than the pn knot between diffusion position line 20 and the shallow well 6, so the voltage of oxidation-nitrogenize-thin oxide layer 30 control diffusion position lines 20 and 6 pn knots of trap.Figure 23 H shows that forming word line 32 thinks that element provides the step of grid voltage.Deposition n+ type or p type polysilicon membrane are subsequently with its etching, to form many word lines.Grid material can be metal gates simultaneously, for example silicide, Ry Ru, molybdenum and tungsten.

Figure 24 is the perspective view of gated diode nonvolatile memory cell array, and this graph structure is formed by the step of Figure 23 A to Figure 23 H.

Figure 30 A to Figure 30 F shows another making flow process example figure of gated diode nonvolatile memory cell array.

Figure 30 A shows p type substrate 10, deposition n type polysilicon 40 on it.Figure 30 B shows the n+ type polysilicon membrane 42 that is made thus, and it is positioned on the P type substrate 10.Figure 30 C shows the barrier layer that forms after a while, and it has one deck protection pad oxide 44 on n+ type polysilicon membrane 42, and one deck silicon nitride 46 is arranged on protection pad oxide 44.The photoresist layer 48 that is positioned on the silicon nitride 46 is parts of photoetching process, in order to form groove.Figure 30 D shows that the shallow-layer groove is formed on the substrate 10 via anisotropic etching.N+ type polysilicon membrane 42 is divided into the first diode node and the second diode node of separation by groove, and the two is a counterpart adjacent on the substrate 10.Similarly, protection pad oxide 44 is divided into several protection pad oxides 52, and silicon nitride 46 is divided into several silicon nitrides 54, and photoresist layer 48 is removed.Among Figure 30 E, insulation oxide 56 filling grooves, isolated simultaneously contiguous diode structure.Subsequently, the step of carrying out chemico-mechanical polishing and removing silicon nitride.Figure 30 F shows the step of removing the SI semi-insulation oxide, forms insulation oxide part 22 thus, in order to isolated adjacent diode structure.Remaining step then is similar to Figure 23 G and Figure 23 H.

Figure 31 A is to the making flow process example of Figure 31 I figure demonstration gated diode nonvolatile memory cell array, and wherein diode structure has diffusion obstacle knot.

Figure 31 A is similar to Figure 30 A to Figure 30 F to the making flow process of Figure 31 I, and Figure 23 G and Figure 23 H, but slightly different: form before the n+ type polysilicon membrane 42 on the p type substrate 10, can form ultrathin membrane 58 earlier on p type substrate 10.In various embodiments, ultrathin membrane 58 can be oxide, nitride, oxynitride, and its thickness is about 10-20 dust (Angstroms).After ultrathin membrane 58 was divided into different blocks, the block of separation became diffusion obstacle knot respectively, and it can reduce the alloy flow phenomenon of the first diode node and the second diode node among each diode structure.

Figure 32 is the perspective view of gated diode nonvolatile memory cell array, wherein have diffusion obstacle knot, and this structure is by the technology made of Figure 31 A to Figure 31 I.

Figure 43 A and Figure 43 B are relatively to have the different diode alloy data that diffusion obstacle knot and tool diffusion obstacle are not tied.

Figure 43 A shows in the diode structure with diffusion obstacle knot, the data and curves of dopant.Curve 4304 and 4306 is represented the doping data of P type dopant boron and n type alloy phosphorus respectively, and curve 4302 is represented the net doping data of curve 4304 and 4306.X-axis is unit with the micron, upright position on the expression diode structure, the intersection of the initial point representative diffusion obstacle knot and the second diode node, the forward numeral on the X-axis is big more, i.e. and the second diode node (increasing the degree that dielectric layer surrounds that is insulated simultaneously) is goed deep in expression more; And the negative sense numeral is big more on the X-axis, and then the first diode node (increasing simultaneously by the degree of charge storing structure and the encirclement of Charge Storage dielectric value) is goed deep in expression more.The first diode node is the n+ polysilicon, and doping content is about 10 ²⁰Cm ^-3

Figure 43 B demonstration is similar to the diode structure doping data of Figure 43 A, but does not wherein have diffusion obstacle knot.Curve 4310 and 4312 decibels of data of representing p type dopant boron and n type dopant phosphorus.Curve 4308 is represented the net doping data of curve 4304 and 4306.Relatively P type boron dopings of below form, n type phosphorus doping, and three kinds of concentration of net doping type, in the second diode node, the degree of depth of corresponding X-axis is X=0.1 μ m.Following table is represented to spread obstacle and is tied the situation that the n type alloy that can reduce in the first diode node moves to the second diode node.

	Figure 43 A has diffusion obstacle knot	Figure 43 B is tool diffusion obstacle knot not
	Figure 43 A has diffusion obstacle knot	Figure 43 B is tool diffusion obstacle knot not	P type boron (cm ^-3)	6.58×10 ¹⁷	6.42×10 ¹⁷
N type phosphorus (cm ^-3)	1.66×10 ¹⁷	1.47×10 ¹⁹	P type boron (cm ^-3)	6.58×10 ¹⁷	6.42×10 ¹⁷
N type phosphorus (cm ^-3)	1.66×10 ¹⁷	1.47×10 ¹⁹	The net doping type of the second diode node	The P type	The N type

Figure 43 A and Figure 43 B relatively have the different diode alloys that diffusion obstacle knot and tool diffusion obstacle are not tied, the data under different heat budgets (thermal budget) situation.Among Figure 44 A and Figure 44 B, the diffusion obstacle of diode structure knot thickness is 15 dusts.X-axis is identical with Figure 43 B with Figure 43 A basically.Among Figure 44 A, curve 4402 and curve 4404 are represented the doping data of p type dopant boron and n type dopant phosphorus respectively.Among Figure 44 B,

curve

4406 and 4408 is represented the doping data of p type dopant boron and n type dopant phosphorus respectively.The heat budget that Figure 44 A is corresponding relatively low utilizes ISSG (in situ steamgeneration) technology, handles 21 seconds at 900 ℃, again with HTO (high temperatureoxide) technology, handles 30 minutes at 900 ℃.Figure 44 B, handled 43.5 minutes for 1000 ℃ with another Technology for Heating Processing with 950 ℃ of heat treatments 10 minutes corresponding to higher relatively heat budget again.Although heat budget has suitable difference, and the corresponding doping data of Figure 43 A and Figure 43 B are still quite similar.

The preferred embodiments of the present invention and example are in detail open as above, should above-mentioned example only as example, non-in order to limit the scope of the invention.With regard to those skilled in the art, from can according to claims correlation technique being made amendment easily and make up.

Claims

1. make the method for non-volatile memory device in integrated circuit for one kind, this element comprises diode, and this diode has the first diode node and the second diode node, and this method comprises:

Form on the second layer of ground floor second charge type in this integrated circuit of first charge type in this integrated circuit, wherein this first charge type is opposite with this second charge type;

Remove the part of this ground floor and this second layer, in this ground floor, to form the first diode node and in this second layer, to form the second diode node, this first diode node of this first charge type is with respect to the second diode node of this second charge type, and this first diode node and this second diode node are separated by knot;

Form spacer medium district in this integrated circuit to isolate at least a portion and the adjacent elements of this second diode node, so this spacer medium district makes this knot not be capped;

Form charge storing structure and one or more storage medium structure in this integrated circuit, the part of whole and this second diode node that this charge storing structure and one or more storage medium structure cover this knot at least and be adjacent to this first diode node of this knot, these one or more storage medium structures to small part between this charge storing structure and this first and second diode node, and to small part between the gate-voltage source of this charge storing structure and this element; And

Form the grid of this gate-voltage source of supplying with this element.

2. the method for claim 1, wherein this charge storing structure has when reverse biased, by the charge storage state that current measurement determined of flowing through between this first diode node and this second diode node.

3. the method for claim 1 wherein forms this spacer medium district and comprises:

Utilize the spacer medium district to cover this knot at least; And

Remove the part of this knot of covering in this spacer medium district.

4. the method for claim 1, wherein this first diode node is a doped polycrystalline silicon.

5. the method for claim 1, wherein this second diode node is the well region in this integrated circuit.

6. the method for claim 1, wherein this second diode node is the substrate in this integrated circuit.

7. the method for claim 1, wherein this first diode node is the bit line of this element of access.

8. the method for claim 1, wherein this diode that is made of this first diode node and this second diode node is a Schottky diode.

9. the method for claim 1, wherein this diode that is made of this first diode node and this second diode node is the pn diode.

10. the method for claim 1, wherein this knot is a homojunction.

11. the method for claim 1, wherein this knot is a heterojunction.

12. the method for claim 1, wherein this knot is the gradient heterojunction.

13. the method for claim 1, wherein this knot comprises diffusion obstacle knot.

14. the method for claim 1, wherein this charge storing structure comprises the charge-trapping material.

15. the method for claim 1, wherein this charge storing structure comprises the floating grid material.

16. the method for claim 1, wherein this charge storing structure comprises nano crystal material.

17. the method for claim 1, wherein this first diode node and this second diode node are monocrystalline, polycrystalline or amorphous.

18. the non-volatile memory device in integrated circuit, this element comprises diode, and this diode has first node and Section Point, and the technology that this element utilization comprises the following step forms:

Form on the second layer of second charge type of ground floor in this integrated circuit of first charge type in this integrated circuit, wherein this first charge type is opposite with this second charge type;

Remove the part of this ground floor and this second layer, in this ground floor, to form first node and in this second layer, to form Section Point, this first node of this first charge type is with respect to the Section Point of this second charge type, and this first node and this Section Point are separated by knot;

Form at least a portion and the adjacent elements of spacer medium district to isolate this Section Point in this integrated circuit, so this spacer medium district makes this knot not be capped;

Form charge storing structure and one or more storage medium structure in this integrated circuit, the part of whole and this Section Point that this charge storing structure and one or more storage medium structure cover this knot at least and be adjacent to this first node of this knot, these one or more storage medium structures to small part between this charge storing structure and this first and second node, and to small part between the gate-voltage source of this charge storing structure and this element; And

Form the grid of this gate-voltage source of supplying with this element.

19. element as claimed in claim 18, wherein this charge storing structure has when reverse biased, by the charge storage state that current measurement determined of flowing through between this first node and this Section Point.

20. element as claimed in claim 18, wherein this knot comprises diffusion obstacle knot.

21. make the method for non-volatile storage element array in integrated circuit for one kind, each this element comprises diode, this diode has first node and Section Point, and this method comprises:

Remove the part of this ground floor and this second layer, in this ground floor, to form first node and in this second layer, to form Section Point, it is right to cause each this element to comprise the vicinity that this first node and this Section Point form, and this first node of each this element and this Section Point are separated by tying;

Form spacer medium in this integrated circuit capable with this Section Point of isolating each this element at least a portion and at least a portion of the Section Point of the element of the adjacent lines of this element, this knot of each this element is not covered by this spacer medium is capable;

Each this element is formed charge storing structure and one or more storage medium structure, the part of whole and this Section Point that this charge storing structure and one or more storage medium structure cover this knot at least and be adjacent to this first node of this knot, these one or more storage medium structures to small part between this charge storing structure and this first and second node, and to small part between the gate-voltage source of this charge storing structure and this element; And

22. method as claimed in claim 21, wherein this first node is a bit line, the specific non-volatile memory device in this bit line and this this non-volatile storage element array of word line access.

23. method as claimed in claim 21, wherein this charge storing structure of each this element has when reverse biased, by the current measurement of flowing through between this first node and this Section Point, the charge storage state that is determined.

24. method as claimed in claim 21, wherein this knot of each this element comprises diffusion obstacle knot.

25. the non-volatile storage element array in integrated circuit, each this element comprises diode, and this diode has first node and Section Point, and the technology that this array utilization comprises the following step forms:

Each this element is formed charge storing structure and one or more storage medium structure, the part of whole and this Section Point that this charge storing structure and one or more storage medium structure cover this knot at least and be adjacent to this first node of this knot, these one or more storage medium structures to small part between this charge storing structure and this first and second node, and to small part between a gate-voltage source of this charge storing structure and this element; And

26. array as claimed in claim 25, wherein this first node is a bit line, the specific non-volatile memory device in this bit line and this this non-volatile storage element array of word line access.

27. array as claimed in claim 25, wherein this charge storing structure of each this element has when reverse biased, by the current measurement of flowing through between this first node and this Section Point, the charge storage state that is determined.

28. array as claimed in claim 25, wherein this knot of each this element comprises diffusion obstacle knot.