CN101587890A - Static discharge protective structure and layout method thereof - Google Patents
Static discharge protective structure and layout method thereof Download PDFInfo
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- CN101587890A CN101587890A CNA2008101125070A CN200810112507A CN101587890A CN 101587890 A CN101587890 A CN 101587890A CN A2008101125070 A CNA2008101125070 A CN A2008101125070A CN 200810112507 A CN200810112507 A CN 200810112507A CN 101587890 A CN101587890 A CN 101587890A
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Abstract
The invention relates to a static discharge protective structure and a layout method thereof. The static discharge protective structure comprises a semiconductor substrate, a substrate contact in the substrate, a grid on the semiconductor substrate, a first lightly doped region and a second lightly doped region which are arranged on two sides of the grid in the semiconductor substrate, a first heavily doped region in the first lightly doped region, and at least one second heavily doped region and one third heavily doped region in the second heavily doped region; the second heavily doped region and the third heavily doped region are arranged at intervals; the grid, the substrate and the first heavily doped region are connected with an earthed end; and the first lightly doped region, the second lightly doped region, the second heavily doped region and the substrate form a parasitic controlled silicon rectifier.
Description
Technical field
The present invention relates to ESD-protection structure and layout method thereof.
Background technology
Nowadays, along with the improvement of integrated circuit fabrication process, make that the characteristic size of CMOS integrated circuit is also more and more littler.Yet, the thing followed, electrostatic discharge (ESD) protection in the sheet (ESD, ElectrostaticDischarge) device for the protective capacities of static discharge also more and more a little less than, i.e. more and more littler along with device size, the electrostatic potential that circuit can bear is also more and more littler.And, owing to the static in the residing operational environment of integrated circuit can't have any change because of dwindling of integrated circuit size, therefore, compare, adopt now that the integrated circuit of deep sub-micron fabrication manufacturing is easier to be subjected to the influence of static discharge and to damage with the large scale integrated circuit.
At first meet with the weld pad that being generally of static discharge directly be coupled to integrated circuit (IC) chip or the input/output circuitry of terminal in the integrated circuit package.Thereby ESD protection circuit also links to each other with input/output circuitry usually.At present; in high tension apparatus technology; the normal ESD-protection structure that adopts as shown in Figure 1; the one electrostatic discharge (ESD) protection pipe that links to each other with imput output circuit (figure does not show) is provided; the grid 4 of described electrostatic discharge (ESD) protection pipe, source electrode 3 link to each other with substrate 1 and ground connection, 2 join with input/output circuitry and drain.When imput output circuit met with static discharge, drain electrode that just can be by described electrostatic discharge (ESD) protection pipe 2 guided to earth terminal with static discharge current, thereby avoided integrated circuit to be subjected to static discharge and damage.
Yet the protective characteristic of described ESD-protection structure is relatively poor, is difficult to satisfy specification requirement usually; if will satisfy specification requirement; then certainly will to increase the size of described electrostatic discharge (ESD) protection pipe, thereby will increase the area of integrated circuit, also will make power consumption of integrated circuit increase.
Summary of the invention
The problem that the present invention solves is the relatively poor problem of protective characteristic of prior art grid ESD-protection structure.
For addressing the above problem, the present invention also provides a kind of ESD-protection structure, comprising:
Substrate contact in Semiconductor substrate and the substrate; Grid on the Semiconductor substrate; In the Semiconductor substrate, be positioned at first light doping section and second light doping section of grid both sides; First heavily doped region in first light doping section; At least each one second heavily doped region and the 3rd heavily doped region in second light doping section, described second heavily doped region and the 3rd heavily doped region are spaced, described grid, substrate and first heavily doped region are connected in earth terminal, described second heavily doped region, the 3rd heavily doped region link to each other, described first light doping section, second light doping section, described second heavily doped region and substrate constitute parasitic silicon controlled rectifier (SCR, SiliconControlled Rectifier).
Optionally, described second heavily doped region, the 3rd heavily doped region are spaced along described grid width direction respectively.
Correspondingly, the invention provides a kind of layout method of ESD-protection structure, comprising:
First layout graph of arrangement representing substrate contact; In a side of described first layout graph, second layout graph of arrangement representing light doping section; The 3rd layout graph of arrangement representing grid on described second layout graph, described the 3rd layout graph is divided into two parts with second layout graph, represents first light doping section and second light doping section respectively; In the 3rd layout graph one side, represent on the second layout graph zone of first light doping section the 4th layout graph of arrangement representing first heavily doped region; At the 3rd layout graph opposite side, represent on the second layout graph zone of second light doping section, at interval the 5th layout graph of arrangement representing second heavily doped region and the 6th layout graph of representing the 3rd heavily doped region; Described first layout graph, the 3rd layout graph and the 4th layout graph are linked to each other, described the 5th layout graph links to each other with the 6th layout graph, and described the 5th layout graph, second layout graph and first layout graph constitute the layout graph of the parasitic silicon controlled rectifier of representative.
Optionally, described the 5th layout graph and the 6th layout graph are spaced along the grid width direction of the 3rd layout graph representative.
Compared with prior art; above-mentioned disclosed ESD-protection structure and layout method thereof have the following advantages: described ESD-protection structure and layout method thereof are by forming two kinds of dissimilar heavily doped regions in the light doping section of metal-oxide-semiconductor grid one side; and be spaced; thereby described wherein one type heavily doped region and substrate constitute parasitic thyristor; because thyristor has bigger current margin, therefore has electrostatic discharge protective characteristic preferably.
And; the possibility of described ESD-protection structure and layout method thereof; make described second heavily doped region, the 3rd heavily doped region be spaced, thereby form the multichannel current path, improved the electric current uniformity of described ESD-protection structure along described grid width direction.
Description of drawings
Fig. 1 is a prior art ESD-protection structure schematic diagram;
Fig. 2 is a kind of execution mode schematic diagram of ESD-protection structure of the present invention;
Fig. 3 is a kind of execution mode schematic diagram of the layout method of ESD-protection structure of the present invention;
Fig. 4 a is a kind of embodiment schematic diagram of layout method shown in Figure 3;
Fig. 4 b is the another kind of embodiment schematic diagram of layout method shown in Figure 3.
Embodiment
ESD-protection structure disclosed in this invention and layout method thereof are by forming two kinds of dissimilar heavily doped regions in the light doping section of metal-oxide-semiconductor grid one side; and be spaced, thereby described wherein one type heavily doped region and substrate constitute parasitic thyristor.
With reference to shown in Figure 2, a kind of execution mode of ESD-protection structure of the present invention comprises:
Described substrate 10 can form the substrate contact by quadruple doped region 50.
Further, described second heavily doped region 20 ', the 3rd heavily doped region 20 " is spaced along described grid 40 Widths respectively.
Make that below by description above-mentioned ESD-protection structure is clearer to the embodiment of an ESD-protection structure.
Continue with reference to shown in Figure 2, the substrate 10 of described electro-static discharge structure is a P type substrate, generally obtains by doping P type ion; Grid 40 normal employing polycrystalline silicon materials on the described substrate 10 prepare and get; In the described substrate 10, first light doping section 30 and second light doping section 20 that are positioned at grid 40 both sides are N type light doping section NDD, generally inject and obtain by substrate 10 being carried out N type ion.Described method is summarized as follows: define in substrate 10 and will carry out the zone that ion injects, then ion is carried out in described zone and inject, N type ion adopts arsenic, phosphorus etc. usually.First heavily doped region 30 in described first light doping section 30 ' be N type heavily doped region N+, the formation method of heavily doped region is similar to the formation method of light doping section, and difference only is the concentration that ion injects.Second heavily doped region 20 in second light doping section 20 ' be P type heavily doped region P+, described P type heavily doped region P+ adopts the method for for example boron ion injection to form usually, and described the 3rd heavily doped region 20 " is N type heavily doped region N+.Described second heavily doped region 20 ' " be spaced with the 3rd heavily doped region 20.Described two N type light doping section NDD and P type substrate constitute parasitic NPN pipe, and described P type heavily doped region P+, N type light doping section NDD and P type substrate constitute parasitic PNP pipe, and described horizontal NPN pipe and longitudinal P NP pipe constitute parasitic silicon controlled rectifier Q.In addition, described quadruple doped region 50 is the heavy doping of P type, as the substrate contact of P type substrate.Generally between described P type substrate contact 50 and first light doping section 30 isolate by field oxide region (sign), described field oxide region generally adopt shallow trench isolation from method form.
Described substrate contact 50, first heavily doped region 30 ' and grid 40 be connected in earth terminal, and second heavily doped region 20 ' and the 3rd heavily doped region 20 " link to each other, and the input/output circuitry of common and for example integrated circuit (IC) chip or link to each other.Because the substrate 10 of P type and second light doping section 20 of N type are low doping concentration, thereby the PN between P type substrate and N type light doping section connects face higher puncture voltage is arranged, when not having the static discharge situation, described PN connects face can conducting, thereby described parasitic silicon controlled rectifier can conducting yet.
When the negative voltage static discharge takes place when; PN between P type substrate and N type light doping section connects the face forward conduction; since second light doping section 20 by second heavily doped region 20 ' and the 3rd heavily doped region 20 " link to each other with input/output circuitry; substrate 10 contacts 50 by substrate and links to each other with earth terminal; make input/output circuitry and earth terminal short circuit; thus described static discharge discharges to earth terminal, has protected integrated circuit (IC) chip.And when the positive voltage static discharge takes place; parasitic silicon controlled rectifier conducting; static discharge by second heavily doped region 20 ' and the 3rd heavily doped region 20 ", second light doping section 20, substrate 10 and first light doping section 30 discharge to earth terminal, protected integrated circuit (IC) chip.Because thyristor has bigger current margin, can tolerate the static discharge that voltage is higher, therefore has electrostatic discharge protective characteristic preferably.
Continue with reference to shown in Figure 2, for second heavily doped region 20 in second light doping section 20 ' and the 3rd heavily doped region 20 " also have the structure of more optimizing; promptly second heavily doped region 20 that forms in second light doping section 20 ' " be spaced along described grid 40 Widths respectively, promptly the conducting channel direction along 20 of first light doping section 30 and second light doping sections is spaced with the 3rd heavily doped region 20.As can see from Figure 2, second heavily doped region 20 in second light doping section 20 ' and the 3rd heavily doped region 20 " distribution be exactly the 3rd heavily doped region 20 ", second heavily doped region 20 ' and the 3rd heavily doped region 20 " such structure that is spaced.And, grid 40 among Fig. 2 and grid 40 ' also can be considered in fact the part of grid pole in the many grid structures of grid fractionation back formation, the size that is limited to accompanying drawing, complete structure is not illustrated, but those skilled in the art should be able to also release complete structure according to described content at an easy rate in conjunction with the accompanying drawings.Described many grids all link to each other, for example grid 40 and grid 40 ' link to each other.Such distributed architecture will make described electro-static discharge structure can form the multichannel current path when the conducting electric current, thereby improve electric current uniformity.
With reference to shown in Figure 3, a kind of execution mode of the layout method of ESD-protection structure of the present invention comprises:
Step s1, first layout graph of arrangement representing substrate contact;
Step s2, in a side of described first layout graph, second layout graph of arrangement representing light doping section;
Step s3, the 3rd layout graph of arrangement representing grid on described second layout graph, described the 3rd layout graph is divided into two parts with second layout graph, represents first light doping section and second light doping section respectively;
Step s4 in the 3rd layout graph one side, represents on the second layout graph zone of first light doping section the 4th layout graph of arrangement representing first heavily doped region;
Step s5 at the 3rd layout graph opposite side, represents on the second layout graph zone of second light doping section, at interval the 5th layout graph of arrangement representing second heavily doped region and the 6th layout graph of representing the 3rd heavily doped region;
Step s6, described first layout graph, the 3rd layout graph and the 4th layout graph are linked to each other, described the 5th layout graph links to each other with the 6th layout graph, and described the 5th layout graph, second layout graph and first layout graph constitute the layout graph of the parasitic silicon controlled rectifier of representative.
Below by concrete example above-mentioned layout method is described in further detail.
In conjunction with Fig. 4 a and shown in Figure 2, execution in step s1, at first first layout graph 100 of arrangement representing substrate contact 50.After the manufacturing process of substrate contact 50 just can in substrate 10, define substrate and contacted 50 shape according to the mask of making by described first layout graph 100.
Then, continue in conjunction with Fig. 4 a and shown in Figure 2, execution in step s2, in a side of described first layout graph 100, second layout graph 200 of arrangement representing light doping section.With reference to above-mentioned description to described electro-static discharge structure, because described first light doping section 30 is identical with the doping type of second light doping section 20, thereby available second layout graph 200 defines the scope of first light doping section 30 and second light doping section 20.
And in order to divide first light doping section 30 and second light doping section 20, execution in step s3 then, continuation is in conjunction with Fig. 4 a and shown in Figure 2, the 3rd layout graph 300 of arrangement representing grid 40 on described second layout graph 100, described the 3rd layout graph 300 is divided into two parts with second layout graph 100, represents first light doping section 30 and second light doping section 20 respectively.In this example, suppose that the subregion of second layout graph 200 between first layout graph 100 and the 3rd layout graph 300 represents first light doping section 30, and second light doping section 20 is not represented in the subregion of remaining second layout graph that is covered by the 3rd layout graph 300.After the light doping section and the manufacturing process of grid just can in substrate 10, define the shape of first light doping section 30 and second light doping section 20 and grid 40 according to the mask of making by described the 3rd layout graph 100 and second layout graph 200.
Continuation is in conjunction with Fig. 4 a and shown in Figure 2, and execution in step s4 in the 3rd layout graph 300 1 sides, represents on second layout graph, 200 zones of first light doping section 30, arrangement representing first heavily doped region 30 ' the 4th layout graph 400.After first heavily doped region 30 ' manufacturing process just can according to the mask of making by described the 4th layout graph 400 come in first light doping section 30, to define first heavily doped region 30 ' shape.
Continuation is in conjunction with Fig. 4 a and shown in Figure 2, execution in step s5, at the 3rd layout graph 300 opposite sides, represent on second layout graph, 200 zones of second light doping section 20, at interval arrangement representing second heavily doped region 20 ' the 5th layout graph 500 and represent the 3rd heavily doped region 20 " the 6th layout graph 600.Described the 5th layout graph 500 and the 6th layout graph 600 along with the 3rd layout graph 300 across being spaced on the vertical direction of the direction of second layout graph 200, described the 5th layout graph 500 is parallel with Fig. 4 a place paper with the 6th layout graph 600 spaced directions.From described the 3rd layout graph 300, on described second layout graph 200, be furnished with the 6th layout graph 600 and the 5th layout graph 500 successively.After second heavily doped region 20 ' and the 3rd heavily doped region 20 " manufacturing process just can according to the mask of making by described the 5th layout graph 500 and the 6th layout graph 600 come in second light doping section 20, to define second heavily doped region 20 ' with the 3rd heavily doped region 20 " shape.
Continuation is in conjunction with Fig. 4 a and shown in Figure 2, and execution in step s6 links to each other described first layout graph 100, the 3rd layout graph 300 (figure does not show) with the 4th layout graph 400, and described the 5th layout graph 500 links to each other with the 6th layout graph 600 (figure does not show).After manufacturing process in, the mask of the layout graph processing procedure of finishing according to step s6, just can define with described substrate contact 50, first heavily doped region 30 ' and grid 40 be connected in the line groove of earth terminal, and with second heavily doped region 20 ' with the 3rd heavily doped region 20 " the line groove that links to each other.And with reference to above-mentioned description to ESD-protection structure as can be known; described first light doping section 30, second light doping section 20, second heavily doped region 20 ' and substrate 10 constitute parasitic silicon controlled rectifier, thereby described the 5th layout graph 500, second layout graph 200 and first layout graph 100 also can be understood as the layout graph that constitutes the parasitic silicon controlled rectifier of representative.
Fig. 4 b provides the another kind of embodiment of the layout method of electro-static discharge structure of the present invention.Layout method in layout method in this example and the above-mentioned example is basic identical, the difference part be to represent second heavily doped region 20 ' the 5th layout graph 500 ' and represent the 3rd heavily doped region 20 " the 6th layout graph 600 ' layout on.Continuation is with reference to shown in Fig. 4 b, described the 5th layout graph 500 ' and the 6th layout graph 600 ' along the 3rd layout graph 300 ' across second layout graph 200 ' direction be spaced, promptly be furnished with successively the 5th layout graph 500 ', the 6th layout graph 600 ', the 5th layout graph 500 ', the 6th layout graph 600 '.。。Described the 5th layout graph 500 ' parallel with Fig. 4 b place paper with the 6th layout graph 600 ' spaced direction.According to second heavily doped region of making 20 of this kind the 5th layout graph 500 and the 6th layout graph 600 ' and the 3rd heavily doped region 20 "; can be as shown in Figure 2, be successively the 3rd heavily doped region 20 ", second heavily doped region 20 ' and the 3rd heavily doped region 20 " such be spaced structure.In addition, the a plurality of sub-layout graphs of described the 3rd layout graph 300 ' also may be split into (figure does not show), described sub-layout graph all along the 3rd layout graph 300 ' across second layout graph 200 ' direction be across second layout graph 200 ' on, and parallel to each other, described each sub-layout graph all links to each other.
In sum; described ESD-protection structure and layout method thereof are by forming two kinds of dissimilar heavily doped regions in the light doping section of metal-oxide-semiconductor grid one side; and be spaced; thereby described wherein one type heavily doped region and substrate constitute parasitic thyristor; because thyristor has bigger current margin, therefore has electrostatic discharge protective characteristic preferably.
And; the possibility of described ESD-protection structure and layout method thereof; make described second heavily doped region, the 3rd heavily doped region be spaced, thereby form the multichannel current path, improved the electric current uniformity of described ESD-protection structure along described grid width direction.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (8)
1. an ESD-protection structure is characterized in that, comprising: the substrate contact in Semiconductor substrate and the substrate; Grid on the Semiconductor substrate; In the Semiconductor substrate, be positioned at first light doping section and second light doping section of grid both sides; First heavily doped region in first light doping section; At least each one second heavily doped region and the 3rd heavily doped region in second light doping section, described second heavily doped region and the 3rd heavily doped region are spaced, described grid, substrate and first heavily doped region are connected in earth terminal, and described first light doping section, second light doping section, described second heavily doped region and substrate constitute parasitic silicon controlled rectifier.
2. ESD-protection structure as claimed in claim 1 is characterized in that, described second heavily doped region, the 3rd heavily doped region are spaced along described grid width direction respectively.
3. ESD-protection structure as claimed in claim 1 is characterized in that, described substrate contact adopts heavily doped method to form.
4. ESD-protection structure as claimed in claim 1 is characterized in that, described grid is many grid structures.
5. the layout method of an ESD-protection structure is characterized in that, comprising: first layout graph of arrangement representing substrate contact; In a side of described first layout graph, second layout graph of arrangement representing light doping section; The 3rd layout graph of arrangement representing grid on described second layout graph, described the 3rd layout graph is divided into two parts with second layout graph, represents first light doping section and second light doping section respectively; In the 3rd layout graph one side, represent on the second layout graph zone of first light doping section the 4th layout graph of arrangement representing first heavily doped region; At the 3rd layout graph opposite side, represent on the second layout graph zone of second light doping section, at interval the 5th layout graph of arrangement representing second heavily doped region and the 6th layout graph of representing the 3rd heavily doped region; Described first layout graph, the 3rd layout graph and the 4th layout graph are linked to each other, described the 5th layout graph links to each other with the 6th layout graph, and described the 5th layout graph, second layout graph and first layout graph constitute the layout graph of the parasitic silicon controlled rectifier of representative.
6. the layout method of ESD-protection structure as claimed in claim 5 is characterized in that, described the 5th layout graph and the 6th layout graph along with the 3rd layout graph across being spaced on the vertical direction of the direction of second layout graph.
7. the layout method of ESD-protection structure as claimed in claim 5 is characterized in that, described the 5th layout graph and the 6th layout graph are along being spaced on the direction of the 3rd layout graph across second layout graph.
8. the layout method of ESD-protection structure as claimed in claim 5 is characterized in that, described the 3rd layout graph comprises a plurality of sub-layout graphs, and described a plurality of sub-layout graphs all link to each other.
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| CN2008101125070A CN101587890B (en) | 2008-05-23 | 2008-05-23 | Layout method of static discharge protective structure |
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| CN2008101125070A CN101587890B (en) | 2008-05-23 | 2008-05-23 | Layout method of static discharge protective structure |
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| CN101587890A true CN101587890A (en) | 2009-11-25 |
| CN101587890B CN101587890B (en) | 2011-05-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116613107A (en) * | 2023-07-21 | 2023-08-18 | 粤芯半导体技术股份有限公司 | Preparation method for improving electrostatic protection structure and structure thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5754380A (en) * | 1995-04-06 | 1998-05-19 | Industrial Technology Research Institute | CMOS output buffer with enhanced high ESD protection capability |
| US5572394A (en) * | 1995-04-06 | 1996-11-05 | Industrial Technology Research Institute | CMOS on-chip four-LVTSCR ESD protection scheme |
| US6365940B1 (en) * | 1999-12-21 | 2002-04-02 | Texas Instruments Incorporated | High voltage trigger remote-cathode SCR |
| US6323074B1 (en) * | 2000-04-24 | 2001-11-27 | Taiwan Semiconductor Manufacturing Company | High voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drain |
| CN1649142A (en) * | 2004-01-19 | 2005-08-03 | 财团法人工业技术研究院 | Static discharging protectire circuit and static discharging protective method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116613107A (en) * | 2023-07-21 | 2023-08-18 | 粤芯半导体技术股份有限公司 | Preparation method for improving electrostatic protection structure and structure thereof |
| CN116613107B (en) * | 2023-07-21 | 2024-01-26 | 粤芯半导体技术股份有限公司 | Preparation method for improving electrostatic protection structure and structure thereof |
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