CN101583047B - System and method for generating reset signal - Google Patents
System and method for generating reset signal Download PDFInfo
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- CN101583047B CN101583047B CN2008100990839A CN200810099083A CN101583047B CN 101583047 B CN101583047 B CN 101583047B CN 2008100990839 A CN2008100990839 A CN 2008100990839A CN 200810099083 A CN200810099083 A CN 200810099083A CN 101583047 B CN101583047 B CN 101583047B
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Abstract
The invention discloses a system and a method for generating a reset signal so as to be convenient for synchronization for example. In one embodiment, the system for generating a reset signal comprises a deviation generator which provides a deviation clock signal with input clock signal frequency deviation. The deviation generator responds to regular phase deviation between the deviation clock signal and an input clock signal, and a reset generator generates the reset signal.
Description
Technical field
The present invention relates generally to be used to generate system and method such as the reset signal that can be used for synchronizing signal and output.
Background technology
In the circuit of many types, wish stable, detection or synchronous given signal and equipment or reference signal.Some technology have been developed with stable signal or the detection signal that is generated when having noise.For instance, can implement to carry out this function such as phase-locked loop close-loop feedback control systems such as (PLL).Usually, the signal of the frequency of PLL generation and output and input or reference signal and phase association.The PLL circuit can improve or reduce the frequency of Coherent Oscillator so automatically in response to the frequency and the phase place of input signal, all mates on frequency and phase place up to output signal and reference signal.In radio, telecommunications, computer and other electronic application, use the PLL circuit widely.
Give one example again, in many communications applications, can use oscilloscope or other display device to generate eyes patterns (being also referred to as eye pattern).According to repeated sampling and be applied to vertical output generate the eyes pattern from the digital data signal of receiver (or other data source), use data rate to trigger horizontal sweep simultaneously.Be called the eyes pattern and receive, because for the coding of some types, this pattern looks like a series of eyes between a pair of path.
Summary of the invention
The present invention relates generally to that a kind of generation for example is used to make the system and method for the synchronous scan reset signal of demonstration and input clock signal.Generation has the offset clocks with respect to the frequency of the given frequency skew of input clock signal.In response to the regular displacement that detects between offset clocks signal and input clock signal, generate reset signal.For example, displacement regularly can be corresponding to the predetermined portions or the integral multiple in input clock signal cycle.This method can be used has the register (for example d type flip flop) of input clock signal conduct by the input of offset clocks timing, detects the regular displacement between clock signal.Can use the reset signal that generated to trigger to be used on related display lockup period to hope the resetting of scanning maker of eyes pattern.
One aspect of the present invention provides a kind of system that generates reset signal, comprises the skew maker, and it provides the offset clocks signal that has frequency shift (FS) with respect to the frequency of input clock signal.In response to the regular phase deviation that detects between offset clocks signal and input clock signal, the maker that resets generates reset signal.
Another aspect of the present invention provides a kind of system that is used for synchronous input signal and equipment.This system comprises and is used to provide the device of offset clocks signal that has the frequency shift (FS) of scheduled volume with respect to first clock signal that described first recovering clock signals is from input signal.This system also comprises the device that is used for generating in response to detect the phase deviation that repeats between the offset clocks signal and first clock signal reset signal.This system also comprises the device that is used for providing according to reset signal the sweep ramp signal, and this sweep ramp signal is used to the expression of synchronous input signal.
Another aspect of the present invention provides a kind of method of synchronous digital input signal to show that be used on equipment.This method comprises from digital input signals recovers first clock signal, and generation has the offset clocks signal that the frequency shift (FS) of scheduled volume is arranged with respect to the frequency of first clock signal.In response to detecting the phase deviation that between the offset clocks signal and first clock signal, repeats, generate reset signal.Generate synchronizing signal according to this reset signal, thereby the expression of synchronous first clock signal is to show on equipment.
Description of drawings
Fig. 1 diagram being used to according to an aspect of the present invention generates the block diagram of the system of sweep ramp signal.
Fig. 2 is the schematic block diagram of system that is used to generate scan reset according to an aspect of the present invention.
Fig. 3 diagram is used for the timing diagram of the intrasystem signal of Fig. 2.
Fig. 4 illustrates the block diagram of the measuring system of implementing system according to one aspect of the invention.
Fig. 5 diagram example that can generate and lock onto the eye pattern of display according to an aspect of the present invention.
Another example of Fig. 6 diagram eye pattern that can generate and lock onto display according to an aspect of the present invention.
Fig. 7 be illustrate according to an aspect of the present invention be used to generate the flow chart that is used to lock input and the method for the ramp signal of display.
Embodiment
The present invention relates generally to generate the system and method for the scan reset signal that can be used for synchronization indicator and clock signal.In a kind of example embodiment, generated frequency has the offset clocks with respect to the predetermined frequency offset of input clock signal.In response to the regular phase deviation that detects between offset clocks signal and input clock signal, generate reset signal.Can use resetting of this reset signal driver sweep maker, for example be used for the eyes pattern that lockup period is hoped on related display.As described here, can implement these system and methods effectively, and the complicated circuit such as phase-locked loop etc. that need in multiple existing system, will not need.
As the skilled person will appreciate, at the flow chart description of this reference method, system and computer program some embodiment of the present invention.Can realize illustrated square frame and the combination of square frame in the accompanying drawings by computer executable instructions with understanding.One or more processors that these computer executable instructions can be offered all-purpose computer, special-purpose computer or other programmable data processing device (or combination of equipment and circuit) are to generate machine, so that the instruction of carrying out by processor is implemented in the function of stipulating in one or more square frames.
These computer executable instructions also can be stored in the computer-readable memory, its can instruct computer or other programming data treatment facility move with ad hoc fashion comprise manufacturing a product of the instruction that is implemented in the function of stipulating in one or more flowchart block so that produce in the instruction of this computer-readable memory stored.Also computer program instructions can be loaded into the sequence of operations step to cause carrying out on computer or other programmable data processing device with on computer or other programmable device, thereby generate computer and carry out processing, so that the instruction of carrying out on computer or other programmable device is provided for being implemented in the step of the function of stipulating in one or more flowchart block.
Fig. 1 diagram being used to generate and resetting and the example of the system 10 of ramp signal according to an aspect of the present invention.System 10 comprises skew maker 12, and it is configured to generate offset clocks signal (OFFSET_CLK) according to input clock signal (INPUT_CLK).This INPUT_CLK signal can be corresponding to from video input data signal recovered clock signal.OFFSET_CLK and INPUT_CLK can be provided as respectively between high and low state with frequency and duty ratio oscillatory signal (for example have the square wave of 50% duty ratio or other).One skilled in the art will understand and appreciate that and to recover the INPUT_CLK signal from the digital input signals of number of different types.For instance, therefrom recovering the digital input signals of INPUT_CLK signal can be corresponding to digital video signal (for example INPUT_CLK signal can corresponding to the part digital video signal).Can be according to routine or professional format arbitrarily, known or will develop (for example Digital Visual Interface (DVI), serial digital interface (SDI) (for example single-definition SDI (SD-SDI), high definition SDI (HD-SDI), two strands meet HD-SDI) etc.) provides digital video signal.
Skew maker 12 is configured to provide OFFSET_CLK signal on the frequency with respect to INPUT_CLK signal bias scheduled volume.Side-play amount between relative frequency can be the non-integral multiple any value as input clock signal.For instance, can be in scope for providing OFFSET_CLK signal to non-integral multiple frequency near the INPUT_CLK signal of twice from the only about half of of input clock signal frequency.This scope can be continuous or discrete number range with the sampling that the INPUT_CLK signal indication is provided or the expected range of sub sampling.Concrete offset value can change according to application requirements.It will be appreciated by those skilled in the art that can be with various types of circuit with acting on the device that the offset clocks signal is provided.
The maker 14 that resets can comprise the scanning edge and the interior consistent logical circuit 16 of corresponding transformation of INPUT_CLK signal that operatively detects the OFFSET_CLK signal.Logical circuit 16 can also be configured to the production burst in response to detecting state-transition.Logical circuit 16 can comprise and for example is provided for detecting the transformation in the INPUT_CLK signal and is used to provide pulse signal as the trigger of RESET signal and the configuration of one or more gates.It will be appreciated by those skilled in the art that and various types of logics and other circuit (for example analog-and digital-circuit) can be embodied as the maker 14 that resets to be provided for generating the device of RESET signal.
The maker 14 that resets can offer the RESET signal scanning maker 18.Scanning maker 18 can generate sweep ramp output signal (RAMP) again, for example can be corresponding to the X coordinate of graphic alphanumeric display.For example, can pass through analog to digital converter (not shown), generate corresponding Y coordinate by the digital input signals that will therefrom recover the INPUT_CLK signal.Can be along with the time offers display (for example passing through image processor) is used for digital input signals with demonstration corresponding eye pattern with a series of X and Y coordinates.For example, scanning maker 18 can be embodied as the free-running operation clock, it is counted on the number range that increases progressively in response to the OFFSET_CLK signal.In response to the RESET signal, scanning maker 18 can regularly reset to initial value, so that can use the RAMP signal that is provided by scanning maker 18 that digital input signals is locked onto display.
Skew maker 12 can be programmed to realize the skew expected, for example based on the PROGRAM input signal.For instance, when being used to generate eye pattern, the user can be provided with a plurality of eyes that will show on related display.Can use eyes quantity that the correspondent frequency deviant is set, the RAMP signal (for example corresponding to the X coordinate) that generates with toilet will scan the clock cycle by the respective numbers that is used for input clock signal.Change as the function of the skew of the relative frequency between INPUT_CLK signal and OFFSET_CLK signal in the quantity of X coordinate between the reset cycle.The duration representative that appears at the phase deviation regularly continuously between input clock signal and the offset clocks signal comprises the sampling interval of the predetermined quantity clock cycle of INPUT_CLK signal.Can with should the sampling interval as the parameter of the frequency of the OFFSET_CLK that is provided in eye pattern as a result, providing the desired amt eyes.
The example of Fig. 2 diagram system 50 that can realize by the logical circuit that is used to generate the RESET signal according to an aspect of the present invention.This system 50 comprises first logical circuit, for example may be embodied as trigger 52 (for example d type flip flop), is used to catch the state-transition with consistent basically first clock signal in offset clocks signal edge.In clock (or enabling) input of trigger 52, provide OFFSET_CLK signal.As described here, provide the OFFSET_CLK signal that has with respect to the predetermined frequency offset of INPUT_CLK signal.The data input of INPUT_CLK signal as trigger 52 is provided.Therefore, the state of INPUT_CLK signal will be hunted down and provide in its Q output according to the OFFSET_CLK signal that provides is provided at clock.The Q output of trigger 52 is corresponding to clock crossbar signal (CLK_CROSSING).For instance, d type flip flop 52 can be embodied as the edge and trigger the trigger of (for example rising edge or trailing edge) or the trigger of level triggers, be used to be captured in the INPUT_CLK signal that provides in its D input.How catching sampling can change according to the type of employed trigger 52.
For instance, the Q of trigger 52 output is corresponding in response to the rising edge (or trailing edge) of clock skew signal and the convert signals of change state consistent basically with state-transition in the INPUT_CLK signal.Just, when the rising edge (or trailing edge) of OFFSET_CLK in a clock signal with first state alignment of INPUT_CLK, subsequently in next signal with inverse state at once, the CLK_CROSSING signal will correspondingly change its state.Therefore this CLK_CROSSING signal can represent each detected state-transition consistent with the OFFSET_CLK edges of signals.The CLK_CROSSING signal will remain in this state, up to catching another state-transition by trigger 52.
Also OFFSET_CLK is offered impulse generator 54, be used for generating the RESET signal in response on the CLK_CROSSING signal, detecting given transformation.In the example of Fig. 2, impulse generator 54 comprises trigger 56 and the Digital Logic 58 that is set to generate the RESET signal.Trigger 56 is received in the OFFSET_CLK in the clock input and the Q output of the trigger 52 in its data input.In the example of Fig. 2, this logic is embodied as and door 60, although it will be appreciated by those skilled in the art that the logic that to implement other type and configuration according to system's needs.The Q of trigger 56 is exported the paraphase input that offers with door 60.The output (CLK_CROSSING signal) of first trigger 52 is offered another input with door 60.With door 60 thereby to the reverse output and the CLK_CROSSING signal of trigger 56 carry out " with " to generate the RESET signal as pulse.One skilled in the art will understand and appreciate that and other circuit can be used to generate corresponding pulses.For example, can use other edge to generate the RESET signal, and can use different circuit that different pulse durations is provided.
Fig. 3 is the timing diagram that is used for from the signal of the system 50 of Fig. 2.In Fig. 3, diagram OFFSET_CLK has slightly the frequency that is lower than (for example the clock cycle of OFFSET_CLK signal is slightly higher than) INPUT_CLK signal.Therefore, the scanning of the rising edge of OFFSET_CLK signal is by the INPUT_CLK signal, the INPUT_CLK signal is carried out son scanning.In the example of Fig. 3, the rising edge with OFFSET_CLK signal of the frequency that is lower than the INPUT_CLK signal seems to scan the signal by INPUT_CLK to the right from the left side of INPUT_CLK signal.Alternately, the OFFSET_CLK signal can have the frequency that is higher than the INPUT_CLK signal, so as this scanning may appear in the example with Fig. 3 illustrated side in the opposite direction in.
As shown in Figure 3, consistent basically with INPUT_CLK signal state-transition from low to high in response to the rising edge of OFFSET_CLK signal, the CLK_CROSSING signal uprised on the time that T1 represents.Also the RESET signal is provided as pulse from T1 to T2 to be identified in the regular phase deviation of the detection between INPUT_CLK signal and the OFFSET_CLK signal.The CLK_CROSSING signal remains high up to time T 3, and wherein the rising edge of OFFSET_CLK is consistent basically with the transformation from high to low of INPUT_CLK signal.Obviously on T3, do not apply the RESET signal, because the impulse generator 54 in Fig. 2 is configured in response to the rising edge of OFFSET_CLK and generation RESET signal consistent basically with the transformation from low to high of INPUT_CLK signal.One skilled in the art will understand and appreciate that and to dispose the pulse that generated with production burst in being different from described herein situation.
Fig. 4 diagram for example can realize the example in the measuring system 100 of the skew maker of this diagram and description and scanning control system.Measuring system 100 comprises clock recovery circuitry 102, and its receiver, video input signal for example has digital video signal known or will development format.Clock recovery circuitry 102 provides the corresponding clock signal of recovering from the video input (CLK).This clock signal clk is offered skew maker and scanning control system 104.Skew maker and scanning control system 104 for example can be corresponding to the systems 10 with reference to figure 1 diagram and description.
As described here, the offset clocks that has with respect to the predetermined frequency offset of the clock signal that is provided by clock recovery circuitry 102 can be provided for skew maker and scanning control system 104.In response to the regular phase deviation that detects between CLK signal and OFFSET_CLK signal, for example described herein, can generate reset signal.Skew maker and scanning control system 104 can generate the regular RAMP signal that offers bus 106 again.Bus 106 can be implemented as the electrical connection, base plate or the norator system that are configured in measuring system 100, transmit data and/or power.One skilled in the art will understand and appreciate that various bus structures, base plate, the point-to-point that can be used to provide bus 106 connect and related protocol.
Video input signals can also be offered modulus (A/D) transducer 108 that can be configured to be used for input signal is converted to respective digital DATA signal.Therefore transducer 108 can offer the DATA signal bus 106.By example, the RAMP signal can be corresponding to the X coordinate of graphic alphanumeric display, and the DATA signal can be corresponding to the Y coordinate.Therefore can on bus 106, send DATA and RAMP signal to display processing system 110.For example, can on bus 106, synchronously provide each DATA and RAMP signal according to the OFFSET_CLK signal.
The eye pattern 150 that Fig. 5 and Fig. 6 diagram can generate on related display 118 and two examples of 160.In the example of Fig. 5, eye pattern 150 comprises according to the RAMP signal that is generated by skew maker and scanning control system 104 with from the DATA semaphore lock of A/D converter 108 three eyes to display.In Fig. 6, eye pattern 160 comprises according to the reset signal that is provided by skew maker and scanning control system 104 (Fig. 4) and corresponding RAMP semaphore lock ten eyes to display.One skilled in the art will understand and appreciate that can be according to the eyes that other quantity for example is provided by the suitable instruction of user interface 106 inputs.
In view of said structure and functional character, will understand some method better with reference to figure 7.To understand and appreciate that illustrated in other embodiments action can occur or occur simultaneously with other action with different order.And, may not need illustrated all features of Fig. 7 to implement the method according to this invention.Also will understand and to use hardware (for example in logical circuit, in one or more processors or controller, for example in computer customized configuration testing apparatus), software (for example be stored in the computer-readable medium or as the executable instruction of on one or more processors, moving) or implement following method as the combination of hardware and software.
Fig. 7 is the flow chart that can be used to generate the RAMP signal and the example of the method that shows eye pattern that illustrates according to an aspect of the present invention.This method starts from 202, wherein the recovered clock signal.For example can import (for example receiving) recovered clock signal from numeral from digital video data source.204, generate the OFFSET_CLK signal.Can generate the OFFSET_CLK signal that has with respect in the predetermined frequency offset of the frequency of 202 place recovered clock signal.This frequency offset is programmable, so that be provided for showing the parameter of predetermined quantity eyes in eye pattern.
206, determine whether to detect regular phase deviation.If do not detect regular phase deviation (denying) as yet, then this method is in 206 cocycles.With this circulation while, the RAMP signal can be according to increasing progressively rising at the 204 OFFSET_CLK signals that generate.If detected regular phase deviation (being), then this method advances to 208.208, in response to detecting regular phase deviation, this sweep signal resets.As described here, for example, can detect regular phase deviation in response to the state-transition consistent basically (for example may on the prearranged multiple in input clock signal cycle, repeat) in the predefine edge of OFFSET_CLK signal and the institute recovered clock signal.
210, show eye pattern.The demonstration of eye pattern will change according to RAMP sweep signal that is generated and the input signal (for example digital video signal) that offers analog to digital converter.Just, RAMP can be corresponding to the X coordinate, and the output of analog to digital converter can be corresponding to the Y coordinate of display.Because according to the sweep signal that resets termly of the regular phase deviation between OFFSET_CLK signal and institute's recovered clock signal, the eye pattern coordinate can be offered display and in fixing basically direction, lock onto display.By this way, eye pattern seems to be static for the beholder, so that can carry out suitable analysis (for example jitter analysis or other test) to input signal.
Claims (10)
1. system that generates reset signal comprises:
The skew maker provides the offset clocks signal that has with respect to the frequency shift (FS) of input clock signal frequency; With
The maker that resets in response to the regular phase deviation that detects between offset clocks signal and input clock signal, generates reset signal.
2. the system of claim 1 also comprises the scanning maker, and the sweep ramp signal that increases progressively and regularly reset in response to reset signal according to the offset clocks signal is provided.
3. the system of claim 2, also comprise analog to digital converter, convert digital input signals to the respective digital data-signal, the x coordinate that shows of this sweep ramp signal definition two-dimensional figure wherein, the y coordinate that digital data signal definition two-dimensional figure shows, described sweep ramp signal are used to the digital data signal on two-dimensional figure shows synchronously.
4. the system of claim 3, wherein this digital input signals comprises the digital video signal that therefrom recovers input clock signal, this two-dimensional figure shows corresponding to eye pattern.
5. the system of claim 1, wherein in response to along with the scanning of offset clocks edges of signals by input clock signal, described edge is consistent basically with the state-transition of input clock signal, the maker that resets repeatedly detects regular phase deviation.
6. the system of claim 1, wherein the quantity in the input clock signal cycle that occurs between a pair of adjacent regular phase deviation changes as the function of the frequency shift (FS) between offset clocks signal and input clock signal.
7. the system of claim 6, wherein frequency shift (FS) is the mark of input clock signal or non-integral multiple.
8. the system of claim 6 is wherein with only about half of in the scope of about twice in the input clock signal frequency of the frequency configuration of offset clocks signal.
9. the system of claim 1, the duration that wherein occurs between each the regular phase deviation between input clock signal and offset clocks signal representative comprises sampling interval of input clock signal of the predetermined quantity clock cycle of input clock signal.
10. the system of claim 1, the maker that wherein resets also comprises at least one trigger, described at least one trigger is by the timing of offset clocks signal, is used to be captured in the state of the input clock signal in the output of at least one trigger,
The maker that wherein resets also comprises the logic of the reset signal that is configured to generate the pulse that detects predetermined transition in response in the output at least one trigger and occur.
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| US5789954A (en) * | 1995-10-25 | 1998-08-04 | Hewlett-Packard Co. | Phase dither of an acquisition clock using a delay lock loop |
| US7061281B2 (en) * | 2004-06-15 | 2006-06-13 | Mediatek Inc. | Methods and devices for obtaining sampling clocks |
| CN101087278A (en) * | 2006-06-05 | 2007-12-12 | 中兴通讯股份有限公司 | A signal estimation method for layered demodulation of multi-input and multi-output system |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4537515A (en) * | 1981-12-17 | 1985-08-27 | Asulab S.A. | Resonator temperature compensated time base and watch using said time base |
| US5789954A (en) * | 1995-10-25 | 1998-08-04 | Hewlett-Packard Co. | Phase dither of an acquisition clock using a delay lock loop |
| US7061281B2 (en) * | 2004-06-15 | 2006-06-13 | Mediatek Inc. | Methods and devices for obtaining sampling clocks |
| CN101087278A (en) * | 2006-06-05 | 2007-12-12 | 中兴通讯股份有限公司 | A signal estimation method for layered demodulation of multi-input and multi-output system |
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