CN101572224B - Method for smoothening doped polysilicon and method for preparing polysilicon floating gate - Google Patents
Method for smoothening doped polysilicon and method for preparing polysilicon floating gate Download PDFInfo
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- CN101572224B CN101572224B CN200810105616XA CN200810105616A CN101572224B CN 101572224 B CN101572224 B CN 101572224B CN 200810105616X A CN200810105616X A CN 200810105616XA CN 200810105616 A CN200810105616 A CN 200810105616A CN 101572224 B CN101572224 B CN 101572224B
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Abstract
The invention relates to a method for smoothening doped polysilicon and a method for preparing polysilicon floating gate. The method for smoothening the doped polysilicon comprises the following steps: providing eigen polysilicon, performing chemico-mechanical polishing, and doping the polysilicon, wherein the dosage concentration of the polysilicon is more than 5.0E+20cm<-2>. The polysilicon prepared by the method has high surface smoothness.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly the manufacture method of a kind of manufacture method of multi-crystal silicon floating bar and semiconductor device.
Background technology
In the manufacture craft of semiconductor device, the chemico-mechanical polishing of polysilicon is a relatively more crucial technology, for example after forming polysilicon plug and polysilicon dual-damascene structure structure, and form after the multi-crystal silicon floating bar of flash memory, all to carry out the CMP (Chemical Mechanical Polishing) process of polysilicon, to form smooth polysilicon surface structure, described polysilicon all is the doped polycrystalline silicon of having carried out N type or the injection of P type ion.
In the prior art, the processing step that doped polycrystalline silicon is carried out chemico-mechanical polishing shown in 1, comprising with reference to the accompanying drawings: step S10, polysilicon is mixed, and step S11 carries out chemico-mechanical polishing to polysilicon.Generally, those skilled in the art thinks and directly doped polycrystalline silicon is carried out chemico-mechanical polishing, can not exert an influence to glossing, can the surface property of the polysilicon after the polishing not exerted an influence yet, for example at document investigations in polysilicon CMP to apply in sub-quartermicron DRAM device, IEEE (The Institute of Electrical and ElectronicsEngineers), description in 1999, the 214-214 pages or leaves.
Along with the manufacture craft of semiconductor device is constantly progressive, the critical dimension of flash memory is more and more littler, and is therefore, also more and more higher to the technology accuracy requirement of each step manufacture craft.In the manufacture craft of flash memory, can adopt multi-crystal silicon floating bar, usually all be on gate oxide, to adopt chemical vapor deposition method directly to form doped polycrystalline silicon, then doped polycrystalline silicon is carried out chemico-mechanical polishing, form multi-crystal silicon floating bar, the doping content of described multi-crystal silicon floating bar is generally 1.0E20cm
-2～5.0E21cm
-2
The surface smoothness of multi-crystal silicon floating bar has directly determined the electrical property quality of the flash memory that forms, and researcher of the present invention finds, when the doping content of doped polycrystalline silicon more than or equal to 5.0E+20cm
-2The time, carry out chemico-mechanical polishing after, the surfacing of the multi-crystal silicon floating bar of formation can not have been satisfied the application need of device.
Summary of the invention
In view of this, the technical problem that the present invention solves provides a kind of flattening method of doped polycrystalline silicon, adopts CMP (Chemical Mechanical Polishing) process and forms the higher doped polycrystalline silicon face of evenness.
The present invention also provides a kind of manufacture method of multi-crystal silicon floating bar, forms the doped polycrystalline silicon floating gate than high-flatness.
The present invention also provides a kind of manufacture method of semiconductor device, and described semiconductor device contains the multi-crystal silicon floating bar of high-dopant concentration, high-flatness.
A kind of flattening method of doped polycrystalline silicon comprises: the polysilicon that eigenstate is provided; Polysilicon to eigenstate carries out chemico-mechanical polishing; Eigenstate polysilicon after the polishing is mixed.
Preferably, the doping content of polysilicon is more than or equal to 5.0E+20cm
-2Be more preferably, the doping content of polysilicon is more than or equal to 5.0E+20cm
-2Smaller or equal to 5.0E+21cm
-2
Preferably, described dopant ion is the P ion.
A kind of manufacture method of multi-crystal silicon floating bar, comprise: Semiconductor substrate is provided, be formed with in the described Semiconductor substrate and be used to isolate the active region isolation structure, the surface of isolation structure is higher than Semiconductor substrate, on described Semiconductor substrate and isolation structure, form gate oxide and intrinsic polysilicon successively, the described intrinsic polysilicon of chemico-mechanical polishing is until exposing isolation structure; Intrinsic polysilicon after the chemico-mechanical polishing is mixed, form multi-crystal silicon floating bar.
Preferably, the doping content of polysilicon is more than or equal to 5.0E+20cm
-2Be more preferably, the doping content of polysilicon is more than or equal to 5.0E+20cm
-2Smaller or equal to 5.0E+21cm
-2
Preferably, described dopant ion is the P ion.
A kind of manufacture method of semiconductor device, comprise: Semiconductor substrate is provided, be formed with in the described Semiconductor substrate and be used to isolate the active region isolation structure, the surface of isolation structure is higher than Semiconductor substrate, on described Semiconductor substrate and isolation structure, form gate oxide and intrinsic polysilicon successively, the described intrinsic polysilicon of chemico-mechanical polishing is until exposing isolation structure; Intrinsic polysilicon after the chemico-mechanical polishing is mixed, form multi-crystal silicon floating bar; Remove the part isolation structure between the adjacent doped polycrystalline silicon floating gate; On multi-crystal silicon floating bar, form silica-silicon-nitride and silicon oxide layer; On silica-silicon-nitride and silicon oxide layer, form control gate.
Preferably, the doping content of polysilicon is more than or equal to 5.0E+20cm
-2Be more preferably, the doping content of polysilicon is more than or equal to 5.0E+20cm
-2Smaller or equal to 5.0E+21cm
-2
Preferably, described dopant ion is the P ion.
Compared with prior art, such scheme has the following advantages:
On the one hand, when the present invention directly carries out chemico-mechanical polishing by discovering to the high-concentration dopant polysilicon, polishing speed reduces, therefore the defective that the polysilicon surface evenness reduces, provides a kind of flatening process of doped polycrystalline silicon, intrinsic polysilicon is carried out after the chemico-mechanical polishing, mix, can form the high doped polycrystalline silicon of evenness, overcome the convention of usually doped polycrystalline silicon directly being carried out chemico-mechanical polishing in the prior art.Though the present invention carries out on the basis that the high-concentration dopant polysilicon is studied, but because process of the present invention is simple, the conventional semiconductor manufacturing process steps is changed not quite, therefore, be applicable to the planarization of the polysilicon of all doping contents simultaneously.Comparative optimization, be fit to doping content greater than 5.0E+20cm
-2Highly doped polysilicon.
On the other hand, the present invention also provides a kind of manufacture method of multi-crystal silicon floating bar, on gate oxide, form intrinsic polysilicon, carry out chemico-mechanical polishing, mix at last, form multi-crystal silicon floating bar, described multi-crystal silicon floating bar has higher surface smoothness, has improved for example electrical property of flash memory of the semiconductor device that contains multi-crystal silicon floating bar that forms.
Description of drawings
Fig. 1 is the process chart of the flatening process of prior art doped polycrystalline silicon;
When Fig. 2 used polishing fluid 1 to carry out chemico-mechanical polishing for embodiment 1, the polysilicon of different levels of doping was at the polishing speed curve of crystal column surface diverse location;
Fig. 3 is the polysilicon use high selectivity polishing fluid of embodiment 1 for different levels of doping, the possible theoretical explanation that polishing speed changes;
When Fig. 4 used polishing fluid 2 to carry out chemico-mechanical polishing for embodiment 1, the polysilicon of different levels of doping was at the polishing speed curve of crystal column surface diverse location;
Fig. 5 is that the polysilicon of embodiment 1 different levels of doping uses low the selection than polishing fluid, the possible theoretical explanation of polishing speed variation;
Fig. 6 is the process chart of the flattening method of the embodiment of the invention 1 doped polycrystalline silicon;
Fig. 7 to Figure 12 is the cross section structure schematic diagram of the manufacture method of the embodiment of the invention 2 multi-crystal silicon floating bars.
Embodiment
The object of the present invention is to provide a kind of flattening method of doped polycrystalline silicon, adopt CMP (Chemical Mechanical Polishing) process, form the polysilicon that has an even surface of high-dopant concentration.
The present invention also aims to provide a kind of manufacture method of multi-crystal silicon floating bar, to obtain smooth multi-crystal silicon floating bar.
The present invention also aims to provide a kind of manufacture method of semiconductor device.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Embodiment 1
Present embodiment provides a kind of flattening method of doped polycrystalline silicon, and the polysilicon of eigenstate is provided, and carries out chemico-mechanical polishing, and polysilicon is mixed.Wherein, the doping content of described polysilicon is more than or equal to 5.0E+20cm
-2
In the existing technology, planarization for doped polycrystalline silicon all adopts CMP (Chemical Mechanical Polishing) process usually, and, usually all be that polysilicon is carried out carrying out chemico-mechanical polishing again after the doping treatment, those skilled in the art it has been generally acknowledged that doped polycrystalline silicon is carried out the technology that chemico-mechanical polishing is a kind of routine, can the stability and the polishing uniformity of technology of polishing do not exerted an influence, can not have influence on the performance of the polysilicon after the polishing yet.
Yet researcher of the present invention finds when doped polycrystalline silicon is carried out chemico-mechanical polishing, when the doping content of doped polycrystalline silicon more than or equal to 5.0E+20cm
-2, in the glossing, the polishing speed difference of wafer diverse location, therefore the surface smoothness of polysilicon reduces after the polishing, can not satisfy the needs of semiconductor device technology design.
Shown in the reference table 1, the polishing speed data of doped polycrystalline silicon face diverse location when the polysilicon of different levels of doping being carried out chemico-mechanical polishing for the present inventor, wherein RRmean represents the mean value of polishing speed, and the polishing speed RR range of a certain point of RR (Removal Rate) expression doped polycrystalline silicon face represents the amplitude of variation of polishing speed.Dopant ion in the described doped polycrystalline silicon is the P ion, and polishing fluid 1 is the two kind polishing fluids different to the polishing speed of doped polycrystalline silicon with polishing fluid 2.The ratio of the polishing speed of 2 pairs of doped polycrystalline silicon of the polishing speed of 1 pair of doped polycrystalline silicon of polishing fluid and polishing fluid is greater than 10.
Table 1
As can be seen from Table 1, no matter polishing fluid 1 still is a polishing fluid 2, when the doping content of P ion greater than 5.00E+20cm
-2The time, polishing fluid is to the polishing speed of doped polycrystalline silicon step-down all, and at the diverse location of doped polycrystalline silicon face, it is big that the difference of polishing speed becomes, therefore, and polishing speed uniformity variation, the evenness variation of polishing back doped polycrystalline silicon face.
With reference to the accompanying drawings shown in 2, when carrying out chemico-mechanical polishing for 1 pair of polysilicon of employing polishing fluid, the polishing speed change curve of polysilicon surface diverse location, contain in the described polishing fluid 1 and have oxidizing substance, adopt chemical reaction corrosion and polishing polycrystalline silicon, for example contain the silica polishing fluid of iodate, described polysilicon be doped to the P ion doping, dopant ion concentration is respectively 0,1.40E+20cm
-2, 3.00E+20cm
-2, 5.00E+20cm
-2, 1.40E+21cm
-2In the accompanying drawing 2, X-direction is represented the position of the polysilicon of chemico-mechanical polishing, and is concrete, is the position (mm) that the polishing point is put to crystal circle center, and Y direction represents to polish polishing speed a little.
As can be seen from Figure 2, along with the increase of P doping content in the polysilicon, the speed of chemico-mechanical polishing reduces, and the evenness of polysilicon surface reduces after the chemico-mechanical polishing.The inventor has inquired into the possible cause that produces described phenomenon, with reference to the accompanying drawings shown in 3, when selecting described polishing fluid for use, usually contain the stronger anion of oxidation susceptibility in the polishing fluid, when containing dopant ions such as P in the polysilicon, there is unnecessary electronics in the surface of polysilicon, when carrying out chemico-mechanical polishing, in excess electron in the polysilicon and the polishing fluid to contain negative oxygen ion mutually exclusive, cause polishing speed to reduce, finally cause existing in the polysilicon position polishing speed of dopant ion low, do not have the position polishing speed height of dopant ion, the evenness of polishing back polysilicon surface reduces.
With reference to the accompanying drawings shown in 4, when carrying out chemico-mechanical polishing for 2 pairs of polysilicons of employing polishing fluid, the polishing speed varied curve figure of polysilicon surface diverse location, described polishing fluid 2 Main physical active force polishing polycrystalline silicons, mainly be polished to and be divided into water and silica, described polysilicon be doped to the P ion doping, dopant ion concentration is respectively 0,1.40E+20cm
-2, 3.00E+20cm
-2, 5.00E+20cm
-2, 1.40E+21cm
-2In the accompanying drawing 2, X-axis is represented the position of the polysilicon of chemico-mechanical polishing, and is concrete, is the position (mm) that the polishing point is put to crystal circle center, and Y-axis represents to polish polishing speed a little.
As can be seen from Figure 4, along with the increase of P doping content in the polysilicon, the speed of chemico-mechanical polishing reduces, and the evenness of polysilicon surface reduces after the chemico-mechanical polishing.The inventor has inquired into the possible cause that produces described phenomenon, with reference to the accompanying drawings shown in 5, when selecting described polishing fluid for use, usually the hydroxide ion in the aqueous solution that contains in the polishing fluid is electronegative, when containing dopant ions such as P in the polysilicon, there is unnecessary electronics in the surface of polysilicon, when carrying out chemico-mechanical polishing, excess electron and the hydroxide ion in the polishing fluid in the polysilicon are mutually exclusive, cause polishing speed to reduce, therefore, cause existing in the polysilicon position polishing speed of dopant ion low, the position polishing speed height that does not have dopant ion causes polishing back doped polycrystalline silicon surface smoothness and reduces.
Therefore, no matter adopt the polishing fluid of which kind of type, along with the increase of P doping content, the speed of chemico-mechanical polishing reduces, and the evenness of polysilicon surface reduces after the chemico-mechanical polishing, and test shows that the dopant ion concentration in polysilicon is greater than 5.0E+20cm
-2The time, the evenness of polishing back polysilicon surface can't satisfy the needs of technological design.
Therefore, present embodiment proposes new polysilicon flattening method, with reference to the accompanying drawings shown in 6 according to above-mentioned research, step S100 provides intrinsic polysilicon, step S110, intrinsic polysilicon is carried out chemico-mechanical polishing, and step S120 mixes to the polysilicon after the polishing.
Described intrinsic polysilicon can be the polysilicon in any semiconductor fabrication process, for example, being used as the polysilicon of floating boom or grid in the memory manufacture craft, also can be the polysilicon that is used to form polysilicon plug or dual-damascene structure in ic manufacturing process.
Described CMP (Chemical Mechanical Polishing) process is a prior art, according to the needs of technology, selects suitable polishing fluid and glossing for use, for example, in being used to form the technology of multi-crystal silicon floating bar, selects described polishing fluid 1 of present embodiment or polishing fluid 2 for use.
Intrinsic polysilicon is carried out polysilicon being mixed after the chemico-mechanical polishing, and described dopant ion can be that the N type mixes, and the dopant ion of injection is the ion of V major element, and relatively the ion of You Huaing is an arsenic ion, phosphonium ion etc.; Also can be that the P type mixes, the dopant ion of injection be the ion of III major element, and relatively the ion of You Huaing is a B ion etc.In the present embodiment, preferred doped polycrystalline silicon is mixed the preferred P ion of dopant ion for the N type.
The described process of present embodiment is applicable to the multi crystal silicon chemical mechanical polishing of any doping content, is particularly useful for doping content more than or equal to 5.0E+20cm
-2The chemico-mechanical polishing of doped polycrystalline silicon, be more preferably, be applicable to that doping content is more than or equal to 5.0E+20cm
-2Smaller or equal to 5.0E+21cm
-2The chemico-mechanical polishing of doped polycrystalline silicon.
Adopt the described process of present embodiment, polysilicon is carried out mixing after the chemico-mechanical polishing again, the defective that polishing speed descends when having avoided in the prior art direct polishing polycrystalline silicon fully, and, the ion in the polishing fluid and the interaction of dopant ion have been avoided, cause the different defective of polysilicon surface diverse location polishing speed, improved the evenness of polishing back doped polycrystalline silicon face.
Embodiment 2
Present embodiment provides a kind of manufacture method of multi-crystal silicon floating bar, Semiconductor substrate is provided, be formed with in the described Semiconductor substrate and be used to isolate the active region isolation structure, the surface of isolation structure is higher than Semiconductor substrate, on described Semiconductor substrate and isolation structure, form gate oxide and intrinsic polysilicon successively, the described intrinsic polysilicon of chemico-mechanical polishing is until exposing isolation structure; Intrinsic polysilicon after the chemico-mechanical polishing is mixed, form multi-crystal silicon floating bar.
Shown in 7, provide Semiconductor substrate 100 with reference to the accompanying drawings, described Semiconductor substrate 100 can be semi-conducting materials such as silicon or silicon-on-insulator (SOI) or SiGe, and described Semiconductor substrate 100 is N type or P type doped semiconductor materials.
Be formed with isolation structure 110 in Semiconductor substrate 100, described isolation structure 110 is trench isolations (STI) structure or selective oxidation silicon (LOCOS) isolation structure, the preferred groove isolation construction of present embodiment.In the prior art, the surface of the groove isolation construction of formation is usually above the surface of Semiconductor substrate.
The formation technology of fleet plough groove isolation structure can be any one process that those skilled in the art understand, for example: on Semiconductor substrate, form pad oxide and corrosion barrier layer successively, and etching corrosion barrier layer, pad oxide and Semiconductor substrate successively, in Semiconductor substrate, form groove; Form lining oxide layer at grooved inner surface; Adopt chemical vapor deposition method in groove inside and pad oxide sidewall and corrosion barrier layer surface form the first insulation lining; Form the isolated insulation layer that covers the first insulation lining and fill up groove; The described isolated insulation layer of planarization is to exposing corrosion barrier layer; Remove corrosion barrier layer and pad oxide on the semiconductor substrate successively, form fleet plough groove isolation structure.Adopt the surface of the surface of the groove isolation construction that described or similar shallow ditch groove separation process forms usually above Semiconductor substrate.
Shown in 8, form gate oxide 120 and intrinsic polysilicon layer 130 on Semiconductor substrate with reference to the accompanying drawings, described gate oxide can be silica (SiO
2) or silicon oxynitride (SiNO).Can also be high-k (high K) materials such as hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide.
The formation technology of described gate oxide and intrinsic polysilicon is any prior art well known to those skilled in the art, preferably, for example adopt chemical vapour deposition technique, the gate oxide that forms is positioned on the Semiconductor substrate, when adopting chemical vapor deposition method, described gate oxide is arranged in (figure does not mark) on the fleet plough groove isolation structure simultaneously, and the thickness of described gate oxide is 200 dust to 2000 dusts.
After forming gate oxide, adopt chemical vapor deposition method deposition intrinsic polysilicon layer on gate oxide, the thickness of described intrinsic polysilicon is 200 dust to 1500 dusts.
The thickness sum of described gate oxide and intrinsic polysilicon can be greater than or less than the height that fleet plough groove isolation structure exceeds semiconductor substrate surface.
Shown in 9, described intrinsic polysilicon layer 130 is carried out chemico-mechanical polishing with reference to the accompanying drawings, form smooth intrinsic polysilicon surface, until exposing isolation structure.
Carry out polishing fluid that chemico-mechanical polishing adopts and concrete glossing and can adopt prior art, in the present embodiment, provide a kind of embodiment, select the polishing fluid of high selectivity for use, described polishing fluid to the ratio of the polishing speed of polysilicon and silicon dioxide approximately greater than 30, for example, it is abrasive grains that described polishing fluid adopts silicon dioxide, and be added with for example iodate of chemical addition agent, because described polysilicon is an intrinsic polysilicon, therefore, in the glossing, the polishing speed of polysilicon surface is fast, and the polishing speed of polysilicon surface diverse location is identical, and polishing fluid and glossing can not exert an influence to the surface smoothness of intrinsic polysilicon.
Shown in 10, intrinsic polysilicon is mixed with reference to the accompanying drawings, form multi-crystal silicon floating bar, can carry out N type or the doping of P type, decide according to the performance of semiconductor device and the needs of technological design to described intrinsic polysilicon.When carrying out the doping of N type, the dopant ion of injection is the ion of V major element, and relatively the ion of You Huaing is an arsenic ion, phosphonium ion etc.; When carrying out the doping of P type, the dopant ion of injection is the ion of III major element, and relatively the ion of You Huaing is a B ion etc.In the present embodiment, preferred doped polycrystalline silicon is mixed the preferred P ion of dopant ion for the N type.In the present embodiment, dopant ion concentration is more than or equal to 5.0E+20cm
-2, preferred, the doping content of described doped polycrystalline silicon is more than or equal to 5.0E+20cm
-2Smaller or equal to 5.0E+21cm
-2
It is any prior art well known to those skilled in the art that described polysilicon is carried out the technology that the N type mixes or the P type mixes, and dopant ion concentration for example is 5.0E+20cm
-2, 8.0E+20cm
-2, 1.0E+21cm
-2, 2.5E+21cm
-2Deng.
With reference to the accompanying drawings 11, after intrinsic polysilicon mixed, form multi-crystal silicon floating bar 130a.
With reference to the accompanying drawings 12, remove the part isolation structure between the adjacent doped polycrystalline silicon floating gate, make the apparent height of doped polycrystalline silicon be slightly larger than isolation structure.
The technology of removing described isolation structure is prior art, for example adopts concrete process using wet etching, selects for use hydrofluoric acid as etching agent.
Adopt the described floating polysilicon grid preparation method of present embodiment, at first form intrinsic polysilicon, afterwards intrinsic polysilicon is carried out chemico-mechanical polishing, and then mix, polishing speed descends when avoiding prior art directly doped polycrystalline silicon to be carried out chemico-mechanical polishing, the defective that the polysilicon surface evenness reduces has improved polishing speed, and has obtained the doped polycrystalline silicon face that evenness meets the technological design needs.Doping content is polysilicon to be carried out the polishing speed of chemico-mechanical polishing and the flatness data of polishing back polysilicon surface at 0 o'clock in its polishing speed and the evenness reference example.
Form after the above-mentioned multi-crystal silicon floating bar, on described multi-crystal silicon floating bar, adopt chemical vapor deposition method cvd silicon oxide-silicon-nitride and silicon oxide layer, adopt chemical vapor deposition method on silica-silicon-nitride and silicon oxide layer, to deposit control gate afterwards again, can form semiconductor device.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (8)
1. the manufacture method of a multi-crystal silicon floating bar comprises:
Semiconductor substrate is provided, is formed with in the described Semiconductor substrate and is used to isolate the active region isolation structure, the surface of isolation structure is higher than Semiconductor substrate;
On described Semiconductor substrate and isolation structure, form gate oxide and intrinsic polysilicon successively;
The described intrinsic polysilicon of chemico-mechanical polishing is until exposing isolation structure;
Intrinsic polysilicon after the chemico-mechanical polishing is mixed, form multi-crystal silicon floating bar.
2. according to the manufacture method of the described multi-crystal silicon floating bar of claim 1, it is characterized in that the doping content of described multi-crystal silicon floating bar is more than or equal to 5.0E+20cm
-2
3. according to the manufacture method of the described multi-crystal silicon floating bar of claim 1, it is characterized in that the doping content of described multi-crystal silicon floating bar is more than or equal to 5.0E+20cm
-2Smaller or equal to 5.0E+21cm
-2
4. according to the manufacture method of the described multi-crystal silicon floating bar of claim 1, it is characterized in that described dopant ion is the P ion.
5. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, is formed with in the described Semiconductor substrate and is used to isolate the active region isolation structure, the surface of isolation structure is higher than Semiconductor substrate;
On described Semiconductor substrate and isolation structure, form gate oxide and intrinsic polysilicon successively;
The described intrinsic polysilicon of chemico-mechanical polishing is until exposing isolation structure;
Intrinsic polysilicon after the chemico-mechanical polishing is mixed, form multi-crystal silicon floating bar;
Remove the part isolation structure between the adjacent doped polycrystalline silicon floating gate;
On multi-crystal silicon floating bar, form silica-silicon-nitride and silicon oxide layer;
On silica-silicon-nitride and silicon oxide layer, form control gate.
6. according to the manufacture method of the described semiconductor device of claim 5, it is characterized in that the doping content of described multi-crystal silicon floating bar is greater than 5.0E+20cm
-2
7. according to the manufacture method of the described semiconductor device of claim 5, it is characterized in that the doping content of described multi-crystal silicon floating bar is greater than 5.0E+20cm
-2Smaller or equal to 5.0E+21cm
-2
8. according to the manufacture method of the described semiconductor device of claim 5, it is characterized in that described dopant ion is the P ion.
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| CN103681512A (en) * | 2013-11-29 | 2014-03-26 | 上海华力微电子有限公司 | Method of improving growth effect of film in small-sized trenches |
| CN106558471B (en) * | 2015-09-25 | 2021-02-26 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN113206094B (en) * | 2020-02-03 | 2022-07-29 | 联芯集成电路制造(厦门)有限公司 | Method for manufacturing semiconductor element |
| CN113611604A (en) * | 2021-03-19 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | Method for manufacturing semiconductor element |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5915183A (en) * | 1998-06-26 | 1999-06-22 | International Business Machines Corporation | Raised source/drain using recess etch of polysilicon |
| CN1835208A (en) * | 2005-03-18 | 2006-09-20 | 海力士半导体有限公司 | Method for fabricating semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5915183A (en) * | 1998-06-26 | 1999-06-22 | International Business Machines Corporation | Raised source/drain using recess etch of polysilicon |
| CN1835208A (en) * | 2005-03-18 | 2006-09-20 | 海力士半导体有限公司 | Method for fabricating semiconductor device |
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