CN101567356A - Circuit board structure and manufacture method thereof - Google Patents
Circuit board structure and manufacture method thereof Download PDFInfo
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- CN101567356A CN101567356A CN 200810093531 CN200810093531A CN101567356A CN 101567356 A CN101567356 A CN 101567356A CN 200810093531 CN200810093531 CN 200810093531 CN 200810093531 A CN200810093531 A CN 200810093531A CN 101567356 A CN101567356 A CN 101567356A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention discloses a circuit board structure and a manufacture method thereof. The circuit board structure comprises a core board and at least one layer increase structure, wherein the surface of the core board is provided with a first line layer with a plurality of electric connection pads; and the layer increase structure covers the surface of the core board, and comprises a dielectric layer, a second line layer and a plurality of conductive blind holes. The conductive blind holes are electrically connected with the electric connection pads and the second line layer, and the surfaces of the second line layer and the conductive blind holes are leveled with the surface of the dielectric layer. The invention also provides a making method of the circuit board structure. The invention can effectively control the shape of a line so as to form a circuit board of a thin line, and can improve the electric function of the circuit board simultaneously.
Description
Technical field
The present invention relates to a kind of board structure of circuit and manufacture method thereof, particularly a kind of board structure of circuit and manufacture method thereof with fine rule road.
Background technology
Flourish along with electronic industry, electronic product also marches toward multi-functional, high performance research and development trend gradually.For satisfying the package requirements of semiconductor package part high integration (integration) and microminiaturized (miniaturization), carry for how main passive device and circuit and to connect, conductor package substrate also develops into multilayer circuit board (multi-layer board) by double-layer circuit board gradually, can be on the conductor package substrate in utilization interlayer interconnection technique (interlayer connection) under the limited space for the configuration area that utilizes to enlarge, integrated circuit (integrated circuit) needs that cooperate elevated track density whereby, reduce the thickness of base plate for packaging, under the same substrate unit are, to hold the circuit and the electronic component of greater number.
For the computing according to microprocessor, chipset, drawing chip and Application Specific Integrated Circuit high-effect chips such as (ASIC) needs, the conductor package substrate that is furnished with lead also need promote it and transmit chip signal, improves functions such as frequency range, control group, achieves the development that high I/O counts packaging part.Yet semiconductor package part is compact, multi-functional, high-speed in order to meet, the exploitation direction of elevated track density and high frequencyization, and base plate for packaging is towards the fine rule road and the small-bore development.Existing conductor package substrate manufacturing process is from the wire sizes of 100 microns of tradition, be reduced to present below 30 microns, wherein, comprise that conductor width (line width), line pitch (space) and depth-to-width ratio (aspect ratio) etc. continue to research and develop towards littler circuit precision.
For improving the wiring precision of conductor package substrate, industry develops and a kind of layer technology (build-up) that increase, also promptly utilize circuit to increase layer a technology interactive stacked multilayer dielectric layer and a line layer on a core circuit plate (core circuit board) surface, and in this dielectric layer, offer conductive blind hole (conductive via) to keep supplying, be electrically connected between lower floor's circuit, and this circuit increases the key that layer manufacturing process influences the conductor package substrate line density, according to existing technology, the practitioner is many, and (semi-additive process SAP) makes the circuit layer reinforced structure with semi-additive process.
And the flow process of this semi-additive process please refer to Fig. 1 a to 1f.At first as shown in Figure 1a, one core board 10 is provided, these core board 10 upper and lower surfaces respectively have a line layer 11, and be formed with a plurality of conductive through holes 101 in this core board 10, to be electrically connected the line layer 11 of these core board 10 upper and lower surfaces, wherein, be filled with resin 12 in described a plurality of conductive through holes 101, with reference to figure 1b, form the surface that a dielectric layer 13 covers this core board 10 and this line layer 11 fully again.Then shown in Fig. 1 c, on this dielectric layer 13, form a plurality of perforates 131, appearing this line layer 11 of part, and in this dielectric layer 13 and described a plurality of perforate 131 thereof, form a conductive layer 16 as electrical connection pad 111.Then shown in Fig. 1 d, on this conductive layer 16, form a patterning resistance layer (resist layer) 14.Then this core board 10 is inserted (not shown) in the electroplating bath, utilize this conductive layer 16 conduction currents, form a metal level in the opening of this patterning resistance layer 14 to electroplate.For another example shown in Fig. 1 f, remove this patterning resistance layer 14 after, and carry out etching and remove this conductive layer 16 that is covered by this patterning resistance layer 14 originally, just finish another line layer 151 and a plurality of conductive blind hole 152.So, the utilization above-mentioned steps repeats to form dielectric layer and line layer, promptly makes a circuit board with multilayer line layer reinforced structure.In addition, relation because of the photoengraving carving technology contraposition limit, its resistance layer 14 perforates 131 must be greater than conductive blind hole 152, so shown in Fig. 1 g, it is the vertical view at Fig. 1 f dotted line A sign place, described a plurality of conductive blind hole 152 peripheries are all around there being an extension, and with as orifice ring 152a, this orifice ring 152a is connected with this line layer 151.
In the making of aforementioned semi-additive process, need etching to remove this conductive layer 16 that this patterning resistance layer 14 is covered, feasible script is positioned at the line layer 151 on dielectric layer 13 surfaces, must reduce its width through after the etching, and make the live width of line layer 151 also lower than the live width of originally estimating, therefore can't keep the quality of line layer originally, if quality instability in the technology, may cause the wherein narrow situation that opens circuit of circuit, if but increase the live width of line layer 151 originally, then be an impediment to the lifting of fine line technology ability.In addition, the orifice ring 152a that is centered around these conductive blind hole 152 peripheries has also occupied the part wiring space, and therefore existing build-up circuit layer 151 is positioned at the structure on dielectric layer 13 surfaces, for promoting the fine line technology ability, still has its technical bottleneck.
Summary of the invention
In view of the foregoing, main purpose of the present invention promptly is to provide a kind of board structure of circuit and preparation method thereof, so as to the shape of effective control circuit, forms the circuit board on fine rule road, can promote the electric work energy of circuit board simultaneously.
For reaching above-mentioned purpose, a kind of board structure of circuit of the present invention comprises: a core board, its surface have one first line layer, and this first line layer has a plurality of electrical connection pads; And at least one layer reinforced structure, cover the surface of this core board, described layer reinforced structure comprises a dielectric layer, one second line layer and a plurality of conductive blind hole, wherein said a plurality of conductive blind hole is electrically connected described a plurality of electrical connection pad and this second line layer, and the flush of the surface of this second line layer and described a plurality of conductive blind holes and this dielectric layer.
Because the surface of this second line layer and described a plurality of conductive blind holes all with the flush of this dielectric layer, so the effective shape of control circuit and can form the circuit board on fine rule road.
In the foregoing circuit plate structure, described a plurality of conductive blind holes can be solid metal column.And this dielectric layer and this second line layer, and has a conductive layer between this dielectric layer and the described a plurality of conductive blind hole.In addition; also can comprise the outermost layer that an insulating protective layer covers described at least one layer reinforced structure; and this insulating protective layer has a plurality of perforates; with partially conductive blind hole and part second line layer that exposes this outermost layer layer reinforced structure; in order to as electrical connection pad, and this insulating protective layer can be a welding resisting layer.
The both sides of foregoing circuit plate can be one respectively and put brilliant side and and plant the ball side, and wherein this is put brilliant side and plant the ball side and has a plurality of conductive blind holes, and the periphery of described a plurality of conductive blind holes does not all have orifice ring.Described to put brilliant side be the side that the foregoing circuit plate is placed chip, and the described ball side of planting is the side that the foregoing circuit plate plants solder ball.
In addition, in the foregoing circuit plate structure, this core board is a core with a substrate, and this first line layer is formed at this substrate surface, and is formed with this first line layer that a plurality of conductive through holes are electrically connected to this substrate surface in this substrate.Wherein, this core board number of plies is not limit, and can be double-layer circuit board or multilayer circuit board.In addition, existing dielectric material often is filled with big molecule filler (Max=10 μ m), and be unfavorable for making fine rule road (live width/line-spacing, L/S＜15/15 μ m), dielectric layer of the present invention is one to have the photonasty dielectric material of high resistivity, and can stop effectively that line pitch dwindles electromigration or the point discharge effect that causes, and can carry out exposure imaging to form perforate, wherein, this photonasty dielectric material can select to be added with at least one micromolecule filler, or select not add filler, therefore can be beneficial to and make fine rule road (L/S＜15/15 μ m).
The present invention also provides a kind of manufacture method of board structure of circuit, may further comprise the steps: a core board is provided, and this core board surface has one first line layer, and this first line layer has a plurality of electrical connection pads; Form a dielectric layer, cover the surface of this core board and this first line layer, form a plurality of line opening in this dielectric layer, wherein the part line opening is then carried out laser drill again, manifests described a plurality of electrical connection pad to form a plurality of perforates; Form a metal level, cover in this dielectric layer surface, described a plurality of line opening and in described a plurality of perforates; And remove this metal level that highly is higher than this dielectric layer surface, this metal level that reaches in described a plurality of perforates in described a plurality of line opening forms one second line layer and a plurality of conductive blind hole respectively, to finish a circuit layer reinforced structure, wherein said a plurality of conductive blind hole is electrically connected described a plurality of electrical connection pad and this second line layer, and the flush of the surface of this second line layer and described a plurality of conductive blind holes and this dielectric layer.
In the manufacture method of foregoing circuit plate structure, by the formed described a plurality of conductive blind holes of this metal level, it can be solid metal column.Described a plurality of line opening of this dielectric layer utilize exposure imaging to form in addition, form described a plurality of perforate by the laser drill mode again, to manifest described a plurality of electrical connection pads of this first line layer.
Moreover the degree of depth of the formed described a plurality of line opening of above-mentioned manufacture method is preferably less than the degree of depth of described a plurality of perforates.
Description of drawings
Fig. 1 a to 1f is the schematic flow sheet of known semi-additive process.
Fig. 1 g is the schematic top plan view at Fig. 1 f dotted line A sign place.
Fig. 2 a to 2h is the schematic flow sheet of the board structure of circuit manufacture method of the embodiment of the invention.
Fig. 2 i is the schematic top plan view at Fig. 2 h dotted line A ' sign place.
Fig. 3 is the generalized section of embodiment of the invention board structure of circuit.
Fig. 4 is the generalized section of embodiment of the invention board structure of circuit.
Fig. 5 is the generalized section of embodiment of the invention board structure of circuit.
And the description of reference numerals in the above-mentioned accompanying drawing is as follows:
10 core boards, 101 conductive through holes
11 line layers, 111 electrical connection pads
12 resins, 13 dielectric layers
131 perforates, 14 resistance layers
152 conductive blind holes, 151 line layers
16 conductive layer 152a orifice rings
20 core boards, 201 substrates
202 conductive through holes, 21 first line layers
211 electrical connection pads, 22 resins
23 dielectric layers, 231 line opening
232 perforates, 24 metal levels
242 second line layers, 241 conductive blind holes
25a puts brilliant side 27 insulating protective layers
23a dielectric layer surface 25b plants the ball side
271 perforates, 26 conductive layers
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those of ordinary skills can understand other advantages of the present invention and effect easily by the content that this specification disclosed.The present invention also can be implemented or be used by other different specific embodiments, and the every details in this specification also can be carried out various modifications and change based on different viewpoints and application under not departing from spirit of the present invention.
Accompanying drawing described in the embodiments of the invention is the schematic diagram of simplification.Described accompanying drawing only shows the element relevant with the present invention, the mode when its shown element is not actual enforcement, and component number, the shape equal proportion during its actual enforcement is an optionally design, and its component placement kenel may be more complicated.
Embodiment 1
Please refer to Fig. 2 a～Fig. 2 h, this is the schematic flow sheet of present embodiment board structure of circuit manufacture method.
Shown in Fig. 2 a, a core board 20 at first is provided, these core board 20 upper and lower surfaces respectively have one first line layer 21, and this first line layer 21 has a plurality of electrical connection pads 211.Therefore, the employed core board of present embodiment can be bilayer or the multilayer circuit board of finishing first line layer, this core board 20 is a core with a substrate 201 in addition, this first line layer 21 is formed at this substrate 201 upper and lower surfaces, and be formed with a plurality of conductive through holes 202 in this substrate 201, and be electrically connected this first line layers 21 of this substrate 201 both side surface, wherein, be filled with resin 22 in described a plurality of conductive through holes 202.
Then shown in Fig. 2 b,, form the surface that a dielectric layer 23 covers this core board 20 and this first line layer 21 fully by the mode of printing, spin coating or pressing.In the present embodiment, this dielectric layer 23 belongs to one and has the photonasty dielectric material of high resistivity, and can be added with at least one micromolecule filler, or selects not add filler and also can.
With reference to figure 2c, utilize the mode of exposure imaging then, on this dielectric layer 23, form a plurality of line opening 231.
Then shown in Fig. 2 d, by the mode of laser drill, part line opening 231 is carried out laser drill more again, form a plurality of perforates 232, to the described a plurality of electrical connection pads 211 that manifest this first line layer 21.Then, form described a plurality of electrical connection pads 211 that a conductive layer 26 covers described a plurality of line opening 231, described a plurality of perforates 232 and this first line layer 21 earlier by modes such as sputter or electroless-platings.
Then,, form in a metal level 24 these dielectric layer 23 surfaces of covering, the described a plurality of line opening 231 and in described a plurality of perforates 232 to electroplate by these conductive layer 26 conduction currents with reference to figure 2e.It is made that this metal level 24 is selected from one of them of the group that is made up of metals such as lead, tin, silver, copper, gold, bismuth, antimony, zinc, nickel, zirconium, magnesium, indium, tellurium, aluminium and gallium and alloy thereof.
Then with reference to figure 2f, utilize brushing or etched mode, remove this metal level 24 and this conductive layer 26 that highly are higher than this dielectric layer surface 23a, this metal level 24 that reaches in described a plurality of perforates 232 in described a plurality of line opening 231 forms one second line layer 242 and a plurality of conductive blind hole 241 respectively.Wherein partially conductive blind hole 241 is electrically connected described a plurality of electrical connection pads 211 and this second line layer 242 of this first line layer 21 on this core board 20, and the surface of this second line layer 242 and described a plurality of conductive blind hole 241 and the flush of this dielectric layer 23, so, can finish layer reinforced structure by above-mentioned steps.
In addition, formed this metal level 24 of above-mentioned plating, a plurality of perforates 232 as described in can being full of fully as Fig. 2 f are just thus formed described a plurality of conductive blind holes 241 form solid metal column.
So far, can repeat the step of above-mentioned Fig. 2 b to Fig. 2 f according to need, produce the layer reinforced structure of multilayer.So just, finish board structure of circuit of the present invention, it comprises shown in Fig. 2 g: a core board 20, its surface have one first line layer 21, and this first line layer 21 has a plurality of electrical connection pads 211; And at least one layer reinforced structure, cover the surface of this core board 20, this at least one layer reinforced structure comprises a dielectric layer 23, one second line layer 242 and a plurality of conductive blind hole 241, wherein said a plurality of conductive blind hole 241 is electrically connected to described a plurality of electrical connection pad 211 and this second line layer 242, and the flush of the surface of this second line layer 242 and described a plurality of conductive blind hole 241 and this dielectric layer 23.
For another example shown in Fig. 2 g, in this dielectric layer 23 of layer reinforced structure, described a plurality of conductive blind holes 241, and this second line layer 242 on, form an insulating protective layer 27.Then, on this insulating protective layer 27, offer a plurality of perforates 271, with partially conductive blind hole 241 and part second line layer 242 that exposes this outermost layer layer reinforced structure, with as electrical connection pad with reference to figure 2h.In the present embodiment, this insulating protective layer 27 is a welding resisting layer.
And shown in the board structure of circuit shown in Fig. 2 h, its both sides are respectively puts brilliant side 25a and plants ball side 25b, wherein, put brilliant side 25a and utilize partially conductive blind hole 241 and part second line layer 242,, put semiconductor chip for forming solder bump and connecing as electrical connection pad.Wherein, Fig. 2 i is the vertical view at Fig. 2 h dotted line A ' sign place, and by Fig. 2 i as can be known, putting brilliant side 25a conductive blind hole 241 peripheries does not have the orifice ring 152a that disclosed as prior art Fig. 1 f and 1g.
The opposite side surface is one and plants ball side 25b, it puts printed circuit board (PCB) for forming solder ball and connecing, this is planted ball side 25b and also utilizes partially conductive blind hole 241 and part second line layer 242, as electrical connection pad, the solder ball of this side is beneficial to plant solder ball much larger than conductive blind hole 241, and connects and put printed circuit board (PCB), conductive blind hole 241 peripheries of planting ball side 25b connect second line layer 242, but also do not have orifice ring as conductive blind hole 241 peripheries of putting brilliant side 25a.
In addition, form perforate 271 on insulating protective layer 27, appear partially conductive blind hole 241 and part second line layer 242, with as electrical connection pad, the definition form of this electrical connection pad is as follows.
One is shown in Fig. 2 h, described a plurality of insulating protective layer 27 parts with perforate 271 cover (partially cover), and this puts the peripheral part of the electrical connection pad of brilliant side 25a, and part covers the peripheral part that this plants the electrical connection pad of ball side 25b, this electrical connection pad is welding resisting layer definition type electrical connection pad (soldermask defined pad, SMD pad);
It is two for as shown in Figure 3, described a plurality of insulating protective layers 27 with perforate 271 that circuit board is put brilliant side 25a do not cover (not cover), and this puts the electrical connection pad of brilliant side 25a, and insulating protective layer 27 does not contact this electrical connection pad yet, this electrical connection pad is non-welding resisting layer definition type electrical connection pad (non-soldermask defined pad, NSMD pad), described a plurality of 27 parts of insulating protective layer with perforate 271 of implanting circuit board side 25b cover the peripheral part of described a plurality of electrical connection pads;
It is three for as shown in Figure 4, described a plurality of insulating protective layers 27 with perforate 271 that circuit board is put brilliant side 25a do not cover described a plurality of electrical connection pad, and insulating protective layer 27 does not contact this electrical connection pad yet, described a plurality of insulating protective layers 27 with perforate 271 of implanting circuit board side 25b do not cover the peripheral part of described a plurality of electrical connection pads yet, and insulating protective layer 27 does not contact this electrical connection pad yet; And
It is four for as shown in Figure 5; described a plurality of insulating protective layer 27 parts with perforate 271 that circuit board is put brilliant side 25a cover the peripheral part of described a plurality of electrical connection pads; described a plurality of 27 electrical connection pads that do not cover described a plurality of conductive structure 241 of insulating protective layer of implanting circuit board side 25b with perforate 271, and insulating protective layer 27 does not contact this electrical connection pad yet.
Therefore, board structure of circuit of the present invention and preparation method thereof, because of the surface of this second line layer 242 and described a plurality of conductive blind hole 241 all with the flush of this dielectric layer 23, so the effective shape of control circuit, and can form the circuit board on fine rule road, can promote the electric work energy of circuit board simultaneously.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claims are described, but not only limits to the foregoing description.
Claims (12)
1. board structure of circuit comprises:
One core board, its surface have one first line layer, and this first line layer has a plurality of electrical connection pads; And
At least one layer reinforced structure, cover the surface of this core board, described at least one layer reinforced structure comprises a dielectric layer, one second line layer and a plurality of conductive blind hole, wherein said a plurality of conductive blind hole is electrically connected to described a plurality of electrical connection pad and this second line layer, and the flush of the surface of this second line layer and described a plurality of conductive blind holes and this dielectric layer.
2. board structure of circuit as claimed in claim 1, wherein, this dielectric layer and this second line layer, and have a conductive layer between this dielectric layer and the described a plurality of conductive blind hole.
3. board structure of circuit as claimed in claim 1; also comprise an insulating protective layer, cover the outermost layer of this at least one layer reinforced structure, and this insulating protective layer has a plurality of perforates; with partially conductive blind hole and part second line layer that exposes this outermost layer layer reinforced structure, in order to as electrical connection pad.
4. board structure of circuit as claimed in claim 3, wherein, the circuit board both sides can be one respectively and put brilliant side and and plant the ball side, and this puts brilliant side and ball-placing side surface has a plurality of conductive blind holes, and the periphery of described a plurality of conductive blind holes does not all have orifice ring.
5. board structure of circuit as claimed in claim 1, wherein, this core board is a core with a substrate, and this first line layer is formed at this substrate surface, and is formed with a plurality of conductive through holes in this substrate, is electrically connected this first line layer of this substrate both side surface.
6. the manufacture method of a board structure of circuit may further comprise the steps:
One core board is provided, and this core board surface has one first line layer, and this first line layer has a plurality of electrical connection pads;
Form a dielectric layer, cover the surface of this core board and this first line layer,
Form a plurality of line opening in this dielectric layer, wherein, the part line opening is carried out laser drill again, forms a plurality of perforates, to manifest described a plurality of electrical connection pad;
Form a metal level, cover in this dielectric layer surface, the described a plurality of line opening, reach in described a plurality of perforates; And
Remove this metal level that highly is higher than this dielectric layer surface, this metal level in described a plurality of line opening and in described a plurality of perforates forms one second line layer and a plurality of conductive blind hole respectively, to finish a circuit layer reinforced structure, wherein said a plurality of conductive blind hole is electrically connected described a plurality of electrical connection pad and this second line layer, and the flush of the surface of this second line layer and described a plurality of conductive blind holes and this dielectric layer.
7. manufacture method as claimed in claim 6, wherein, described a plurality of line opening of this dielectric layer utilize exposure imaging to form described a plurality of line opening, form described a plurality of perforate by the laser drill mode again, to manifest described a plurality of electrical connection pad.
8. manufacture method as claimed in claim 6 wherein, also is formed with a conductive layer between this dielectric layer and this metal level.
9. manufacture method as claimed in claim 6; wherein; also be formed with an insulating protective layer on this dielectric layer and this second line layer; and be formed with a plurality of perforates in this insulating protective layer; with partially conductive blind hole and part second line layer that exposes this outermost layer layer reinforced structure, in order to as electrical connection pad.
10. manufacture method as claimed in claim 9, wherein, the circuit board both sides can be one respectively and put brilliant side and and plant the ball side, and this puts brilliant side and ball-placing side surface has a plurality of conductive blind holes, and the periphery of described a plurality of conductive blind holes does not all have orifice ring.
11. manufacture method as claimed in claim 6, wherein, this core board is a core with a substrate, and this first line layer is formed at this substrate surface, and is formed with a plurality of conductive through holes in this substrate, is electrically connected to this first line layer of this substrate both side surface.
12. manufacture method as claimed in claim 6, wherein, the degree of depth of described a plurality of line opening is less than the degree of depth of described a plurality of perforates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810093531 CN101567356B (en) | 2008-04-23 | 2008-04-23 | Circuit board structure and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810093531 CN101567356B (en) | 2008-04-23 | 2008-04-23 | Circuit board structure and manufacture method thereof |
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| CN101567356A true CN101567356A (en) | 2009-10-28 |
| CN101567356B CN101567356B (en) | 2010-12-08 |
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| CN 200810093531 Active CN101567356B (en) | 2008-04-23 | 2008-04-23 | Circuit board structure and manufacture method thereof |
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| CN (1) | CN101567356B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102595778A (en) * | 2012-03-13 | 2012-07-18 | 华为技术有限公司 | Multilayer printed circuit board and manufacture method thereof |
| CN102054709B (en) * | 2009-11-06 | 2012-10-10 | 欣兴电子股份有限公司 | Manufacturing method of packed base plate |
| CN103871907A (en) * | 2014-03-26 | 2014-06-18 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing technology of ultra-thin substrate |
| CN104661429A (en) * | 2013-11-26 | 2015-05-27 | 国基电子（上海）有限公司 | Circuit board |
| CN113764847A (en) * | 2020-06-04 | 2021-12-07 | 旭德科技股份有限公司 | Waveguide structure |
| CN114173479A (en) * | 2021-11-18 | 2022-03-11 | 苏州群策科技有限公司 | Circuit board and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001185845A (en) * | 1999-12-15 | 2001-07-06 | Internatl Business Mach Corp <Ibm> | Producing method for electronic component and electronic component |
| TWI335195B (en) * | 2003-12-16 | 2010-12-21 | Ngk Spark Plug Co | Multilayer wiring board |
| CN2741319Y (en) * | 2004-10-12 | 2005-11-16 | 威盛电子股份有限公司 | Circuit substrate |
| CN1956635A (en) * | 2005-10-27 | 2007-05-02 | 全懋精密科技股份有限公司 | Structure of thin wire of multi-dielectric layer circuit board and its manufacturing method |
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2008
- 2008-04-23 CN CN 200810093531 patent/CN101567356B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102054709B (en) * | 2009-11-06 | 2012-10-10 | 欣兴电子股份有限公司 | Manufacturing method of packed base plate |
| CN102595778A (en) * | 2012-03-13 | 2012-07-18 | 华为技术有限公司 | Multilayer printed circuit board and manufacture method thereof |
| CN102595778B (en) * | 2012-03-13 | 2015-12-16 | 华为技术有限公司 | A kind of multilayer printed circuit board and manufacture method thereof |
| US9510449B2 (en) | 2012-03-13 | 2016-11-29 | Huawei Technologies Co., Ltd. | Multi-layer printed circuit board and method for fabricating multi-layer printed circuit board |
| CN104661429A (en) * | 2013-11-26 | 2015-05-27 | 国基电子（上海）有限公司 | Circuit board |
| CN103871907A (en) * | 2014-03-26 | 2014-06-18 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing technology of ultra-thin substrate |
| CN103871907B (en) * | 2014-03-26 | 2017-04-12 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing technology of ultra-thin substrate |
| CN113764847A (en) * | 2020-06-04 | 2021-12-07 | 旭德科技股份有限公司 | Waveguide structure |
| CN113764847B (en) * | 2020-06-04 | 2022-11-08 | 旭德科技股份有限公司 | Waveguide structure |
| US11764451B2 (en) | 2020-06-04 | 2023-09-19 | Subtron Technology Co., Ltd. | Waveguide structure |
| CN114173479A (en) * | 2021-11-18 | 2022-03-11 | 苏州群策科技有限公司 | Circuit board and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN101567356B (en) | 2010-12-08 |
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