CN101562148A - Method for carbon nano tube to achieve vertical interconnection of upper and lower layers of conductive material - Google Patents

Abstract

The invention discloses a method for realizing the vertical interconnection of upper and lower layers of conductive materials by using carbon nanotubes, which belongs to the interconnection technology in integrated circuits. The method comprises preparing a vertical structure including upper and lower two horizontal planes on a substrate; depositing a conductive material on the vertical structure to form upper and lower conductive layers; preparing a carbon nanotube solution, and dropping the carbon nanotube solution To the above vertical structure, and apply direct current or alternating current between the upper and lower conductive layers, the two ends of the carbon nanotubes are respectively lapped on the two layers of conductive materials; deposit insulating dielectric materials to form a carbon nanotube through-hole structure, In this way, the vertical interconnection between the upper and lower layers of conductive materials is realized. In the present invention, the carbon nanotube preparation and assembly processes are carried out separately, and the latter is carried out at room temperature, so the interconnection technology can avoid the pollution caused by the carbon nanotube preparation process to the circuit chip, and is compatible with the existing CMOS process .

Description

A method of vertical interconnection of upper and lower layers of conductive materials using carbon nanotubes

technical field

The invention relates to interconnection technology in integrated circuits, in particular to a vertical interconnection method between upper and lower layers of conductive materials.

Background technique

Interconnections in integrated circuits mainly include two types, one is horizontal interconnection within the same layer, and the other is vertical interconnection between different layers, that is, through holes. As the feature size of integrated circuits continues to scale down and the degree of integration continues to increase, the size of interconnect lines in integrated circuits also decreases, and the number of interconnect layers continues to increase. In integrated circuits, vertical interconnects that connect the upper and lower layers There are more and more through holes. However, as the line width decreases, the resistivity of the traditional copper interconnection caused by grain boundary scattering and surface roughness increases, so that the delay caused by the interconnection becomes larger and the circuit speed decreases; in addition Since the copper wiring will undergo significant electromigration when the current density exceeds 10 ⁶ A/cm ² , the circuit will become ineffective. However, carbon nanotubes have very strong current transport ability, and the highest current density they can withstand can reach 10 ⁹ A/cm ² . In addition to their unique ballistic current characteristics, their resistivity is theoretically very small. Studies have shown that at the 22nm node In the future, the advantages of carbon nanotube interconnection are much higher than that of copper interconnection, so carbon nanotubes are very suitable for interconnection materials, especially through-hole interconnection materials.

According to ITRS prediction, at the 90nm node in 2010, the minimum via hole height should be 144nm. Since the mean free path of carbon nanotubes can reach several microns, at this node, if carbon nanotubes are used as via interconnections, direct ballistic transport of current can be achieved, thereby effectively increasing the circuit speed. However, since the conductive properties of carbon nanotubes are related to their chirality and geometric size, and the size of the through holes is small, how to design the structure of the carbon nanotube through holes and select carbon nanotubes with specific chirality and geometric size according to needs, Therefore, effectively connecting the upper and lower conductive layers is the basis for realizing the interconnection of carbon nanotubes.

At present, the methods for preparing the through-hole structure of carbon nanotubes mainly include: using Ni as a catalyst on Si/SiO ₂ /Cr from bottom to top, using plasma-enhanced chemical vapor deposition to prepare vertically interconnected carbon nanotube bundles, and then Use CVD to deposit SiO ₂ to fill the gaps between carbon nanotubes, and then use chemical mechanical polishing to flatten the SiO ₂ so that only the carbon nanotube bundles are exposed on the surface, and finally deposit metal on it to realize the carbon nanotubes in the upper and lower layers. interconnection; the other is to use the catalyst buried layer (3nmFe/5nmTa/150-200nmSiO ₂ ), to prepare MWCNTs by CVD in the photolithographically good 20nm through hole with a very large aspect ratio, and then use CMP or The top of the MWCNTs was exposed by reverse etching, and the metal electrode layer was deposited, and annealed at 850°C to reduce the contact resistance, and the obtained resistivity was 7.8kohm. Due to the preparation of carbon nanotubes by PECVD method, if the growth temperature is low (<400°C), amorphous carbon is easy to be produced, and the quality of the prepared nanotubes is very poor, that is, all current methods for preparing carbon nanotube through-hole interconnections All use methods such as PECVD or CVD to grow carbon nanotubes on the spot (in-situ). First, the growth temperature cannot be too low, so it does not meet the growth temperature lower than 400 ° C predicted by ITRS. In addition, due to the on-site growth, the prepared carbon The quality of nanotubes is not well controlled.

Contents of the invention

The invention overcomes the deficiencies in the prior art and provides a vertical interconnection method between upper and lower layers of conductive materials.

Technical scheme of the present invention is:

A vertical interconnection method between upper and lower layers of conductive materials, the steps of which include:

1) Prepare a vertical structure including upper and lower horizontal planes on the substrate;

2) Depositing a conductive material on the vertical structure to form upper and lower conductive layers;

3) Prepare a carbon nanotube solution, drop the carbon nanotube solution on the above-mentioned vertical structure, and apply a direct current or an alternating current between the upper and lower conductive layers, and the two ends of the carbon nanotubes are tightly connected to the conductive layer of the two layers. on the material;

4) Depositing insulating dielectric material to form a carbon nanotube through-hole structure, so as to realize the vertical interconnection between the upper and lower layers of conductive materials.

In the step 1), the substrate can be made of Si, Ge or GaAs semiconductor material.

Before step 2), an insulating dielectric layer may be deposited on the vertical structure.

In the step 2), the conductive material can be highly doped Si, Ge, GaAs or metal Ti/Au.

In the step 2), the conductive materials used in the upper conductive layer and the lower conductive layer may be different.

In the step 3), the carbon nanotube solution may be an organic solution containing single-wall, double-wall, multi-wall or single-wall carbon nanotube bundles, and the organic solvent is ethanol, acetone, n-hexane, isopropanol, di Methylformamide or 1,2-dichloroethane.

In the step 4), the insulating dielectric layer can be made of SiO ₂ , organic, nitrogen-doped oxide or porous low-K dielectric material.

Compared with prior art, the beneficial effect of the present invention is:

In the present invention, the preparation and assembly process of carbon nanotubes are carried out separately, and the electrophoresis method is used to construct the carbon nanotubes on the upper and lower layers of conductive materials, and then deposit insulating dielectric materials to form a carbon nanotube through-hole structure, thereby realizing the upper and lower layers. A vertical interconnect structure between the lower two layers of conductive material. Adopting the present invention does not require the high-temperature preparation process of various carbon nanotubes, so the pollution to devices caused by the preparation process of carbon nanotubes will not occur. Secondly, for different nanotubes, such as single-wall and multi-wall nanotubes, nanotubes of different diameters, nanotubes of different lengths, and nanotubes of different chiral distributions, the required nanotubes can be selected according to different structures. In addition, the density of nanotube interconnection can be controlled by controlling the concentration of nanotube solution. Moreover, the interconnection between multiple layers can be realized sequentially through this method.

Description of drawings

FIG. 1 is a schematic diagram of the upper and lower two-layer structure of the vertical interconnection realized in Embodiment 1;

Fig. 2 is the process flow chart of embodiment one;

Fig. 3 is a schematic diagram of the upper and lower two-layer structure of the vertical interconnection realized in the second embodiment;

Fig. 4 is the process flow chart of embodiment two.

Detailed ways

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

Embodiment 1, taking the boss-shaped vertical structure shown in FIG. 1 as an example, the process of the present invention is described.

1) First, etch a boss structure on the silicon substrate, there is a vertical plane between the upper surface and the lower surface of the structure, and a layer of stunning dielectric layer can be deposited on the boss structure, as shown in Figure 2(a) shown.

The substrate can be a semiconductor material such as Si, Ge, GaAs, or an integrated circuit structure.

The above-mentioned insulating dielectric layer may be SiO ₂ , organic, nitrogen-doped oxide or porous low-K dielectric material.

2) depositing a conductive layer on the vertical structure;

The upper and lower layers of conductive materials can be the same material or different materials, including but not limited to metals, highly doped semiconductor materials: Si, Ge, GaAs, carbon nanotube films or conductive polymers. Among them, carbon nanotube films: single-wall carbon tube films, multi-wall carbon tube films or mixed films of single-wall and multi-wall carbon tubes, single-layer or multi-layer graphite sheets, conductive plastic polymers, etc.

The structure formed by depositing a conductive layer on the vertical structure is shown in 2(b).

3) ultrasonically dispersing carbon nanotubes in organic solutions such as ethanol, acetone, n-hexane, isopropanol, dimethylformamide or 1,2-dichloroethane to prepare a solution containing carbon nanotubes.

The carbon nanotubes here can be single-walled, double-walled, multi-walled or single-walled carbon nanotube bundles.

4) Apply direct current or alternating current between the upper and lower conductive layers deposited in step 2). The parameter range of the applied alternating current is V _PP =1-20V, frequency 1-10MHZ.

And drop the prepared carbon nanotube solution on the boss structure, the carbon nanotubes will be polarized under the action of the electric field, arranged according to the orientation of the electric field, and the two ends will be densely attached to the two layers of conductive materials , after removing the electric field, the formed structure is shown in Figure 2(c).

5) Deposit an insulating medium on the vertical structure of the carbon nanotubes to fill the gaps between the nanotubes. After the deposition is completed, a carbon nanotube through-hole structure is formed, thereby realizing the gap between the upper and lower layers of conductive materials. vertical interconnection.

The above-mentioned insulating dielectric layer may be SiO ₂ , organic, nitrogen-doped oxide or porous low-K dielectric material.

Embodiment 2, taking the groove-shaped vertical structure shown in FIG. 3 as an example, to illustrate the process of the present invention.

1) Firstly, a groove structure is etched on the substrate. There are three vertical planes between the upper surface and the lower surface of the structure. A layer of insulating dielectric layer can be deposited on the above vertical structure, as shown in Figure 3(a). Show.

The substrate can be a semiconductor material such as Si, Ge, GaAs, or any vertical structure of an integrated circuit; material 2 is an insulating dielectric material, which can be SiO ₂ , organic, nitrogen-doped oxide, or porous low-K dielectric Material.

2) Deposit a conductive layer on the upper and lower two-layer structure;

The deposited conductive layer can be metals such as Ti/Au, or highly doped semiconductor materials such as Si, Ge, GaAs, etc., as shown in 3(b).

The conductive materials of the upper and lower layers can be the same or different.

3) ultrasonically dispersing the carbon nanotubes in a chemical reagent to prepare a solution of the carbon nanotubes.

The carbon nanotubes here can be single-walled carbon nanotubes, multi-walled carbon nanotubes, or a mixture of single-walled carbon nanotubes and multi-walled carbon nanotubes.

Ultrasonic dispersion of carbon nanotubes in organic solutions such as ethanol, acetone, n-hexane, isopropanol, dimethylformamide or 1,2-dichloroethane to prepare a solution containing carbon nanotubes.

4) Direct current or alternating current is passed between the upper and lower conductive layers deposited in step 2), and direct current or alternating current is applied between the upper and lower conductive layers. The parameter range of the applied alternating current is V _PP =1-20V, frequency 1 -10MHZ. And drop the prepared carbon nanotube solution between the upper and lower conductive layers to form an interconnection structure, the carbon nanotubes will be polarized under the action of the electric field, arranged according to the orientation of the electric field, and the two ends It will be densely attached to two layers of conductive materials, and after the electric field is removed, the formed structure is shown in Figure 3(c).

5) Deposit an insulating medium on the vertical structure of the carbon nanotubes to fill the gaps between the nanotubes. After the deposition is completed, a carbon nanotube through-hole structure is formed, thereby realizing the gap between the upper and lower layers of conductive materials. vertical interconnection.

The above-mentioned insulating dielectric layer may be SiO ₂ , organic, nitrogen-doped oxide or porous low-K dielectric material.

The method for vertical interconnection between the upper and lower layers of conductive materials provided by the present invention has been described above through detailed embodiments. Those skilled in the art should understand that the present invention can be modified within the scope not departing from the essence of the present invention. Variation or modification; its preparation method is not limited to the content disclosed in the examples.

Claims (7)

1, the perpendicular interconnection method between a kind of upper and lower two layers of conductive material, its step comprises:

1) vertical stratification that preparation one comprises upper and lower two horizontal planes in substrate;

2) depositing conductive material on above-mentioned vertical stratification forms upper and lower two conductive layers;

3) the preparation carbon nano-tube solution drips to this carbon nano-tube solution on the above-mentioned vertical stratification, and apply direct current or alternating current between upper and lower conductive layer, and the two ends of carbon nano-tube are respectively closely to being overlapped on the two layers of conductive material;

4) deposit dielectric material forms the carbon nano-tube through-hole structure, thereby realizes the perpendicular interconnection between the upper and lower two layers of conductive material.

2, the method for claim 1 is characterized in that, in the described step 1), Si, Ge or GaAs semi-conducting material are adopted in described substrate.

3, the method for claim 1 is characterized in that, in step 2) before, deposit one insulating medium layer on described vertical stratification.

4, the method for claim 1 is characterized in that, described step 2) in, described electric conducting material is highly doped Si, Ge, GaAs or metal Ti/Au.

5, method as claimed in claim 4 is characterized in that, described step 2) in, it is described that upward conductive layer is different with the electric conducting material that lower conductiving layer is adopted.

6, the method for claim 1, it is characterized in that, in the described step 3), described carbon nano-tube solution is the organic solution that contains single wall, double-walled, many walls or Single Walled Carbon Nanotube tube bank, this organic solvent is ethanol, acetone, n-hexane, isopropyl alcohol, dimethyl formamide or 1, the 2-dichloroethanes.

7, the method for claim 1 is characterized in that, in the described step 4), described insulating medium layer adopts SiO ₂, organic class, nitrating oxide or porousness low-K dielectric material.

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