CN101556947B - Basal plate for reducing warpage degree and chip packaging structure provided with same - Google Patents
Basal plate for reducing warpage degree and chip packaging structure provided with same Download PDFInfo
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- CN101556947B CN101556947B CN200810089751XA CN200810089751A CN101556947B CN 101556947 B CN101556947 B CN 101556947B CN 200810089751X A CN200810089751X A CN 200810089751XA CN 200810089751 A CN200810089751 A CN 200810089751A CN 101556947 B CN101556947 B CN 101556947B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
The invention discloses a basal plate for reducing the warpage degree. The basal plate mainly comprises a core layer, wherein a line layer and a first welding shield layer are formed on one surface ofthe core layer in sequence, and a second welding shield layer and a crystal bonding layer are formed on the other surface of the core layer in sequence; and the first welding shield layer and the sec ond welding shield layer have different thickness. The invention also discloses a chip packing structure provided with the basal plate, besides the basal plate, the chip packaging structure also comprises a chip, two or more than two electric connecting elements and a sealing colloid, wherein the chip is adhered on the upper surface of the second welding shield layer by the crystal bonding layer; the two or more than two electric connecting elements are electrically connected with the chip to the first line layer of the basal plate; and the sealing collide for sealing the chip is arranged on the upper surface of the second welding shield layer of the basal layer. Due to different thickness difference of the upper welding shield layer and the lower welding shield layer, the warpage modification for resisting heat stress is produced under the temperature change so as to restrict the warpage degree of the asymmetric layer basal plate; thus the basal plate can be produced with lower cost and does not need additional stiffening elements, thereby achieving the efficacy of restricting the warpage of the basal plate in the chip packaging process.
Description
Technical field
The present invention can apply to the semiconductor die package structure relevant for a kind of printed circuit board (PCB), is particularly to a kind of chip encapsulation construction that reduces the substrate of angularity and have this substrate.
Background technology
In recent years, printed circuit board (PCB) develops into the microminiature substrate toward densification and high-effectization, with the chip carrier as semiconductor packages.Yet in known semiconductor packaging process,, need to glue brilliant colloid and be formed on the substrate, and make the heat treatment of substrate by prebake conditions for chip being arranged on the substrate.In addition, substrate may meet with various heat treatments in the semiconductor packaging process, for example, and baking-curing, projection reflow or curing of sealed colloid or the like after the sticking brilliant colloid.Yet, substrate is when bearing heat treated variations in temperature, and the unmatched problem of the thermal coefficient of expansion of (as adhesive body and chip) between other encapsulating materials (CTE, coefficient ofthermal expansion) can cause the substrate warp distortion, thereby causes operational difficulty.
As shown in Figure 1, known a kind of substrate 100 that is used for semiconductor die package is made in lamination (laminate) mode, and it comprises core layer 110, first welding cover layer 120, second welding cover layer 130, first line layer 140 and second line layer 160 usually.This core layer 110 is a kind of glass fiber-reinforced resin and as the central core of this substrate 100.Symmetrically, lower surface pressing first line layer 140 of this core layer 110, upper surface pressing second line layer 160 of this core layer 110.These first line layers 140 and second line layer 160 can be copper (copper) layer, to form most bar conductive traces (conductive trace).More symmetrically, upper surface is respectively laid first welding cover layer 120 and second welding cover layer 130 under the outermost layer of this substrate 100.The thickness of these first welding cover layers 120 and second welding cover layer 130 is generally all identical; and be the insulating properties material; cover the protective layer of conductive trace with formation; but manifest two or more outer connection pads 141 and connect finger 161, do usefulness follow-up and conducting element such as soldered ball (solder ball) or bonding wire (bondingwire) electric connection to stay with two or more.Because the laminated substrate of known substrate 100, so substrate warp and to influence the problem of Chip Packaging operation still not obvious for having the symmetrical number of plies.
Again as shown in Figure 1, in chip package process, electronic component such as semiconductor chip 11 can be arranged at the upper surface of this substrate 100 by the stickup of sticking crystal layer 12, the active surface of this chip 11 has two or more weld pads 11A, can utilize two or more to electrically connect elements 13 (for example routing form bonding wire) and connect these weld pads 11A and connect to these of this substrate 100 and refer to 161, make this chip 11 and these substrate 100 electrical interconnects.Afterwards; with adhesive body 14 with pressing mold or some glue mode; be arranged at the upper surface of this substrate 100; electrically connect element 13 to seal this chip 11 with these; suitable protection is provided; be arranged at the lower surface of this substrate 100 again with two or more external terminals 15 (common is soldered ball), to form the chip encapsulation construction of ball grid array form.
Yet, in the setting of the curing (curing) of the stickup of above-mentioned sticking crystal layer 12, adhesive body 14, external terminal 15 or subsequent thermal cyclic test (thermal cycle test) etc. the processing of heated substrates 100 is arranged all, in chip package process, easily produce the substrate warp problem.Particularly should be pre-formed when this substrate 100 by sticking crystal layer 12, owing to be somebody's turn to do when the thermal coefficient of expansion of sticking crystal layer 12 may there are differences with the thermal coefficient of expansion of this substrate 100 or should glue crystal layer 12 has tangible cure shrinkage or have the thermal expansion coefficient difference of other encapsulating material, the volume contraction that should glue crystal layer 12 can not match with this substrate 100, cause the imbalance of thermal stress, so the warpage of this substrate 100 before packaging technology can cause the decrease in yield of Chip Packaging manufacturing.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of chip encapsulation construction that reduces the substrate of angularity and have this substrate, to suppress substrate warp and to reduce manufacturing cost.
The object of the invention to solve the technical problems realizes by the following technical solutions.Comprise core layer, first welding cover layer, second welding cover layer, first line layer and sticking crystal layer according to a kind of substrate that reduces angularity of the present invention.This core layer has first surface and second surface.This first welding cover layer is formed at this first surface of this core layer.This second welding cover layer is formed at this second surface of this core layer.This first line layer is formed at this first surface of this core layer and covers this first line layer with this first welding cover layer.Should be covered on this second welding cover layer sticking crystal layer part.Wherein, this first welding cover layer and this second welding cover layer have thickness inequality, and to reduce the angularity of this substrate, this first welding cover layer is thinner than this second welding cover layer, and this sticking crystal layer has the thermal coefficient of expansion less than this first welding cover layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In the substrate of aforesaid reduction angularity, the thickness difference of this first welding cover layer and this second welding cover layer can be not less than 10 microns (μ m).
In the substrate of aforesaid reduction angularity, this first welding cover layer can be thicker than this second welding cover layer.And in the substrate of aforesaid reduction angularity, this sticking crystal layer can have the thermal coefficient of expansion roughly the same with this first welding cover layer.
In the substrate of aforesaid reduction angularity, this first welding cover layer can be thinner than this second welding cover layer, and this sticking crystal layer has the thermal coefficient of expansion less than this first welding cover layer.
In the substrate of aforesaid reduction angularity, can include second line layer, it is formed at this second surface of this core layer and covers this second line layer with this second welding cover layer, so that this substrate is lamination type (laminate).
In the substrate of aforesaid reduction angularity, also can have through hole, it runs through this first welding cover layer, this first line layer, this core layer and this second welding cover layer.
In the substrate of aforesaid reduction angularity, this first line layer can be connected with two or more outer connection pads.
For achieving the above object, the present invention also provides a kind of chip encapsulation construction with the substrate that reduces angularity, and it comprises: substrate, and this substrate comprises: core layer has first surface and second surface; First welding cover layer is formed at this first surface of this core layer; Second welding cover layer is formed at this second surface of this core layer; First line layer is formed at this first surface of this core layer and covers this first line layer with this first welding cover layer; And sticking crystal layer, the part is covered on this second welding cover layer; And this first welding cover layer and this second welding cover layer have thickness inequality, and to reduce the angularity of this substrate, this first welding cover layer is thinner than this second welding cover layer, and this sticking crystal layer has the thermal coefficient of expansion less than this first welding cover layer; Chip utilizes this sticking crystal layer adhesion and is arranged at the upper surface of this second welding cover layer; Two or more electrically connect element, electrically connect first line layer of this chip to this substrate; And adhesive body, be arranged on the upper surface of second welding cover layer of this substrate, seal this chip.
As can be seen from the above technical solutions, the substrate of reduction angularity of the present invention and chip encapsulation construction with this substrate, be laid in the upper and lower surface of substrate so as to the welding cover layer of different-thickness, under variations in temperature, produce the thermal stress of contending with each other, to suppress substrate warp.Therefore, this substrate can low manufacturing cost, can not need to increase additional stiffening elements and reaches the effect that suppresses substrate warp in chip package process.
Description of drawings
Fig. 1 is the known schematic cross-section that applies to the substrate of semiconductor die package;
Fig. 2 is the schematic cross-section according to the substrate of the reduction angularity of the present invention's first specific embodiment;
Fig. 3 is the schematic cross-section of the chip encapsulation construction of the substrate of use the present invention first specific embodiment;
Fig. 4 is the schematic cross-section according to the substrate of the reduction angularity of the present invention's second specific embodiment;
Fig. 5 is the schematic cross-section according to the substrate of the reduction angularity of the present invention's the 3rd specific embodiment;
Fig. 6 is the schematic cross-section of the chip encapsulation construction of the substrate of use the present invention the 3rd specific embodiment.
Description of reference numerals
11 chip 11A weld pads, 12 sticking crystal layers
13 electrically connect element 14 adhesive bodies 15 external terminals
21 chip 21A weld pads
23 electrically connect element 24 adhesive bodies 25 external terminals
41 chip 41A weld pads
43 electrically connect element 44 adhesive bodies 45 external terminals
100 substrates, 110 core layers
120 first welding cover layers, 130 second welding cover layers
140 first line layers, 141 outer connection pads
160 second line layers 161 connect finger
200 substrates, 210 core layers, 211 first surfaces
212 second surfaces
220 first welding cover layers, 230 second welding cover layers
240 first line layers, 241 outer connection pad 250 sticking crystal layers
260 second line layers 261 connect finger
300 substrates, 310 core layers, 311 first surfaces
312 second surfaces
320 first welding cover layers, 330 second welding cover layers
340 first line layers, 341 outer connection pad 350 sticking crystal layers
400 substrates, 401 through holes
410 core layers, 411 first surfaces, 412 second surfaces
420 first welding cover layers, 430 second welding cover layers
440 first line layers, 441 outer connection pads 442 connect finger
450 sticking crystal layer 460 second line layers
The thickness of T220 first welding cover layer
The thickness of T230 second welding cover layer
The thickness of T320 first welding cover layer
The thickness of T330 second welding cover layer
Embodiment
First specific embodiment
According to first specific embodiment of the present invention, specifically disclose a kind of substrate and chip encapsulation construction that reduces angularity.
See also shown in Figure 2ly, comprise core layer 210, first welding cover layer 220, second welding cover layer 230, first line layer 240 and sticking crystal layer 250 according to a kind of substrate 200 that reduces angularity of the present invention.This core layer 210 has first surface 211 and second surface 212.This core layer 210 is as the central core of this substrate 200, it generally is glass fiber-reinforced resin, the resin material of selecting for use can be epoxy resin (epoxyresin), pi (polyimide) resin, Bismaleimide Triazine (BT, bismaleimide triazine) resin, FR4 resin etc.This first welding cover layer 220 is formed at this first surface 211 of this core layer 210.This second welding cover layer 230 is formed at this second surface 212 of this core layer 210.These first welding cover layers 220 and second welding cover layer 230 promptly are " green lacquer " (Solder mask or the Solder Resist) that is commonly called as; it also is anti-welding lacquer; for ease of visual inspection; adding to the helpful viridine green of eyes in main lacquer; green lacquer is main constituent with epoxy resin and photosensitive resin; mainly coat printed circuit board surface, cover conductive trace with formation and make it avoid the protective layer of extraneous aqueous vapor, pollutant infringement.But these first welding cover layers 220, second welding cover layer 230 do not limit green, can be black, redness, blueness or other random color etc. yet.The coating method of general welding cover layer printing ink is broadly divided into: wire mark (screen printing), heavy curtain coating (curtaincoating), spraying coating (spray coating), roller coating (roller coating) etc.But pressing epoxy resin dry film or deposition ring epoxy resins liquid film utilize coating and hardening process to form this first welding cover layer 220 and this second welding cover layer 230.Particularly, this first welding cover layer 220 has thickness inequality with this second welding cover layer 230.Particularly, this first welding cover layer 220 can be not less than 10 microns (μ m) with the thickness difference of this second welding cover layer 230, second welding cover layer 230 that can reduce the upper strata and the warping phenomenon of first welding cover layer 220 of lower floor because of different these substrate 200 bendings that produce of thermal stress (theraml stress).
In addition, this first line layer 240 is formed at this first surface 211 of this core layer 210, and covers this first line layer 240 with this first welding cover layer 220.This first line layer 240 can be copper (copper) layer, make the copper layer through exposure (exposing), develop (developing), etching technologies such as (etching) and patterning (patterning) to be to form multi-conducting trace (conductive trace).Particularly, in the present embodiment, this substrate 200 also can include second line layer 260, and it is formed at this second surface 212 of this core layer 210, and with these second welding cover layer, 230 these second line layers 260 of covering, so that this substrate 200 is lamination (laminate) formula.
Should be covered on this second welding cover layer 230 sticking crystal layer 250 parts, can be used as the usefulness of follow-up stickup chip.Preferably, the material of this sticking crystal layer 250 can be selected from the sticking brilliant material that B rank colloid or other can multistage curing.In different embodiment, the material of this sticking crystal layer 250 also can be selected the adhesive tape on non-B rank or viscous gel etc. for use.Can be pre-formed on this substrate 200 before chip package process or in the operation in early stage.
In general, at influence such as the coefficient of expansion of chip, substrate, soldered ball, sticking crystal layer, adhesive body etc., can obtain the thermal stress balance by the thickness difference of this first welding cover layer 220 and this second welding cover layer 230 to the substrate warp degree.As shown in Figure 2, in the present embodiment, this sticking crystal layer 250 has the thermal coefficient of expansion roughly the same with this first welding cover layer 220.Preferably, as shown in Figure 2, and the thickness T 220 of this first welding cover layer 220 is greater than the thickness T 230 of this second welding cover layer 230.As shown in Figure 3, because this first welding cover layer 220 is formed at the substrate composition surface of these external terminals 25, so the thickness adjustment of this first welding cover layer 220 can not influence the integral thickness of final chip encapsulation construction.In addition, about the determining method of this first welding cover layer 220, can be CAE software by ANSYS software with the thickness difference of this second welding cover layer 230, utilize finite element method (FEM) (FEM, Finite element method) to find the solution.Suitably adjust the thickness and the thermal coefficient of expansion of this sticking crystal layer 250, this first welding cover layer 220 and this second welding cover layer 230, make these substrate 200 upper and lower surfaces produce the thermal stress of contending with each other, to be suppressed at substrate 200 warpages in the chip package process.And in general, the thermal coefficient of expansion of welding cover layer is 60～160ppm/ ℃, and the thermal coefficient of expansion of core layer is 16ppm/ ℃, and the thermal coefficient of expansion of line layer is 16ppm/ ℃.
Particularly, this first line layer 240 can be connected with two or more outer connection pads 241, and this first welding cover layer 220 and this second welding cover layer 230 have a plurality of openings and connect finger 261 with two or more that expose that these outer connection pads 241 of forming on this first line layer 240 and this second line layer 260 form.
When carrying out follow-up chip package process, as shown in Figure 3, semiconductor chip 21 is by the stickup of this sticking crystal layer 250 and stick on the upper surface of second welding cover layer 230, the active surface of this chip 21 has two or more weld pads 21A, can utilize two or more these weld pads 21A that electrically connect element 23 these chips 21 of connection to refer to 261 to be electrically connected to first line layer 240 of this substrate 200, make this chip 21 and these substrate 200 electrical interconnects to connecing of second line layer 260.In the present embodiment, these electrically connect the bonding wire that element 23 forms for routing.Afterwards; adhesive body 24 is with pressing mold or some glue mode; be arranged at the upper surface of second welding cover layer 230 of this substrate 200; electrically connect element 23 to seal this chip 21 with these; suitable protection is provided; this chip 21 is arranged at these outer connection pads 241 of this first line layer 240 again with two or more external terminals 25, so that must be realized electrical connection with external printed circuit board (PCB, printed circuitboard).In this example, these external terminals 25 comprise two or more soldered balls.
Carrying out under substrate baking, adhesive body curing or the subsequent thermal cycle operation equitemperature changing environment, because the thickness T 220 of this first welding cover layer 220 is greater than the thickness T 230 of this second welding cover layer 230, and should sticking crystal layer 250 have the thermal coefficient of expansion roughly the same with this first welding cover layer 220, no matter be at this substrate 200 states of cooling or heated condition, the thickness difference of this first welding cover layer 220 provides the warpage correction, whereby, can make this substrate 200 keep dimensionally stables, not temperature influence and avoid producing warpage.
Second specific embodiment
Second specific embodiment of the present invention discloses the another kind of substrate that reduces angularity.See also shown in Figure 4ly, this substrate 300 mainly comprises core layer 310, first welding cover layer 320, second welding cover layer 330, first line layer 340 and sticking crystal layer 350.This core layer 310 has first surface 311 and second surface 312.This first welding cover layer 320 is formed at this first surface 311 of this core layer 310.This second welding cover layer 330 is formed at this second surface 312 of this core layer 310.This first line layer 340 is formed at this first surface 311 of this core layer 310, and covers this first line layer 340 with this first welding cover layer 320.This first line layer 340 is connected with two or more outer connection pads 341, with external electric connection.Should be covered on this second welding cover layer 330 sticking crystal layer 350 parts.Wherein, this first welding cover layer 320 has thickness inequality with this second welding cover layer 330, and as shown in Figure 4, in the present embodiment, the thickness T 320 of this first welding cover layer 320 is thinner than the thickness T 330 of this second welding cover layer 330.Usually this sticking crystal layer 350 can have the thermal coefficient of expansion less than this first welding cover layer 320.Because this substrate 300 only has this first line layer 340 of one deck,, come the thermal stress of these substrate 300 upper and lower surfaces of balance, to suppress this substrate 300 generation warpages so be located at the thickness of second welding cover layer 330 of this second surface 312 by thickening.
The 3rd specific embodiment
The 3rd specific embodiment of the present invention discloses another kind of substrate and the chip encapsulation construction that reduces angularity.See also shown in Figure 5ly, this substrate 400 mainly comprises core layer 410, first welding cover layer 420, second welding cover layer 430, first line layer 440, sticking crystal layer 450 and second line layer 460.This core layer 410 has first surface 411 and second surface 412.This first welding cover layer 420 is formed at this first surface 411 of this core layer 410.This second welding cover layer 430 is formed at this second surface 412 of this core layer 410.This first line layer 440 is formed at this first surface 411 of this core layer 410, and covers this first line layer 440 with this first welding cover layer 420.Should be covered on this second welding cover layer 430 sticking crystal layer 450 parts.Wherein, this first welding cover layer 420 has thickness inequality with this second welding cover layer 430, as shown in Figure 5, in the present embodiment, this substrate 400 can have through hole 401, it runs through this first welding cover layer 420, this first line layer 440, this core layer 410, this second line layer 460 and this second welding cover layer 430, passes through for routing.Generally speaking, this through hole 401 can be positioned at center or other position of this substrate 400.As shown in Figure 5, this first welding cover layer 420 is thicker than this second welding cover layer 430, and should sticking crystal layer 450 have the thermal coefficient of expansion roughly the same, with second welding cover layer 430 that reduces the upper strata warping phenomenon with first welding cover layer, 420 these substrate 400 bendings of generation of lower floor because thermal stress (theraml stress) is different with this first welding cover layer 420.
Particularly, this first line layer 440 can be connected with two or more outer connection pads 441, and this first welding cover layer 420 has a plurality of openings and connects finger 442 to expose these outer connection pads 441 that form on this first line layer 440 with two or more.
When carrying out follow-up chip package process, as shown in Figure 6, semiconductor chip 41 is by the stickup of this sticking crystal layer 450 and be arranged at the upper surface of this second welding cover layer 430, the active surface of this chip 41 has two or more weld pads 41A, can utilize two or more to electrically connect elements 43 and connect these weld pads 41A by this through hole 401 and connect to these of this substrate 400 and refer to 442, make this chip 41 and these substrate 400 electrical interconnects.In the present embodiment, these electrically connect the bonding wire that element 43 forms for routing.Afterwards, carry out the sealing operation, adhesive body 44 is formed at top, the local below and this through hole 401 of this substrate 400, to seal this chip 41, this through hole 401 and these electric connection elements 43, provides suitable protection.Again with two or more external terminals 45 as soldered ball, be arranged at this first surface 411 of this substrate 400, so that this chip 41 must be realized electrical connection with external printed circuit board (PCB, printed circuit board).
Under the curing of the prebake conditions of carrying out on the substrate sticking crystal layer, adhesive body or subsequent thermal cycle operation or the like variations in temperature environment, because the thickness difference of this first welding cover layer 420 and this second welding cover layer 430, whereby, can make this second welding cover layer 430, this first line layer 440 keep stable with this second line layer 460, not affected by environment and produce warpage, particularly be applicable to the lamination type substrate of asymmetric layer.
Generally speaking, the present invention is laid in the upper and lower surface of substrate by the welding cover layer of different-thickness, produces the thermal stress of contending with each other under variations in temperature, to suppress substrate warp in chip package process.Therefore, this substrate can be made at lower cost, and can not need to increase additional stiffening elements and reach in chip package process the effect that suppresses substrate warp.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction, and the technical solution of the present invention scope is when being as the criterion according to appended claims.Any those of ordinary skill in the art can utilize the technology contents of above-mentioned announcement to make a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention,, all still belong in the scope of technical solution of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (8)
1. a substrate that reduces angularity is characterized in that, comprises:
Core layer has first surface and second surface;
First welding cover layer is formed at this first surface of this core layer;
Second welding cover layer is formed at this second surface of this core layer;
First line layer is formed at this first surface of this core layer, and covers this first line layer with this first welding cover layer; And
Sticking crystal layer, the part is covered on this second welding cover layer;
This first welding cover layer and this second welding cover layer have thickness inequality, and to reduce the angularity of this substrate, this first welding cover layer is thinner than this second welding cover layer, and this sticking crystal layer has the thermal coefficient of expansion less than this first welding cover layer.
2. the substrate of reduction angularity as claimed in claim 1 is characterized in that, the thickness difference of described first welding cover layer and this second welding cover layer is not less than 10 microns.
3. the substrate of reduction angularity as claimed in claim 1 is characterized in that, also includes second line layer, and it is formed at the described second surface of described core layer, and covers this second line layer with described second welding cover layer, so that this substrate is a lamination type.
4. the substrate of reduction angularity as claimed in claim 1 is characterized in that, described first line layer is connected with two or more outer connection pads.
5. chip encapsulation construction with the substrate that reduces angularity is characterized in that it comprises:
Substrate, this substrate comprises:
Core layer has first surface and second surface;
First welding cover layer is formed at this first surface of this core layer;
Second welding cover layer is formed at this second surface of this core layer;
First line layer is formed at this first surface of this core layer and covers this first line layer with this first welding cover layer; And
Sticking crystal layer, the part is covered on this second welding cover layer;
This first welding cover layer and this second welding cover layer have thickness inequality, and to reduce the angularity of this substrate, this first welding cover layer is thinner than this second welding cover layer, and this sticking crystal layer has the thermal coefficient of expansion less than this first welding cover layer;
Chip utilizes this sticking crystal layer adhesion and is arranged at the upper surface of second welding cover layer;
Two or more electrically connect element, electrically connect first line layer of this chip to this substrate; And
Adhesive body is arranged on the upper surface of second welding cover layer of this substrate, seals this chip.
6. the chip encapsulation construction with the substrate that reduces angularity as claimed in claim 5 is characterized in that it has through hole, and this through hole runs through described first welding cover layer, described first line layer, described core layer and described second welding cover layer.
7. the chip encapsulation construction with the substrate that reduces angularity as claimed in claim 5 is characterized in that described first line layer is connected with two or more outer connection pads.
8. the chip encapsulation construction with the substrate that reduces angularity as claimed in claim 7 is characterized in that, also includes two or more external terminals, is engaged in described outer connection pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN200810089751XA CN101556947B (en) | 2008-04-10 | 2008-04-10 | Basal plate for reducing warpage degree and chip packaging structure provided with same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810089751XA CN101556947B (en) | 2008-04-10 | 2008-04-10 | Basal plate for reducing warpage degree and chip packaging structure provided with same |
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| Publication Number | Publication Date |
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| CN101556947A CN101556947A (en) | 2009-10-14 |
| CN101556947B true CN101556947B (en) | 2011-04-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200810089751XA Active CN101556947B (en) | 2008-04-10 | 2008-04-10 | Basal plate for reducing warpage degree and chip packaging structure provided with same |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US11031353B2 (en) | 2019-08-23 | 2021-06-08 | Micron Technology, Inc. | Warpage control in microelectronic packages, and related assemblies and methods |
| CN112309875A (en) * | 2020-11-02 | 2021-02-02 | 南方电网科学研究院有限责任公司 | Chip packaging method |
| CN116887531B (en) * | 2023-07-28 | 2024-02-06 | 湖南中科存储科技有限公司 | Method for implementing temperature control hot-press shaping on sealing glue PCB substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306682B1 (en) * | 1999-05-31 | 2001-10-23 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a ball grid array integrated circuit package having an encapsulating body |
| CN1812089A (en) * | 2004-12-21 | 2006-08-02 | 精工爱普生株式会社 | Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument |
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- 2008-04-10 CN CN200810089751XA patent/CN101556947B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6306682B1 (en) * | 1999-05-31 | 2001-10-23 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a ball grid array integrated circuit package having an encapsulating body |
| CN1812089A (en) * | 2004-12-21 | 2006-08-02 | 精工爱普生株式会社 | Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument |
Non-Patent Citations (1)
| Title |
|---|
| JP平2-10859A 1990.01.16 |
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