CN101556297A - Capacitance value measuring circuit and measuring method thereof - Google Patents

Abstract

The invention provides a capacitance value measuring circuit and capacitance value measuring method thereof. The capacitance value measuring method comprises the following steps: firstly, responding to the first group of clock pulse signals, the voltage on at least one end of a capacitor to be measured is switched, a level of integrating voltage is regulated into an ending level from an original level in the first integration period, and the capacitance value of the capacitor to be measured is relevant to the difference value between the original level and the ending level; secondly, responding to the second group of clock pulse signals, the level of the integrating voltage is regulated into the original level from the ending level in the second integration period; and thirdly, the capacitance value of the capacitor to be measured is obtained by an operation way according to the first and the second integration periods and known characteristic values. The capacitance value measuring circuit has the advantages that the capacitors to be measured with different number ranges can be elastically measured, another design selection of the capacitance value measuring circuit can be effectively provided, and the measurement of the capacitance value of the capacitor to be measured can be accurately carried out.

Description

Capacitance value measuring circuit and method thereof

Technical field

The present invention relates to a kind of capacitance value measuring circuit (capacitance evaluation circuit, evaluationcircuit for capacitance), and be particularly related to a kind ofly, obtain the capacitance value measuring circuit of the capacitance of testing capacitance by observing the reaction time of charge and discharge when testing capacitance carried out the charge and discharge operation.

Background technology

Traditionally, coming with mechanical switch mostly is that the user realizes the control interface device.Because conventional mechanical switch needs directly to contact with the user, just can operate in response to user's steering order, traditional mechanical formula device is recurring structure corrupted in user's operating process easily.

In the epoch now that development in science and technology is maked rapid progress, there is the touch switch.Traditionally, the touch switch for example is a capacitance-type switch, and its capacitance by the induction testing capacitance is controlled with user's whether approaching variation.Yet, how to design the capacitance value measuring circuit that can measure the capacitance variation of testing capacitance effectively, be one of direction of constantly endeavouring of industry to promote capacitance-type switch.

Summary of the invention

The present invention relates to a kind of capacitance value measuring circuit, than traditional capacitance value measuring circuit, the capacitance value measuring circuit of present embodiment can be carried out capacitance value measuring to testing capacitance more accurately.

According to the present invention proposes a kind of capacitance value measuring circuit, comprise integrator circuit, first, second control circuit and processor circuit.Integrator circuit has input end and output terminal, has integral voltage on the output terminal, and integrator circuit is in order to be set at the start bit standard with integral voltage in control signal is during voltage is set.First control circuit comprises first output terminal and testing capacitance, first output terminal is electrically connected at input end, first control circuit is in order to the voltage at least one end that switches testing capacitance in response to first group of clock signal, and an end of testing capacitance and first input end are electrically connected, carry out voltage integrating meter with control integrator circuit in during first integral, integral voltage is adjusted into the stop bit standard from the start bit standard, and the capacitance of testing capacitance is relevant with the accurate difference with the start bit standard of stop bit.Second control circuit comprises second output terminal and passive device, and passive device has the known features value, and second output terminal is electrically connected at input end.Second control circuit is in order to the voltage at least one end that switches passive device in response to second group of clock signal, and an end of passive device and second input end are electrically connected, carry out voltage integrating meter with control integrator circuit in during second integral, accurate self termination position, the position standard of integral voltage is adjusted into the start bit standard.Processor circuit drives first and this second control circuit in order to first group and second group of clock signal to be provided, and in order to calculate the capacitance of testing capacitance according to the time span between first and second integration period and known features value.

According to capacitance value measuring circuit of the present invention, wherein this first control circuit also comprises: first on-off circuit, comprise first end, second end and the 3rd end, be coupled to respectively this testing capacitance first end, be coupled to this input end and receive first voltage, first end that this first on-off circuit makes this testing capacitance respectively in order to first state and second state in response to this first group of clock signal is coupled to this input end and makes first termination of this testing capacitance receive this first voltage.

According to capacitance value measuring circuit of the present invention, wherein this passive device is a known capacitance, this second control circuit also comprises: the second switch circuit, comprise first end, second end and the 3rd end, be coupled to respectively this known capacitance first end, be coupled to this input end and receive second voltage, first end that this second switch circuit makes this known capacitance respectively in order to first state and second state in response to this second group of clock signal is coupled to this input end and makes first termination of this known capacitance receive this second voltage.

According to capacitance value measuring circuit of the present invention, wherein this second control circuit also comprises: the 3rd on-off circuit, comprise first end, second end and the 3rd end, be coupled to respectively this known capacitance second end, receive this second voltage and receive tertiary voltage, the 3rd on-off circuit provides this second voltage and this tertiary voltage second end to this known capacitance respectively in order to first state that responds this second group of clock signal and second state; Wherein the position standard of this second voltage is substantially equal to this start bit standard.

According to capacitance value measuring circuit of the present invention, wherein this first control circuit also comprises: the 4th on-off circuit, comprise first end, second end and the 3rd end, be coupled to respectively this testing capacitance second end, receive this first voltage and receive the 4th voltage, the 4th on-off circuit is in order to provide this first voltage and the 4th voltage second end to this testing capacitance respectively in response to first state of this first group of clock signal and second state; Wherein the position standard of this first voltage is substantially equal to this start bit standard.

According to capacitance value measuring circuit of the present invention, wherein this passive device is a known resistance, this second control circuit also comprises: the second switch circuit, comprise first end and second end, be coupled to first end of this known resistance respectively and be coupled to this input end, first end that first end that this second switch circuit makes this known resistance respectively in order to first state and second state in response to this second group of clock signal is coupled to this input end and makes this known resistance is suspension joint basically.

According to capacitance value measuring circuit of the present invention, wherein this first group and this second group of clock signal have the substantially the same clock pulse cycle, this first and this second integral during length comprise N this clock pulse cycle and M this clock pulse cycle basically respectively, this processor circuit calculates the capacitance of this testing capacitance according to the ratio of numerical value of N and M, and numerical value of N and M are the natural number greater than 1.

According to capacitance value measuring circuit of the present invention, wherein this processor circuit comprises: pierce circuit, produce the 3rd clock signal and the 4th clock signal in order to vibration, and the 3rd and the 4th clock signal is for anti-phase basically; First logical circuit produces this control signal during setting at this voltage; Second logical circuit in order to producing this first group of clock signal in during this first integral, and produces this second group of clock signal in order to first time point after during this first integral; Comparator circuit, the height of and this start bit standard accurate in order to the position of this integral voltage relatively, and in that the position of this integral voltage is accurate when satisfying second time point of critical condition, the trigger action incident; Counter circuit, in order to light the execution counting operation certainly at this first o'clock, make counts increase progressively 1 every the clock pulse cycle of this second group of clock signal from zero beginning, this counter circuit is also in order to stop counting operation in response to this Action Events at this second time point, to count to get a numerical value M, M is the natural number greater than 1; And fasten lock circuit, in order to write down this numerical value M in response to this Action Events; Wherein this first and this second time point define during this second integral, this processor circuit obtained during this second integral according to clock pulse cycle of this numerical value M and this second group of clock signal.

According to capacitance value measuring circuit of the present invention, wherein this integrator circuit comprises: operational amplifier, positive input terminal receives this start bit standard, negative input end be coupled to this first and this input end of this second control circuit, output terminal is this output terminal that is coupled to this processor circuit; Integrating capacitor, the two ends of this integrating capacitor are coupled to negative input end and this output terminal of this operational amplifier respectively; And the 5th on-off circuit, first end and second end are coupled to negative input end and this output terminal of this operational amplifier respectively, the 5th on-off circuit is in order in response to this control signal conducting, connect negative input end and this output terminal of this operational amplifier with short circuit, be this start bit standard with the negative input end of setting this operational amplifier and the voltage of this output terminal.

According to capacitance value measuring circuit of the present invention, wherein this integrator circuit comprises: the 5th on-off circuit, first end and second end receive reference voltage respectively and are coupled to this output terminal, and the position standard of this reference voltage is substantially equal to this start bit standard; And integrating capacitor, first end and second end are coupled to this output terminal respectively and receive first voltage.

According to capacitance value measuring circuit of the present invention, wherein this second control circuit is also in order in response to the 5th group of clock signal and the 6th group of clock signal, this integrator circuit of control carries out voltage integrating meter during third integral and between the 4th integration period respectively, being adjusted into this stop bit standard from this start bit standard with the position of this integral voltage is accurate respectively, and be adjusted into this start bit standard from this stop bit standard with the position of this integral voltage is accurate; Wherein this processor circuit is proofreaied and correct in order to come that according to the time difference between the 3rd and the 4th integration period this capacitance value measuring circuit is carried out deviation voltage.

According to capacitance value measuring circuit of the present invention, wherein this passive device is a known capacitance, this second control circuit also comprises: the 6th on-off circuit, comprise first end, second end, the 3rd end and the 4th end, be coupled to first end of this known capacitance respectively, be coupled to this input end, receive first voltage and receive second voltage, first end that the 6th on-off circuit makes this known capacitance respectively in order to first state and second state in response to the 5th group of clock signal is coupled to this input end and makes first termination of this known capacitance receive this first voltage, and first end that the 6th on-off circuit also makes this known capacitance respectively in order to first state and second state in response to the 6th group of clock signal is coupled to this input end and makes first termination of this known capacitance receive this second voltage.

According to capacitance value measuring circuit of the present invention, wherein this passive device is a known capacitance, this second control circuit also comprises: minion is closed circuit, comprise first end, second end and the 3rd end, be coupled to first end of this known capacitance respectively, be coupled to this input end and receive tertiary voltage, this minion is closed circuit makes first end of this known capacitance be coupled to this input end in order to first state in response to the 5th group and the 6th group clock signal, and makes first termination of this known capacitance receive this tertiary voltage in order to second state in response to the 5th group and the 6th group clock signal; And octavo is closed circuit, comprise first end, second end, the 3rd end and the 4th end, be coupled to respectively this known capacitance second end, receive this tertiary voltage, receive first voltage and receive second voltage, second termination that this octavo pass circuit makes this known capacitance respectively in order to first state and second state in response to the 5th group of clock signal is received this tertiary voltage and is received this first voltage, and receives this tertiary voltage and receive this second voltage in order to second termination that first state and second state in response to the 6th group of clock signal make this known capacitance respectively.

According to capacitance value measuring circuit of the present invention, wherein the 5th group and the 6th group of clock signal have the substantially the same clock pulse cycle, length between the 3rd and the 4th integration period is respectively J this clock pulse cycle and K this clock pulse cycle basically, this processor circuit obtains this time difference according to difference and this clock pulse cycle of numerical value J and K, and numerical value J and K are the natural number greater than 1.

Comprise integrator circuit, first, second control circuit and processor circuit according to the invention allows for a kind of capacitance value measuring circuit.Integrator circuit has input end and output terminal, has integral voltage on the output terminal, and integrator circuit is in order to be set at the start bit standard with integral voltage in control signal is during voltage is set.First control circuit comprises first output terminal and passive device, and passive device has the known features value, and first output terminal is electrically connected at input end.First control circuit is in order to the voltage at least one end that switches passive device in response to first group of clock signal, and an end of passive device and first input end are electrically connected, carry out voltage integrating meter with control integrator circuit in during first integral, to be adjusted into the stop bit standard from the start bit standard with the position of integral voltage is accurate.Second control circuit comprises second output terminal and testing capacitance, second output terminal is electrically connected at input end, second control circuit is in order to the voltage at least one end that switches testing capacitance in response to second group of clock signal, and an end of testing capacitance and second input end are electrically connected, carry out voltage integrating meter with control integrator circuit in during second integral, integral voltage self termination position standard is adjusted into the start bit standard, and the capacitance of testing capacitance is relevant with the difference that stops with this start bit standard.Processor circuit drives first and this second control circuit in order to first group and second group of clock signal to be provided, and in order to calculate the capacitance of testing capacitance according to the time span between first and second integration period and known features value.

According to the invention allows for a kind of capacitance value measuring method, be applied to capacitance value measuring circuit, capacitance value measuring circuit comprises integrator circuit, and the output terminal of integrator circuit has integral voltage, and testing capacitance is electrically connected to the input end of integrator.Capacitance value measuring method comprises the following steps: that (a) is at first in response to the voltage at least one end of first group of clock signal switching testing capacitance, to be adjusted into the stop bit standard from the start bit standard with the position of integral voltage is accurate in during first integral, the capacitance of testing capacitance difference accurate with stop bit and the start bit standard is relevant; (b) then in response to during second group of clock signal is during second integral accurate self termination position, the position standard of integral voltage being adjusted into the start bit standard; And (c) afterwards according to reaching the capacitance that the computing of known features value obtains testing capacitance between first, second integration period.

According to capacitance value measuring method of the present invention, (a) also comprises before in step: the position standard with this integral voltage in (d) during voltage is set is set to this start bit standard.

According to capacitance value measuring method of the present invention, (a) also comprises before in step: (e) switch voltage at least one end of known capacitance in response to the 3rd group of clock signal, to be adjusted into this stop bit standard from this start bit standard with the position of this integral voltage is accurate in during third integral; (f) switch voltage on this at least one end of this known capacitance in response to the 4th group of clock signal, to be adjusted into this start bit standard from this stop bit standard with the position of this integral voltage is accurate between the 4th integration period; And (g) obtain the offset correction value according to the difference computing between the 3rd and the 4th integration period; Wherein step (c) according to this first, during this second integral and this offset correction value computing obtain the capacitance of this testing capacitance.

According to capacitance value measuring method of the present invention, wherein this first and this second integral during correspond to N clock pulse cycle and M clock pulse cycle respectively, step (c) comprising: the capacitance that calculates this testing capacitance according to capacitance, numerical value of N and the M of this known capacitance.

According to capacitance value measuring method of the present invention, wherein step (c) comprising: revise numerical value M according to this offset correction value; Reach the capacitance that obtains this testing capacitance according to capacitance, numerical value of N and the revised numerical value M computing of this known capacitance.

Proposed a kind of capacitance value measuring method again according to the present invention, be applied to capacitance value measuring circuit, capacitance value measuring circuit comprises integrator circuit, and the output terminal of integrator circuit has integral voltage, and testing capacitance is electrically connected to the input end of integrator.Capacitance value measuring method comprises the following steps: that (a) at first is adjusted into the stop bit standard with integral voltage from the start bit standard in first group of clock signal is during first integral; (b) then in response to the voltage at least one end of second group of clock signal switching testing capacitance, accurate self termination position, the position standard of integral voltage is adjusted into the start bit standard in during second integral, the capacitance of testing capacitance difference accurate with stop bit and the start bit standard is relevant; And (c) afterwards according to reaching the capacitance that the computing of known features value obtains testing capacitance between first, second integration period.

According to capacitance value measuring method of the present invention, (a) also comprises before in step: the position standard with this integral voltage in (d) during voltage is set is set to this start bit standard.

According to capacitance value measuring method of the present invention, (a) also comprises before in step: (e) switch voltage at least one end of known capacitance in response to the 3rd group of clock signal, to be adjusted into this stop bit standard from this start bit standard with the position of this integral voltage is accurate in during third integral; (f) switch voltage on this at least one end of this known capacitance in response to the 4th group of clock signal, to be adjusted into this start bit standard from this stop bit standard with the position of this integral voltage is accurate between the 4th integration period; And (g) obtain the offset correction value according to the difference computing between the 3rd and the 4th integration period.

According to capacitance value measuring method of the present invention, wherein this first and this second integral during correspond to N clock pulse cycle and M clock pulse cycle respectively, step (c) comprising: the capacitance that calculates this testing capacitance according to capacitance, numerical value of N and the M of this known capacitance.

According to capacitance value measuring method of the present invention, wherein step (c) comprising: revise numerical value M according to this offset correction value; Reach the capacitance that obtains this testing capacitance according to capacitance, numerical value of N and the revised numerical value M computing of this known capacitance.

For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and in conjunction with appended accompanying drawing, be described in detail below.

Description of drawings

Fig. 1 shows the calcspar of the capacitance value measuring circuit of first embodiment of the invention.

Fig. 2 shows the coherent signal sequential chart of the capacitance value measuring circuit 10 of Fig. 1.

Fig. 3 shows the detailed block diagram of the processor circuit 18 of Fig. 1.

Fig. 4 shows the detailed block diagram of the logical block 18a2 of Fig. 3.

Fig. 5 shows another coherent signal sequential chart of the capacitance value measuring circuit 10 of Fig. 1.

Fig. 6 shows the calcspar according to the capacitance value measuring circuit of second embodiment of the invention.

Fig. 7 shows the calcspar according to the capacitance value measuring circuit of third embodiment of the invention.

Fig. 8 shows the coherent signal sequential chart of the capacitance value measuring circuit 30 of Fig. 7.

Fig. 9 shows the calcspar according to the capacitance value measuring circuit of fourth embodiment of the invention.

Figure 10 shows the coherent signal sequential chart of the capacitance value measuring circuit of Fig. 9.

Figure 11 shows the calcspar according to the capacitance value measuring circuit of fifth embodiment of the invention.

Figure 12 shows the coherent signal sequential chart of the capacitance value measuring circuit of Figure 11.

Figure 13 shows another calcspar according to the capacitance value measuring circuit of fifth embodiment of the invention.

Embodiment

The capacitance value measuring circuit of present embodiment comes the voltage on the node is charged and discharge operation with testing capacitance and known capacitance respectively, and the ratio of the running time that corresponds to charging operations and discharge operation calculates the capacitance of testing capacitance.

First embodiment

Please refer to Fig. 1, it shows the calcspar of the capacitance value measuring circuit of first embodiment of the invention.Capacitance value measuring circuit 10 comprises control circuit 12,14, integrator circuit 16 and processor circuit 18. Control circuit 12 and 14 is set at the integral voltage Vx on the output terminal ndo of integrator circuit 16 the stop bit standard and its self termination position standard is set at the start bit standard from the start bit standard in order to control integrator circuit 16 respectively.In the present embodiment, be that example explains with the accurate situation that is higher than the start bit standard in the position of stop bit standard.Processor circuit 18 is carried out aforementioned operation in order to the signal Drive and Control Circuit 12,14 and the integrator circuit 16 that produce correspondence, and in order to carry out the computing of the capacitance of testing capacitance Cx in response to the accurate variation in the position of integral voltage Vx.Next, the operation to each element in the capacitance value measuring circuit 10 is described further.

Integrator circuit 16 comprises input end ndi, output terminal ndo, switch S c, integrating capacitor Ci and operational amplifier (Operational Amplifier) OP1.The two ends cross-over connection of the two ends of switch S c and integrating capacitor Ci is in negative input end and the output terminal ndo of operational amplifier OP1, the be enabled control signal CS1 conducting of (enabling) of switch S c.The positive input terminal of operational amplifier OP1 receives reference voltage Vr.Wherein, reference voltage Vr is the ceiling voltage VDD of capacitance value measuring circuit 10 of present embodiment and any specific reference voltage between ground voltage, and for instance, reference voltage Vr is substantially equal to voltage VDD/2.

Control circuit 12 comprises output terminal OE1, on-off circuit SW1 and testing capacitance Cx, and it is coupled to node nd1.On-off circuit SW1 comprises switch S a1 and Sa2, and the one end is coupled to node nd1, and the other end receives voltage Vf1 respectively and is coupled to the negative input end of operational amplifier OP1.Clock signal CK_a1 that switch S a1 and Sa2 are enabled respectively and CK_a2 conducting.The two ends of testing capacitance Cx are coupled to node nd1 respectively and receive voltage Vf1.Voltage Vf1 for example is a ground voltage.

Control circuit 14 comprises output terminal OE2, on-off circuit SW2 and known capacitance Cc, and it is coupled to node nd2.On-off circuit SW2 comprises switch Sb 1 and Sb2, and the one end is coupled to node nd2, and the other end receives voltage Vf2 respectively and is coupled to the negative input end of operational amplifier OP1.Clock signal CK_b1 that switch Sb 1 and Sb2 are enabled respectively and CK_b2 conducting.The two ends of known capacitance Cc are coupled to node nd2 respectively and receive voltage Vf1.Voltage Vf2 for example is ceiling voltage VDD.

Please refer to Fig. 2, it shows the coherent signal sequential chart of the capacitance value measuring circuit 10 of Fig. 1.The capacitance value measuring circuit 10 of present embodiment for example comprise voltage set during three operating periods such as TP_IT1 and TP_IT2 between TP_PS, integration period, processor circuit 18 is in order to produce corresponding control signal in the operating period of correspondence, so that capacitance value measuring circuit 10 is carried out sequential control.

In more detail, among the TP_PS, processor circuit 18 activation control signal CS1 are with actuating switch Sc during voltage is set.So, the negative input end of operational amplifier OP1 and output terminal ndo are electrically connected to each other, making operational amplifier OP1 biased basically is a unity gain buffer (Unit Gain Buffer), and the positive input terminal of operational amplifier OP1 and output terminal ndo have the voltage (=reference voltage Vr) that equates basically.In addition, the positive-negative input end of operational amplifier OP1 is the characteristic of imaginary short each other, and so, among the TP_PS, the positive and negative input end of operational amplifier OP1 and the position standard on the output terminal ndo all are set to reference voltage Vr during voltage is set.Among the TP_PS, clock signal CK_a1, CK_a2, CK_b1 and CK_b2 are disabled constantly, make switch S a1, Sa2, Sb1 and Sb2 for closing during voltage is set.For instance, the activation position standard of control signal CS1 for example is a high levels; The disabled position standard of clock signal CK_a1, CK_a2, CK_b1 and CK_b2 for example is a low level.

Among the TP_IT1, processor circuit 18 provides clock signal CK_a1 and CK_a2 between integration period, and the position quasi periodic ground of clock signal CK_a1 and CK_a2 switches between high levels and low level, with actuating switch Sa1 and Sa2 accordingly.

For instance, among the TP1, switch S a1 and Sa2 are respectively conducting and reach to closing during first child-operation.So, the voltage of node nd1 is set to ground voltage, makes the cross-pressure at testing capacitance Cx two ends be essentially 0, and the cross-pressure at integrating circuit Ci two ends also is 0.Among the TP2, switch S a1 and Sa2 are respectively and close and conducting during second child-operation, and node nd1 is coupled to the negative input end of operational amplifier OP1.Because the node nd1 (promptly being the negative input end of operational amplifier OP1) that testing capacitance Cx and integrating capacitor Ci couple mutually is a suspension joint (Floating), so the total electrical charge that testing capacitance Cx and integrating capacitor Ci store among the TP1 during first child-operation is substantially equal to the total electrical charge that it stores among TP2 during second child-operation, promptly be to satisfy equation:

Cx×(Vf1-Vf1)+Ci×[Vr-Vx(t0)]＝Cx×Vr+Ci×[Vr-Vx(t1)]

Wherein the levoform of aforesaid equation is the total electrical charge that testing capacitance Cx and integrating capacitor Ci store among the TP1 during first child-operation, and right formula be the total electrical charge of testing capacitance Cx and integrating capacitor Ci storage among the TP2 during second child-operation.Voltage Vx (t0) is the start bit standard of integral voltage Vx, and voltage Vx (t1) is integral voltage Vx through the voltage after integration operation.Because the integral voltage Vx (t0) of TP1 is substantially equal to reference voltage Vr during first child-operation, promptly is to be substantially equal to voltage VDD/2, can push away according to aforesaid equation:

$\mathrm{Vx}\left(t1\right)=\frac{\mathrm{Cx}+\mathrm{Ci}}{\mathrm{Ci}}\×\mathrm{Vr}=\frac{\mathrm{VDD}\×(\mathrm{Cx}+\mathrm{Ci})}{2\×\mathrm{Ci}}$

$\mathrm{\&Delta;<figure-callout\; id="1"\; label="V"\; filenames="A20081008989200351.png,A20081008989200361.png"\; state="\{\{state\}\}">V</figure-callout>}1=\mathrm{Vx}\left(t1\right)-\mathrm{Vx}\left(t0\right)=\frac{\mathrm{VDD}\&times;(\mathrm{Cx}+\mathrm{Ci})}{2\&times;\mathrm{Ci}}-\mathrm{Vr}=\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cx"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cx</figure-callout>}}{2\&times;\mathrm{Ci}}$

According to above-mentioned derivation as can be known, through after integration operation, the integral voltage Vx difference voltage Δ V1 that rises basically.TP_IT1 for example comprises the cycle (promptly be during N first child-operation and N second child-operation during) of N clock signal CK_a1 between the integration period of present embodiment, in the cycle of each clock signal CK_a1, control circuit 12 is carried out similar integration operation to integrator circuit 16, and N is a natural number.So, by carrying out above-mentioned integration operation repeatedly N time, integral voltage Vx is risen to the accurate Vx_Tr of stop bit from its start bit standard (position that equals reference voltage Vr is accurate):

$\mathrm{Vx}\_\mathrm{Tr}=\mathrm{Vr}+N\&times;\mathrm{\&Delta;<figure-callout\; id="1"\; label="V"\; filenames="A20081008989200351.png,A20081008989200361.png"\; state="\{\{state\}\}">V</figure-callout>}1=\mathrm{Vr}+N\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cx"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cx</figure-callout>}}{2\&times;\mathrm{Ci}}$

Among the TP_IT2, processor circuit 18 provides clock signal CK_b1 and CK_b2 between integration period, comes Drive and Control Circuit 14 to carry out the operation close with control circuit 12, so that integral voltage Vx is carried out integration.Wherein, control circuit 12 and 14 operation difference are that switch Sb 1 receives voltage Vf2 (promptly being ceiling voltage VDD), make that the integration differential voltage Δ V2 when control circuit 14 is carried out integration operation is a negative value, so that the integral voltage Vx self termination accurate Vx_Tr in position drops to the starting potential (position that promptly is reference voltage Vr is accurate) of integral voltage Vx.Wherein, difference voltage Δ V2 satisfies:

$\mathrm{\&Delta;<figure-callout\; id="2"\; label="V"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">V</figure-callout>}2=-\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}}$

According to above-mentioned derivation as can be known, in integration operation, the integral voltage Vx difference voltage Δ V2 that descends.TP_IT2 for example comprises the cycle of M clock signal CK_b1 between the integration period of present embodiment, and in the cycle of each clock signal CK_a1, control circuit 14 is carried out similar integration operation to integrator circuit 16, and M is a natural number.So, by carrying out above-mentioned integration operation repeatedly M time, integral voltage Vx being dropped to the start bit standard from the accurate Vx_Tr of its stop bit, promptly is to satisfy equation:

$\mathrm{Vr}=\mathrm{Vx}\_\mathrm{Tr}+M\&times;\mathrm{\&Delta;<figure-callout\; id="2"\; label="V"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">V</figure-callout>}2=\mathrm{Vr}+N\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cx"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cx</figure-callout>}}{2\&times;\mathrm{Ci}}+(-M\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}})$

Can obtain the relational expression of testing capacitance Cx and numerical value M, N and known capacitance Cc after the arrangement:

$N\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cx"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cx</figure-callout>}}{2\&times;\mathrm{Ci}}=M\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}}\&DoubleRightArrow;\mathrm{Cx}=\frac{M}{N}\mathrm{Cc}$

So, processor circuit 18 also tries to achieve according to the capacitance of numerical value M, N and known capacitance Cc the capacitance of testing capacitance Cx according to aforesaid equation.

Please refer to Fig. 3, it shows the detailed block diagram of the processor circuit 18 of Fig. 1.In more detail, processor circuit 18 comprises logical circuit 18a, comparator circuit 18b, pierce circuit 18c, counter circuit 18d, fastens lock device circuit 18e and computing circuit 18f.Logical circuit 18a comprises logical block 18a1 and 18a2.Logical block 18a2 produces clock signal CK_a1 and CK_a2 in order to the control signal CS2 in response to activation, and produces clock signal CK_b1 and CK_b2 in order to the control signal CS3 in response to activation.

For instance, the detailed block diagram of logical block 18a2 as shown in Figure 4.Logical block 18a2 comprises with (And Gate) _ 1, with door _ 2, reaches and door _ 4 with door _ 3, it receives control signal CS2 and clock signal CK_1, control signal CS2 and clock signal CK_2, control signal CS3 and clock signal CK_1 and control signal CS3 and clock signal CK_2 respectively, and exports clock signal CK_a1, CK_a2, CK_b1 and CK_b2 accordingly.Wherein, clock signal CK_1 and CK_2 are produced by pierce circuit 18c vibration.

Logical block 18a1 produces control signal CS1 in order to TP_PS during voltage is set, and with control integrator circuit 16 voltage of charging voltage Vx is set at reference voltage Vr.Logical block 18a1 produces the control signal CS2 and the CS3 of activation respectively in order among TP_IT1 between integration period and the TP_IT2, produces clock signal CK_a1 and CK_a2 and CK_b1 and CK_b2 with steering logic unit 18a2.Logical block 18a1 also corresponds to the cycle length of what clock signal CK_1 in order to TP_IT2 between the record integration period.

In the present embodiment, logical block 18a1 is in order to the control signal CS3 of decision and the initial time point Tx1 generation activation of TP_IT2 between integration period.Whether logical block 18a1 also triggers in order to the metrology operation incident, and decides the termination time point Tx2 of TP_IT2 between integration period in response to this Action Events.

For instance, this Action Events is the incident of activation for the control signal CS4 that comparator circuit 18b produces.Comparator circuit 18b is accurate in order to the position of reception and comparison integral voltage Vx and reference voltage Vr, and produces control signal CS4 accordingly.As integral voltage Vx during greater than reference voltage Vr, control signal CS4 is a disabled.When the position of integral voltage Vx standard during basically less than reference voltage Vr, comparator circuit 18b activation control signal CS4.So, via the Action Events that response comparator circuit 18b triggers, logical block 18a1 can determine the termination time point Tx2 of TP_IT2 between integration period effectively.

In the present embodiment, logical block 18a1 is for example in order to activation drive signal En between time point Tx1 and Tx2, and increase progressively 1 counting operation the cycle length (equaling the cycle of clock signal CK_b1) of coming actuation counter circuit 18d to carry out every a clock signal CK_1.So, the processor circuit 18 of present embodiment can obtain numerical value M by the counting operation of counter circuit 18d.

For instance, counter circuit 18d is an i digit counter circuit, and its counting produces and i bit data Bit_1～Bit_i of output numerical value M locks device circuit 18e to fastening.Fasten lock device circuit 18e in order to receive and recorded bit data Bit_1～Bit_i.Arithmetic element 18f obtains numerical value M according to the bit data Bit_1～Biti that fastens lock device circuit 18e storage, and obtains the capacitance of testing capacitance Cx according to the relational expression of aforementioned testing capacitance Cx and numerical value M, N and known capacitance Cc.

In the present embodiment, logical block 18a1 produces in order and fastens lock signal Srdy and reset signal Srst also in order to after the TP_IT2 between integration period.So, fasten lock device circuit 18e and fasten the output valve of pinning counter circuit 18d in response to fastening lock signal Srdy.Fasten lock device circuit 18e finish fasten the operation of pinning this output valve after, counter circuit 18d is in response to reset signal Srst its count value of resetting.Fasten lock device circuit 18e and counter circuit 18d finish fasten latching operation and the operation of resetting after, processor circuit 18 can carry out the metrology operation of testing capacitance next time.

The logical block 18a1 of present embodiment is also in order to the record numerical value of N, and decides TP_IT1 between integration period to comprise the cycle of what clock signal CK_1 according to numerical value of N.In the present embodiment, numerical value of N (promptly being the number in the cycle of the clock signal CK_a1 that comprises among the TP_IT1 between integration period) is for adjustable, by adjusting numerical value of N, the user can make the capacitance value measuring circuit 10 of present embodiment be applicable to the testing capacitance Cx that measures different capacitance scopes.

Furthermore, according to equation:

$\mathrm{Cx}=\frac{M}{N}\mathrm{Cc}$

As can be known, the ratio of the ratio of numerical value M and N and the capacitance between testing capacitance Cx and known capacitance Cc is relevant.Because the numerical range of numerical value M is fixing (subtracting 1 to the i+1 power of numerical value 2 between numerical value 0), the user adjusts capacitance value measuring circuit 10, so that it is applicable to the metrology operation of different testing capacitance Cx via the size of adjustment numerical value of N.For instance, when numerical value of N is set to x/one times of the maximal value Mmax of numerical value M, according to equation:

$\mathrm{Cx}=\frac{M}{N}\&times;\mathrm{Cc}\&DoubleRightArrow;\frac{\mathrm{Cx}}{\mathrm{Cc}}=\frac{M}{M\max /x}\&le;\frac{M\max }{M\max /x}=x$

Capacitance value measuring circuit 10 can be carried out capacitance value measuring to the x testing capacitance Cx doubly that capacitance is less than or equal to the capacitance of known capacitance Cc, and x is a real number.Maximal value Mmax equals 2 i+1 power and subtracts 1.So, the multiple relation that the capacitance of the testing capacitance Cx that the visual desire of user measures and known capacitance Cc are about decides numerical value of N.

In the present embodiment, though only the situation that is higher than the start bit standard (equal reference voltage Vr position accurate) of integral voltage Vx with the accurate Vx_Tr of the stop bit of integral voltage Vx is that example explains, yet the accurate Vx_Tr of the stop bit of present embodiment is not limited to be higher than the start bit standard.In another example, the accurate Vx_Tr of stop bit is lower than the start bit standard.So between first and second integration period among integration TP_IT1 and the TP_IT2, integral voltage Vx drops to the accurate Vx_Tr of stop bit by the start bit standard respectively, and rises to the start bit standard by the accurate Vx_Tr of stop bit.

In the present embodiment, though be that example explains only to control the situation that integrator circuit 16 carries out integration operation by control circuit 12 and 14 in order after the TP_PS during voltage is set, yet the capacitance value measuring circuit 10 of present embodiment is not limited to control integrator circuit 16 by control circuit 12 and 14 in order and operates.In another example, the capacitance value measuring circuit 10 of present embodiment also can be carried out integration operation by control circuit 14 control integrator circuits 16 earlier, carries out integration operation by control circuit 12 control integrator circuits 16 more afterwards, as shown in Figure 5.

The capacitance value measuring circuit of present embodiment uses testing capacitance and known capacitance that charging voltage is set at the stop bit standard from the start bit standard respectively, and charging voltage self termination position standard is set at the start bit standard, and try to achieve the capacitance of testing capacitance according to the capacitance of clock pulse amount of cycles corresponding and known capacitance with aforementioned charge and discharge operation.So, the user can adjust the numerical range of the scalable testing capacitance of capacitance value measuring circuit of present embodiment via the clock pulse amount of cycles of adjusting the charging operations correspondence.So, than traditional capacitance value measuring circuit, the capacitance value measuring circuit of present embodiment has the advantage that can flexibly measure the testing capacitance of different numerical ranges, and the design alternative of another kind of capacitance value measuring circuit can be provided effectively.

In addition, a plurality of clock pulses of the capacitance value measuring circuit of present embodiment between integration period are carried out repeatedly integration operation in the cycle.So, the capacitance value measuring circuit of present embodiment can be passed through the higher integration operation number of times of accumulated quantity, offset the influence of circuit noise to the difference voltage in each time integration operation, and reduce the influence of noise to final scores accumulated voltage, make the capacitance value measuring circuit of present embodiment carry out capacitance value measuring to testing capacitance exactly.

Second embodiment

The capacitance value measuring circuit of present embodiment realizes on-off circuit corresponding in two control circuits of present embodiment with the on-off circuit that comprises four switches.Please refer to Fig. 6, it shows the calcspar according to the capacitance value measuring circuit of second embodiment of the invention.Capacitance value measuring circuit 10 differences of the capacitance value measuring circuit of present embodiment and first embodiment are that the control circuit 22 and 24 of present embodiment has another kind of circuit design.

Control circuit 22 comprises on-off circuit SW1 ' and testing capacitance Cx, and wherein on-off circuit SW1 ' comprises switch S a3, Sa4, Sa5 and Sa6.The end of switch S a3 and Sa5 is coupled to first end of testing capacitance Cx, and the other end of switch S a3 and Sa5 receives voltage Vf2 and reference voltage Vr respectively.The end of switch S a4 and Sa6 is coupled to second end of testing capacitance, and the other end of switch S a4 and Sa6 receives reference voltage Vr respectively and is coupled to the negative input end of operational amplifier OP2.Voltage Vf2 for example equals ceiling voltage VDD, and reference voltage Vr for example equals 1/2nd ceiling voltage VDD.

Switch S a3 and Sa4 make first and second end of testing capacitance Cx receive voltage Vf2 and reference voltage Vr respectively in response to clock signal CK_a1 conducting during first child-operation.Switch S a5 and Sa6 be in response to clock signal CK_a2 conducting during second child-operation, makes first and second end of testing capacitance Cx receive reference voltage Vr respectively and be coupled to the negative input end of operational amplifier OP2.Because in during second child-operation, the node that second end of testing capacitance Cx and integrating capacitor Ci couple mutually (promptly being the negative input end of operational amplifier OP2) is a suspension joint, so the total electrical charge that testing capacitance Cx and integrating capacitor Ci store in during first child-operation be substantially equal to its during second child-operation in the total electrical charge of storage, promptly be to satisfy equation:

Cx×(Vr-Vf2)+Ci×[Vr-Vx(t0)]＝Cx×(Vr-Vr)+Ci×[Vr-Vx(t1)]

Derivation can obtain the result identical with first embodiment according to following formula:

$\mathrm{Vx}\left(t1\right)=\frac{\mathrm{Cx}+\mathrm{Ci}}{\mathrm{Ci}}\&times;\mathrm{Vr}=\frac{\mathrm{VDD}\&times;(\mathrm{Cx}+\mathrm{Ci})}{2\&times;\mathrm{Ci}}$

$\mathrm{\&Delta;<figure-callout\; id="1"\; label="V"\; filenames="A20081008989200351.png,A20081008989200361.png"\; state="\{\{state\}\}">V</figure-callout>}1=\mathrm{Vx}\left(t1\right)-\mathrm{Vx}\left(t0\right)=\frac{\mathrm{VDD}\&times;(\mathrm{Cx}+\mathrm{Ci})}{2\&times;\mathrm{Ci}}-\mathrm{Vr}=\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cx"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cx</figure-callout>}}{2\&times;\mathrm{Ci}}$

$\mathrm{Vx}\_\mathrm{Tr}=\mathrm{Vr}+N\&times;\mathrm{\&Delta;<figure-callout\; id="1"\; label="V"\; filenames="A20081008989200351.png,A20081008989200361.png"\; state="\{\{state\}\}">V</figure-callout>}1=\mathrm{Vr}+N\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cx"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cx</figure-callout>}}{2\&times;\mathrm{Ci}}$

Control circuit 24 comprises on-off circuit SW2 ' and known capacitance Cc, and wherein on-off circuit SW2 ' comprises switch Sb 3, Sb4, Sb5 and Sb6.The operation of control circuit 24 can be analogized according to the operation of the control circuit 14 of the control circuit 22 and first embodiment and obtained.According to above narration as can be known, the capacitance value measuring circuit of present embodiment has the testing capacitance that can flexibly measure different numerical ranges, the design alternative that another kind of capacitance value measuring circuit can be provided effectively and can carry out the advantage of capacitance value measuring exactly to testing capacitance.

The 3rd embodiment

The capacitance value measuring circuit of present embodiment realizes integrator circuit with the series circuit of integrating capacitor and switch.Please refer to Fig. 7, it shows the calcspar according to the capacitance value measuring circuit of third embodiment of the invention.The capacitance value measuring circuit 30 of present embodiment is that with the capacitance value measuring circuit 10 of first and second embodiment and 20 differences the integrator circuit 36 in capacitance value measuring circuit 30 omits the use of operational amplifier, and directly realizes with the series circuit of switch S c ' with integrating capacitor Ci '.Integrating capacitor Ci ' couples mutually with the end of switch S c ', and its voltage that couples node is integral voltage Vx, and integrating capacitor Ci ' receives voltage Vf1 and Vr respectively with the other end of switch S c '.For instance, voltage Vf1 and Vr are respectively 1/2nd of ground voltage and ceiling voltage VDD.The control circuit 32 of present embodiment with 34 with the capacitance value measuring circuit 10 of first embodiment in corresponding control circuit 12 and 14 differences be that the voltage that on-off circuit SW1 " with SW2 " receives changes voltage Vf2 and Vf1 respectively into.

Please refer to Fig. 8, it shows the coherent signal sequential chart of the capacitance value measuring circuit 30 of Fig. 7.Because the use of having omitted operational amplifier in integrator circuit 36, the difference voltage Δ V1 of the increase and decrease of integral voltage Vx in each time integration operation of present embodiment and Δ V2 are non-for fixing, and it is relevant to be essentially geometric progression.

In more detail, between integration period among the TP_IT1, the integral voltage Vx (t1) after initial integral voltage Vx (t0) (equaling reference voltage Vr) and the integration operation for the first time satisfies:

Cx×(Vf2-Vf1)+Ci×[Vx(t0)-Vf1]＝Cx×(Vx(t1)-Vf1)+Ci×[Vx(t1)-Vf1]

Wherein voltage Vf1 and Vf2 are respectively ground voltage and ceiling voltage VDD.So, arrangement obtains according to aforesaid equation:

$\mathrm{Vx}\left(t1\right)=\frac{\mathrm{<figure-callout\; id="2"\; label="VDD"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">VDD</figure-callout>}}{2}+\frac{\mathrm{Cx}\&times;\mathrm{<figure-callout\; id="2"\; label="VDD"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">VDD</figure-callout>}}{2\&times;(\mathrm{Cx}+\mathrm{Ci})}$

Derivation obtains according to similar methods:

$\mathrm{Vx}\left(t2\right)=\frac{\mathrm{<figure-callout\; id="2"\; label="VDD"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">VDD</figure-callout>}}{2}+\frac{\mathrm{Cx}\&times;\mathrm{<figure-callout\; id="2"\; label="VDD"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">VDD</figure-callout>}}{2\&times;(\mathrm{Cx}+\mathrm{Ci})}+\frac{\mathrm{Cx}\&times;\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Ci"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Ci</figure-callout>}}{2\&times;{(\mathrm{Cx}+\mathrm{Ci})}^2}$

Analogize according to above-mentioned condition, suppose that the control circuit 32 of present embodiment and integrator circuit 36 carry out N integration operation among the TP_IT1 between integration period, the integral voltage Vx (tN) after N the integration operation that obtains during the TP_IT1 termination between integration period equals:

$\mathrm{Vx}\left(\mathrm{tN}\right)=\frac{\mathrm{<figure-callout\; id="2"\; label="VDD"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">VDD</figure-callout>}}{2}+\underset{x=1}{\overset{N}{\mathrm{\&Sigma;}}}\frac{\mathrm{VDD}\&times;\mathrm{Cx}\&times;{\mathrm{Ci}}^{x-1}}{2\&times;{(\mathrm{Cx}+\mathrm{Ci})}^x}$

Similarly, suppose that the control circuit 34 of present embodiment and integrator circuit 36 carry out M integration operation among the TP_IT2 between integration period, the integral voltage Vx (tM) after M the integration operation that obtains during the TP_IT2 termination between integration period equals:

$\mathrm{Vx}\left(\mathrm{tM}\right)=[\frac{\mathrm{<figure-callout\; id="2"\; label="VDD"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">VDD</figure-callout>}}{2}+\underset{x=1}{\overset{N}{\mathrm{\&Sigma;}}}\frac{\mathrm{VDD}\&times;\mathrm{Cx}\&times;{\mathrm{Ci}}^{x-1}}{{(\mathrm{Cx}+\mathrm{Ci})}^x}]\&times;[1-\underset{y=1}{\overset{M}{\mathrm{\&Sigma;}}}\frac{\mathrm{Cc}\&times;{\mathrm{Ci}}^{y-1}}{{(\mathrm{Cc}+\mathrm{Ci})}^y}]\&cong;\frac{\mathrm{<figure-callout\; id="2"\; label="VDD"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">VDD</figure-callout>}}{2}$

Derivation obtains the relational expression of testing capacitance Cx, known capacitance Cc, integrating capacitor Ci, numerical value of N and M according to following formula:

$\underset{x=1}{\overset{N}{\mathrm{\&Sigma;}}}\frac{\mathrm{Cx}\&times;{\mathrm{Ci}}^{x-1}}{{(\mathrm{Cx}+\mathrm{Ci})}^x}\&cong;\frac{\underset{y=1}{\overset{M}{\mathrm{\&Sigma;}}}\frac{\mathrm{Cc}\&times;{\mathrm{Ci}}^{y-1}}{{(\mathrm{Cc}+\mathrm{Ci})}^y}}{1-\underset{y=1}{\overset{M}{\mathrm{\&Sigma;}}}\frac{\mathrm{Cc}\&times;{\mathrm{Ci}}^{y-1}}{{(\mathrm{Cc}+\mathrm{Ci})}^y}}$

The processor circuit 38 of present embodiment stores the numerical relation of testing capacitance Cx and known capacitance Cc, integrating capacitor Ci ', numerical value of N and the M of aforesaid equation according to table look-up (Look-up Table).So, the capacitance value measuring circuit 30 of present embodiment also can be tried to achieve the capacitance of testing capacitance Cx effectively.

In the another one example, work as condition:

Ci＞＞Cx；Ci＞＞Cc； $M\&times;\frac{\mathrm{Cc}}{\mathrm{Ci}}<<1$

All under the situation of Man Zuing, the above-mentioned relation formula can be reduced to:

$\underset{x=1}{\overset{N}{\mathrm{\&Sigma;}}}\frac{\mathrm{Cx}}{\mathrm{Ci}}\&cong;\frac{\underset{y=1}{\overset{M}{\mathrm{\&Sigma;}}}\frac{\mathrm{Cc}}{\mathrm{Ci}}}{1-\underset{y=1}{\overset{M}{\mathrm{\&Sigma;}}}\frac{\mathrm{Cc}}{\mathrm{Ci}}}\&DoubleRightArrow;N\frac{\mathrm{Cx}}{\mathrm{Ci}}\&cong;\frac{M\&times;\frac{\mathrm{Cc}}{\mathrm{Ci}}}{1-M\&times;\frac{\mathrm{Cc}}{\mathrm{Ci}}}\&DoubleRightArrow;N\&times;\frac{\mathrm{Cx}}{\mathrm{Ci}}\&cong;M\&times;\frac{\mathrm{Cc}}{\mathrm{Ci}}\&DoubleRightArrow;\mathrm{Cx}=\frac{M}{N}\mathrm{Cc}$

So, in this example, the capacitance value measuring circuit 30 of present embodiment also can be derived via the relational expression substantially the same with first and second embodiment and be obtained the capacitance of testing capacitance Cx.According to above narration as can be known, the capacitance value measuring circuit of present embodiment has the testing capacitance that can flexibly measure different numerical ranges, the design alternative that another kind of capacitance value measuring circuit can be provided effectively and can carry out the advantage of capacitance value measuring exactly to testing capacitance.

The 4th embodiment

The capacitance value measuring circuit of present embodiment realizes in order to the discharge control circuit of integration operation of control integrator circuit with integrating resistor and switch.Please refer to Fig. 9 and Figure 10, Fig. 9 shows the calcspar according to the capacitance value measuring circuit of fourth embodiment of the invention, and Figure 10 shows the coherent signal sequential chart of the capacitance value measuring circuit of Fig. 9.The control circuit 44 that capacitance value measuring circuit 30 differences of the capacitance value measuring circuit of present embodiment and the 3rd embodiment are present embodiment replaces known capacitance Cc and on-off circuit SW2 among the 3rd embodiment with known resistance Rc and switch Sb 7 " circuit structure.One end of known resistance Rc and switch Sb 7 couples mutually, and the other end receives voltage Vf1 respectively and is coupled to coupling a little of integrating capacitor Ci ' and switch S c '.Wherein voltage Vf1 for example is a ground voltage.Switch Sb 7 is controlled by control signal CS3 and operates.

Among the TP_IT2, control signal CS3 is activation, with actuating switch Sb7 between integration period.So, control circuit 44 forms discharge path basically, and so that integral voltage Vx is discharged, and the curve of integral voltage Vx is continuous capacitance resistance discharge curve.Suppose that the control circuit 42 of present embodiment and integrator circuit 46 carry out N integration operation among the TP_IT1 between integration period, the integral voltage Vx (tN) after N the integration operation that obtains during the TP_IT1 termination between integration period equals:

$\mathrm{Vx}\left(\mathrm{tN}\right)=\frac{\mathrm{<figure-callout\; id="2"\; label="VDD"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">VDD</figure-callout>}}{2}+\underset{x=1}{\overset{N}{\mathrm{\&Sigma;}}}\frac{\mathrm{VDD}\&times;\mathrm{Cx}\&times;{\mathrm{Ci}}^{x-1}}{2\&times;{(\mathrm{Cx}+\mathrm{Ci})}^x}$

Similarly, suppose that the control circuit 44 of present embodiment and integrator circuit 46 carry out M integration operation among the TP_IT2 between integration period, the integral voltage Vx (tM) after M the integration operation that obtains during the TP_IT2 termination between integration period equals:

$\mathrm{Vx}\left(\mathrm{tM}\right)=\mathrm{Vx}\left(\mathrm{tN}\right)\&times;e^{-\frac{M\&times;T_{\mathrm{CLK}}}{\mathrm{Rc}\&times;(\mathrm{Cx}+\mathrm{Ci})}}\&cong;\frac{\mathrm{<figure-callout\; id="2"\; label="VDD"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">VDD</figure-callout>}}{2}$

T wherein _CLKBe the cycle of clock signal CK_1.Can derive according to following formula and to obtain the relational expression of testing capacitance Cx and numerical value M, N and known capacitance Cc:

$\underset{x=1}{\overset{N}{\mathrm{\&Sigma;}}}\frac{\mathrm{Cx}\&times;{\mathrm{Ci}}^{x-1}}{{(\mathrm{Cx}+\mathrm{Ci})}^x}\&cong;e^{\frac{M\&times;T_{\mathrm{CLK}}}{\mathrm{Rc}\&times;(\mathrm{Cx}+\mathrm{Ci})}}-1$

With the 3rd embodiment similarly, testing capacitance Cx that the processor circuit of present embodiment 48 stores aforesaid equation according to tabling look-up and the numerical relation of known resistance Rc, integrating capacitor Ci ', numerical value of N and M.So, the capacitance value measuring circuit 40 of present embodiment also can be tried to achieve the capacitance of testing capacitance Cx effectively.

In the another one example, work as condition:

Ci＞＞Cx and M * T _CLK＜＜Rc * Ci

When satisfying, the relational expression of above-mentioned testing capacitance Cx and known resistance Rc, integrating capacitor Ci ', numerical value of N and M can be reduced to:

$N\&times;\mathrm{Cx}=\frac{M\&times;T_{\mathrm{CLK}}}{\mathrm{Rc}}\&DoubleRightArrow;\mathrm{Cx}=\frac{M\&times;T_{\mathrm{CLK}}}{N\&times;\mathrm{Rc}}$

So, in this example, the capacitance value measuring circuit 40 of present embodiment also can be derived via the relational expression substantially the same with first and second embodiment and be obtained the capacitance of testing capacitance Cx.According to above narration as can be known, the capacitance value measuring circuit of present embodiment has the testing capacitance that can flexibly measure different numerical ranges, the design alternative that another kind of capacitance value measuring circuit can be provided effectively and can carry out the advantage of capacitance value measuring exactly to testing capacitance.

The 5th embodiment

The capacitance value measuring circuit of present embodiment has error correction circuit, in order to operational amplifier in the capacitance value measuring circuit and comparer are carried out offset voltage (Offset Voltage) correction.Please refer to Figure 11 and 12, Figure 11 shows the calcspar according to the capacitance value measuring circuit of fifth embodiment of the invention, and Figure 12 shows the coherent signal sequential chart of the capacitance value measuring circuit of Figure 11.

Capacitance value measuring circuit 10 differences of the capacitance value measuring circuit 50 of present embodiment and first embodiment are also to comprise switch Sb 8 and Sb9 in the control circuit 54 of present embodiment, and the processor circuit 58 in the capacitance value measuring circuit 50 also comes gauge tap Sb8, Sb9, Sb1 and Sb2 respectively in order to produce control signal CS5, CS6, clock signal CK_c1 and CK_c2 among the TP_AJ during proofreading and correct.

Before the TP_AJ, processor circuit 58 also produces control signal CS1 during proofreading and correct, to set integral voltage Vx near reference voltage Vr.Among the TP_AJ, clock signal CK_c1 and CK_c2 periodically switch between high levels and low level during proofreading and correct, with periodically actuating switch Sb1 and Sb2.Clock signal CK_c1 and CK_c2 be inversion signal each other each other, and its frequency equals the frequency of clock signal CK_1.

TP_AJ comprises TP_AJ1, TP_AJ2 and TP_AJ3 during the syndrome during the correction.Among the TP_AJ1, control signal CS5 is activation, with actuating switch Sb8 during syndrome.So, among the TP_AJ1, the control circuit 12 among the control circuit 54 and first embodiment has close operation during syndrome, so that integral voltage Vx is risen to the accurate Vx_Tr of stop bit from its start bit standard (position that equals reference voltage Vr is accurate ).Control circuit 54 and 12 differences are that control circuit 54 comes integral voltage Vx is carried out integration operation via known capacitance Cc, and so, difference voltage Δ V3 and the stop bit accurate Vx_Tr of integral voltage Vx in each time integration operation satisfies equation respectively:

$\mathrm{\&Delta;V}3=\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}}$

$\mathrm{Vx}\_\mathrm{Tr}=\mathrm{Vx}\left(t0\right)+N^{\&prime;}\&times;\mathrm{\&Delta;V}3=\mathrm{Vx}\left(t0\right)+N^{\&prime;}\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}}$

Wherein, Vx (t0) is during for the correct operation of integral voltage Vx TP_AJ1 and TP_AJ2 during not carrying out syndrome, the initial value of integral voltage Vx.

Among the TP_AJ2, control signal CS6 is activation, with actuating switch Sb9 during syndrome.So, among the TP_AJ2, the control circuit 14 among the control circuit 54 and first embodiment has close operation during syndrome, so that the accurate Vx_Tr in integral voltage Vx self termination position is descended.So, the final integral voltage Vx (tM) after the difference voltage Δ V4 of integral voltage Vx in each time integration operation and the inferior integration operation of process M ' satisfies equation respectively:

$\mathrm{\&Delta;V}4=-\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}}$

$\mathrm{Vt}\left(\mathrm{tM}\right)=\mathrm{Vx}\_\mathrm{Tr}+M^{\&prime;}\&times;\mathrm{\&Delta;V}4=\mathrm{Vx}\left(t0\right)+N^{\&prime;}\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}}+(-M^{\&prime;}\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}})$

$\&DoubleRightArrow;\mathrm{Vx}\left(\mathrm{tM}\right)-\mathrm{Vx}\left(t0\right)=[(N^{\&prime;}-M^{\&prime;})\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}}]$

At operational amplifier OP3 and comparator circuit 58b is under the ideal situation, and integral voltage Vx (t0) and final integral voltage Vx (tM) are equal to reference voltage Vr, and numerical value M ' and N ' are for equating basically.Yet when having deviation voltage to exist between the two ends of the positive-negative input end of operational amplifier OP3 or comparator circuit 58b, numerical value M ' and N ' are unequal.For instance, when the negative input end that just reaches of operational amplifier OP3 has deviation voltage Vof1, when the two ends of comparator circuit 58b had bias voltage Vof2, integral voltage Vx (t0) and final integral voltage Vx (tM) equaled respectively:

Vx(t0)＝Vr+Vof1

Vx(tM)＝Vr-Vof2

Above-mentioned integral voltage Vx this moment (t0) is rewritten as with the relational expression of final integral voltage Vx (tM):

$\mathrm{Vt}\left(\mathrm{tM}\right)-\mathrm{Vx}\left(t0\right)=(\mathrm{Vr}+\mathrm{Vof}1)-(\mathrm{Vr}-\mathrm{Vof}2)=[(N^{\&prime;}-M^{\&prime;})\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}}]$

$\&DoubleRightArrow;\mathrm{<figure-callout\; id="1"\; label="Vof"\; filenames="A20081008989200351.png,A20081008989200361.png"\; state="\{\{state\}\}">Vof</figure-callout>}1+\mathrm{<figure-callout\; id="2"\; label="Vof"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Vof</figure-callout>}2=[(N^{\&prime;}-M^{\&prime;})\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}}]=D\&times;\frac{\mathrm{VDD}\&times;\mathrm{<figure-callout\; id="2"\; label="Cc"\; filenames="A20081008989200371.png,A20081008989200372.png"\; state="\{\{state\}\}">Cc</figure-callout>}}{2\&times;\mathrm{Ci}}$

So, can obtain the difference D corresponding with the Vof2 sum by aforesaid operations with deviation voltage Vof1.When normal running backward,, can carry out deviation voltage to operational amplifier OP3 and proofread and correct by numerical value M and the difference D addition that record is obtained.

In the present embodiment, though only in the control circuit 54 with capacitance value measuring circuit 50 switch Sb 8 and Sb9 are set additionally, with the situation of carrying out the deviation voltage correct operation is that example explains, yet the control circuit 54 of present embodiment is not limited to have the structure that goes out as shown in figure 11.In another realizes example, control circuit 54 ' by known capacitance Cc, switch Sb 3 ', Sb4 ', Sb5 ', Sb6 ', Sb8 ' and Sb9 ' realization, as shown in figure 13.Wherein, switch Sb 3 ' and Sb4 ' be controlled by clock signal CK_c1, switch Sb 5 ' and Sb6 ' be controlled by clock signal CK_c2.So, capacitance value measuring circuit 50 ' also can be carried out the operation that deviation voltage is proofreaied and correct with comparator circuit 58b ' to the operational amplifier OP3 ' of its inside.

In the present embodiment, though only the situation that is higher than the start bit standard (equal reference voltage Vr position accurate) of integral voltage Vx with the accurate Vx_Tr of the stop bit of integral voltage Vx is that example explains, yet the accurate Vx_Tr of the stop bit of present embodiment is not limited to be higher than the start bit standard.In another example, the accurate Vx_Tr of stop bit is lower than the start bit standard.So, difference voltage Δ V3 and Δ V4 are respectively negative real number and arithmetic number, and during syndrome among TP_AJ1 and the TP_AJ2, integral voltage Vx drops to the accurate Vx_tr of stop bit by the start bit standard respectively, and rises to the start bit standard by the accurate Vx_Tr of stop bit.

According to above narration as can be known, the capacitance value measuring circuit of present embodiment has the testing capacitance that can flexibly measure different numerical ranges, the design alternative that another kind of capacitance value measuring circuit can be provided effectively and can carry out the advantage of capacitance value measuring exactly to testing capacitance.

In addition, the capacitance value measuring circuit of present embodiment also has and can carry out the advantage that bias voltage is proofreaied and correct to the operational amplifier and the comparator circuit of inside.

In sum, though the present invention with preferred embodiment disclosure as above, yet it is not in order to limit the present invention.The ordinary technical staff in the technical field of the invention under the situation that does not break away from the spirit and scope of the present invention, should make various changes and modification.Therefore, protection scope of the present invention should be with appended being as the criterion that claim was limited subsequently.

The primary clustering symbol description

10,20,30,40,50,50 ': capacitance value measuring circuit

12,14,22,24,32,34,42,44,54,54 ': control circuit

SW1, SW2, SW1 ', SW2 ', SW1 ", SW2 ": on-off circuit

16,36,46: integrator circuit

18,28,38,48,58,58 ': processor circuit

18a: logic circuit

18a1,18a2: logical block

18b, 58b, 58b ': comparator circuit

18c: pierce circuit

18d: counter circuit

18e: fasten lock device circuit

18f: computing circuit

OP1, OP2, OP3, OP3 ': operational amplifier

Sa1, Sa2, Sb1, Sb2, Sa3, Sa4, Sa5, Sa6, Sb3, Sb4, Sb5, Sb6, Sb7, Sb8, Sb9, Sb3 ', Sb4 ', Sb5 ', Sb6 ', Sb8 ', Sb9 ', Sc, Sc ': switch

Cx: testing capacitance Cc: known capacitance

Ci, Ci ': integrating capacitor ndo: output terminal

With door _ 1～with the door _ 4: with door Rc: known resistance

Nd1, nd2: node.

Claims (10)

1. capacitance value measuring circuit comprises:

Integrator circuit has input end and output terminal, has integral voltage on the described output terminal, and described integrator circuit is in order to be set at the start bit standard with described integral voltage in control signal is during voltage is set;

First control circuit, comprise first output terminal and testing capacitance, described first output terminal is electrically connected at described input end, described first control circuit is in order to the voltage at least one end that switches described testing capacitance in response to first group of clock signal, and an end of described testing capacitance and described first input end are electrically connected, carry out voltage integrating meter with the described integrator circuit of control in during first integral, described integral voltage is adjusted into the stop bit standard from described start bit standard;

Second control circuit, comprise second output terminal and passive device, described passive device has the known features value, described second output terminal is electrically connected at described input end, described second control circuit is in order to the voltage at least one end that switches described passive device in response to second group of clock signal, and an end of described passive device and described second input end are electrically connected, carry out voltage integrating meter with the described integrator circuit of control in during second integral, be adjusted into described start bit standard from described stop bit standard with the position of described integral voltage is accurate; And

Processor circuit, in order to providing described first group and described second group of clock signal to drive described first and described second control circuit, and in order to according to described first and described second integral during time span and the described known features value capacitance that calculates described testing capacitance.

2. capacitance value measuring circuit according to claim 1, wherein, described first control circuit also comprises:

First on-off circuit, comprise first end, second end and the 3rd end, be coupled to respectively described testing capacitance first end, be coupled to described input end and receive first voltage, first end that described first on-off circuit makes described testing capacitance respectively in order to first state and second state in response to described first group of clock signal is coupled to described input end and makes first termination of described testing capacitance receive described first voltage.

3. capacitance value measuring circuit according to claim 1, wherein, described passive device is a known capacitance, described second control circuit also comprises:

The second switch circuit, comprise first end, second end and the 3rd end, be coupled to respectively described known capacitance first end, be coupled to described input end and receive second voltage, first end that described second switch circuit makes described known capacitance respectively in order to first state and second state in response to described second group of clock signal is coupled to described input end and makes first termination of described known capacitance receive described second voltage.

4. capacitance value measuring circuit according to claim 3, wherein, described second control circuit also comprises:

The 3rd on-off circuit, comprise first end, second end and the 3rd end, be coupled to second end, described second voltage of reception of described known capacitance respectively and receive tertiary voltage, described the 3rd on-off circuit provides extremely second end of described known capacitance of described second voltage and described tertiary voltage respectively in order to first state and second state that responds described second group of clock signal;

Wherein, the position standard of described second voltage is substantially equal to described start bit standard.

5. capacitance value measuring circuit according to claim 2, wherein, described first control circuit also comprises:

The 4th on-off circuit, comprise first end, second end and the 3rd end, be coupled to second end, described first voltage of reception of described testing capacitance respectively and receive the 4th voltage, described the 4th on-off circuit provides extremely second end of described testing capacitance of described first voltage and described the 4th voltage respectively in order to first state and second state in response to described first group of clock signal;

Wherein, the position standard of described first voltage is substantially equal to described start bit standard.

6. capacitance value measuring circuit according to claim 1, wherein, described passive device is a known resistance, described second control circuit also comprises:

The second switch circuit, comprise first end and second end, be coupled to first end of described known resistance respectively and be coupled to described input end, first end that first end that described second switch circuit makes described known resistance respectively in order to first state and second state in response to described second group of clock signal is coupled to described input end and makes described known resistance is suspension joint basically.

7. capacitance value measuring circuit according to claim 1, wherein, described first group and described second group of clock signal have the substantially the same clock pulse cycle, described first and described second integral during length comprise N described clock pulse cycle and M described clock pulse cycle basically respectively, described processor circuit calculates the capacitance of described testing capacitance according to the ratio of numerical value of N and M, and numerical value of N and M are the natural number greater than 1.

8. capacitance value measuring circuit comprises:

Integrator circuit has input end and output terminal, has integral voltage on the described output terminal, and described integrator circuit is in order to be set at the start bit standard with described integral voltage in control signal is during voltage is set;

First control circuit, comprise first output terminal and passive device, described passive device has the known features value, described first output terminal is electrically connected at described input end, described first control circuit is in order to the voltage at least one end that switches described passive device in response to first group of clock signal, and an end of described passive device and described first input end are electrically connected, carry out voltage integrating meter with the described integrator circuit of control in during first integral, to be adjusted into the stop bit standard from the start bit standard with the position of described integral voltage is accurate;

Second control circuit, comprise second output terminal and testing capacitance, described second output terminal is electrically connected at described input end, described second control circuit is in order to the voltage at least one end that switches described testing capacitance in response to second group of clock signal, and an end of described testing capacitance and described second input end are electrically connected, carry out voltage integrating meter with the described integrator circuit of control in during second integral, described integral voltage is adjusted into described start bit standard from described stop bit standard, and the capacitance of described testing capacitance is relevant with the difference of described termination and described start bit standard; And

Processor circuit, in order to providing described first group and described second group of clock signal to drive described first and described second control circuit, and in order to according to described first and described second integral during time span and the described known features value capacitance that calculates described testing capacitance.

9. capacitance value measuring method, be applied to capacitance value measuring circuit, described capacitance value measuring circuit comprises integrator circuit, has integral voltage on the output terminal of described integrator circuit, testing capacitance is electrically connected at the input end of described integrator, and described capacitance value measuring method comprises:

(a) switch voltage at least one end of described testing capacitance in response to first group of clock signal, to be adjusted into the stop bit standard from the start bit standard with the position of described integral voltage is accurate in during first integral;

(b) in response to being adjusted into described start bit standard from described stop bit standard with the position of described integral voltage is accurate during second group of clock signal is during second integral; And

(c) according to during described first, the described second integral and the computing of known features value obtain the capacitance of described testing capacitance.

10. capacitance value measuring method, be applied to capacitance value measuring circuit, described capacitance value measuring circuit comprises integrator circuit, has integral voltage on the output terminal of described integrator circuit, testing capacitance is electrically connected at the input end of described integrator circuit, and described capacitance value measuring method comprises:

(a) in first group of clock signal is during first integral, integral voltage is adjusted into the stop bit standard from the start bit standard;

(b) switch voltage at least one end of testing capacitance in response to second group of clock signal, to be adjusted into described start bit standard from described stop bit standard with the position of described integral voltage is accurate in during second integral; And

(c) according to during described first, the described second integral and the computing of known features value obtain the capacitance of described testing capacitance.

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